1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 /* 209 * When a Virtual Processor is scheduled to run on a HW thread, the 210 * hypervisor pushes its identifier in the OS CAM line. Emulate the 211 * same behavior under QEMU. 212 */ 213 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 214 { 215 uint8_t nvt_blk; 216 uint32_t nvt_idx; 217 uint32_t nvt_cam; 218 219 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 220 221 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 222 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 223 } 224 225 static void spapr_xive_end_reset(XiveEND *end) 226 { 227 memset(end, 0, sizeof(*end)); 228 229 /* switch off the escalation and notification ESBs */ 230 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 231 } 232 233 static void spapr_xive_reset(void *dev) 234 { 235 SpaprXive *xive = SPAPR_XIVE(dev); 236 int i; 237 238 /* 239 * The XiveSource has its own reset handler, which mask off all 240 * IRQs (!P|Q) 241 */ 242 243 /* Mask all valid EASs in the IRQ number space. */ 244 for (i = 0; i < xive->nr_irqs; i++) { 245 XiveEAS *eas = &xive->eat[i]; 246 if (xive_eas_is_valid(eas)) { 247 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 248 } else { 249 eas->w = 0; 250 } 251 } 252 253 /* Clear all ENDs */ 254 for (i = 0; i < xive->nr_ends; i++) { 255 spapr_xive_end_reset(&xive->endt[i]); 256 } 257 } 258 259 static void spapr_xive_instance_init(Object *obj) 260 { 261 SpaprXive *xive = SPAPR_XIVE(obj); 262 263 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 264 TYPE_XIVE_SOURCE, &error_abort, NULL); 265 266 object_initialize_child(obj, "end_source", &xive->end_source, 267 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 268 &error_abort, NULL); 269 270 /* Not connected to the KVM XIVE device */ 271 xive->fd = -1; 272 } 273 274 static void spapr_xive_realize(DeviceState *dev, Error **errp) 275 { 276 SpaprXive *xive = SPAPR_XIVE(dev); 277 XiveSource *xsrc = &xive->source; 278 XiveENDSource *end_xsrc = &xive->end_source; 279 Error *local_err = NULL; 280 281 if (!xive->nr_irqs) { 282 error_setg(errp, "Number of interrupt needs to be greater 0"); 283 return; 284 } 285 286 if (!xive->nr_ends) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 /* 292 * Initialize the internal sources, for IPIs and virtual devices. 293 */ 294 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 295 &error_fatal); 296 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 297 &error_fatal); 298 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 299 if (local_err) { 300 error_propagate(errp, local_err); 301 return; 302 } 303 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 304 305 /* 306 * Initialize the END ESB source 307 */ 308 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 309 &error_fatal); 310 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 311 &error_fatal); 312 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 313 if (local_err) { 314 error_propagate(errp, local_err); 315 return; 316 } 317 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 318 319 /* Set the mapping address of the END ESB pages after the source ESBs */ 320 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 321 322 /* 323 * Allocate the routing tables 324 */ 325 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 326 xive->endt = g_new0(XiveEND, xive->nr_ends); 327 328 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 329 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 330 331 qemu_register_reset(spapr_xive_reset, dev); 332 333 /* TIMA initialization */ 334 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 335 "xive.tima", 4ull << TM_SHIFT); 336 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 337 338 /* 339 * Map all regions. These will be enabled or disabled at reset and 340 * can also be overridden by KVM memory regions if active 341 */ 342 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 343 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 344 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 345 } 346 347 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 348 uint32_t eas_idx, XiveEAS *eas) 349 { 350 SpaprXive *xive = SPAPR_XIVE(xrtr); 351 352 if (eas_idx >= xive->nr_irqs) { 353 return -1; 354 } 355 356 *eas = xive->eat[eas_idx]; 357 return 0; 358 } 359 360 static int spapr_xive_get_end(XiveRouter *xrtr, 361 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 362 { 363 SpaprXive *xive = SPAPR_XIVE(xrtr); 364 365 if (end_idx >= xive->nr_ends) { 366 return -1; 367 } 368 369 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 370 return 0; 371 } 372 373 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 374 uint32_t end_idx, XiveEND *end, 375 uint8_t word_number) 376 { 377 SpaprXive *xive = SPAPR_XIVE(xrtr); 378 379 if (end_idx >= xive->nr_ends) { 380 return -1; 381 } 382 383 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 384 return 0; 385 } 386 387 static int spapr_xive_get_nvt(XiveRouter *xrtr, 388 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 389 { 390 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 391 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 392 393 if (!cpu) { 394 /* TODO: should we assert() if we can find a NVT ? */ 395 return -1; 396 } 397 398 /* 399 * sPAPR does not maintain a NVT table. Return that the NVT is 400 * valid if we have found a matching CPU 401 */ 402 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 403 return 0; 404 } 405 406 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 407 uint32_t nvt_idx, XiveNVT *nvt, 408 uint8_t word_number) 409 { 410 /* 411 * We don't need to write back to the NVTs because the sPAPR 412 * machine should never hit a non-scheduled NVT. It should never 413 * get called. 414 */ 415 g_assert_not_reached(); 416 } 417 418 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 419 { 420 PowerPCCPU *cpu = POWERPC_CPU(cs); 421 422 return spapr_cpu_state(cpu)->tctx; 423 } 424 425 static const VMStateDescription vmstate_spapr_xive_end = { 426 .name = TYPE_SPAPR_XIVE "/end", 427 .version_id = 1, 428 .minimum_version_id = 1, 429 .fields = (VMStateField []) { 430 VMSTATE_UINT32(w0, XiveEND), 431 VMSTATE_UINT32(w1, XiveEND), 432 VMSTATE_UINT32(w2, XiveEND), 433 VMSTATE_UINT32(w3, XiveEND), 434 VMSTATE_UINT32(w4, XiveEND), 435 VMSTATE_UINT32(w5, XiveEND), 436 VMSTATE_UINT32(w6, XiveEND), 437 VMSTATE_UINT32(w7, XiveEND), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static const VMStateDescription vmstate_spapr_xive_eas = { 443 .name = TYPE_SPAPR_XIVE "/eas", 444 .version_id = 1, 445 .minimum_version_id = 1, 446 .fields = (VMStateField []) { 447 VMSTATE_UINT64(w, XiveEAS), 448 VMSTATE_END_OF_LIST() 449 }, 450 }; 451 452 static int vmstate_spapr_xive_pre_save(void *opaque) 453 { 454 if (kvm_irqchip_in_kernel()) { 455 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 456 } 457 458 return 0; 459 } 460 461 /* 462 * Called by the sPAPR IRQ backend 'post_load' method at the machine 463 * level. 464 */ 465 int spapr_xive_post_load(SpaprXive *xive, int version_id) 466 { 467 if (kvm_irqchip_in_kernel()) { 468 return kvmppc_xive_post_load(xive, version_id); 469 } 470 471 return 0; 472 } 473 474 static const VMStateDescription vmstate_spapr_xive = { 475 .name = TYPE_SPAPR_XIVE, 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .pre_save = vmstate_spapr_xive_pre_save, 479 .post_load = NULL, /* handled at the machine level */ 480 .fields = (VMStateField[]) { 481 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 483 vmstate_spapr_xive_eas, XiveEAS), 484 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 485 vmstate_spapr_xive_end, XiveEND), 486 VMSTATE_END_OF_LIST() 487 }, 488 }; 489 490 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 491 bool lsi, Error **errp) 492 { 493 SpaprXive *xive = SPAPR_XIVE(intc); 494 XiveSource *xsrc = &xive->source; 495 496 assert(lisn < xive->nr_irqs); 497 498 if (xive_eas_is_valid(&xive->eat[lisn])) { 499 error_setg(errp, "IRQ %d is not free", lisn); 500 return -EBUSY; 501 } 502 503 /* 504 * Set default values when allocating an IRQ number 505 */ 506 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 507 if (lsi) { 508 xive_source_irq_set_lsi(xsrc, lisn); 509 } 510 511 if (kvm_irqchip_in_kernel()) { 512 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 513 } 514 515 return 0; 516 } 517 518 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 519 { 520 SpaprXive *xive = SPAPR_XIVE(intc); 521 assert(lisn < xive->nr_irqs); 522 523 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 524 } 525 526 static Property spapr_xive_properties[] = { 527 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 528 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 529 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 530 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 531 DEFINE_PROP_END_OF_LIST(), 532 }; 533 534 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 535 PowerPCCPU *cpu, Error **errp) 536 { 537 SpaprXive *xive = SPAPR_XIVE(intc); 538 Object *obj; 539 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 540 541 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); 542 if (!obj) { 543 return -1; 544 } 545 546 spapr_cpu->tctx = XIVE_TCTX(obj); 547 548 /* 549 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they 550 * don't beneficiate from the reset of the XIVE IRQ backend 551 */ 552 spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); 553 return 0; 554 } 555 556 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 557 { 558 SpaprXive *xive = SPAPR_XIVE(intc); 559 560 if (kvm_irqchip_in_kernel()) { 561 kvmppc_xive_source_set_irq(&xive->source, irq, val); 562 } else { 563 xive_source_set_irq(&xive->source, irq, val); 564 } 565 } 566 567 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 568 { 569 SpaprXive *xive = SPAPR_XIVE(intc); 570 CPUState *cs; 571 572 CPU_FOREACH(cs) { 573 PowerPCCPU *cpu = POWERPC_CPU(cs); 574 575 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 576 } 577 578 spapr_xive_pic_print_info(xive, mon); 579 } 580 581 static void spapr_xive_class_init(ObjectClass *klass, void *data) 582 { 583 DeviceClass *dc = DEVICE_CLASS(klass); 584 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 585 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 586 587 dc->desc = "sPAPR XIVE Interrupt Controller"; 588 dc->props = spapr_xive_properties; 589 dc->realize = spapr_xive_realize; 590 dc->vmsd = &vmstate_spapr_xive; 591 592 xrc->get_eas = spapr_xive_get_eas; 593 xrc->get_end = spapr_xive_get_end; 594 xrc->write_end = spapr_xive_write_end; 595 xrc->get_nvt = spapr_xive_get_nvt; 596 xrc->write_nvt = spapr_xive_write_nvt; 597 xrc->get_tctx = spapr_xive_get_tctx; 598 599 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 600 sicc->claim_irq = spapr_xive_claim_irq; 601 sicc->free_irq = spapr_xive_free_irq; 602 sicc->set_irq = spapr_xive_set_irq; 603 sicc->print_info = spapr_xive_print_info; 604 } 605 606 static const TypeInfo spapr_xive_info = { 607 .name = TYPE_SPAPR_XIVE, 608 .parent = TYPE_XIVE_ROUTER, 609 .instance_init = spapr_xive_instance_init, 610 .instance_size = sizeof(SpaprXive), 611 .class_init = spapr_xive_class_init, 612 .interfaces = (InterfaceInfo[]) { 613 { TYPE_SPAPR_INTC }, 614 { } 615 }, 616 }; 617 618 static void spapr_xive_register_types(void) 619 { 620 type_register_static(&spapr_xive_info); 621 } 622 623 type_init(spapr_xive_register_types) 624 625 /* 626 * XIVE hcalls 627 * 628 * The terminology used by the XIVE hcalls is the following : 629 * 630 * TARGET vCPU number 631 * EQ Event Queue assigned by OS to receive event data 632 * ESB page for source interrupt management 633 * LISN Logical Interrupt Source Number identifying a source in the 634 * machine 635 * EISN Effective Interrupt Source Number used by guest OS to 636 * identify source in the guest 637 * 638 * The EAS, END, NVT structures are not exposed. 639 */ 640 641 /* 642 * Linux hosts under OPAL reserve priority 7 for their own escalation 643 * interrupts (DD2.X POWER9). So we only allow the guest to use 644 * priorities [0..6]. 645 */ 646 static bool spapr_xive_priority_is_reserved(uint8_t priority) 647 { 648 switch (priority) { 649 case 0 ... 6: 650 return false; 651 case 7: /* OPAL escalation queue */ 652 default: 653 return true; 654 } 655 } 656 657 /* 658 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 659 * real address of the MMIO page through which the Event State Buffer 660 * entry associated with the value of the "lisn" parameter is managed. 661 * 662 * Parameters: 663 * Input 664 * - R4: "flags" 665 * Bits 0-63 reserved 666 * - R5: "lisn" is per "interrupts", "interrupt-map", or 667 * "ibm,xive-lisn-ranges" properties, or as returned by the 668 * ibm,query-interrupt-source-number RTAS call, or as returned 669 * by the H_ALLOCATE_VAS_WINDOW hcall 670 * 671 * Output 672 * - R4: "flags" 673 * Bits 0-59: Reserved 674 * Bit 60: H_INT_ESB must be used for Event State Buffer 675 * management 676 * Bit 61: 1 == LSI 0 == MSI 677 * Bit 62: the full function page supports trigger 678 * Bit 63: Store EOI Supported 679 * - R5: Logical Real address of full function Event State Buffer 680 * management page, -1 if H_INT_ESB hcall flag is set to 1. 681 * - R6: Logical Real Address of trigger only Event State Buffer 682 * management page or -1. 683 * - R7: Power of 2 page size for the ESB management pages returned in 684 * R5 and R6. 685 */ 686 687 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 688 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 689 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 690 on same page */ 691 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 692 693 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 694 SpaprMachineState *spapr, 695 target_ulong opcode, 696 target_ulong *args) 697 { 698 SpaprXive *xive = spapr->xive; 699 XiveSource *xsrc = &xive->source; 700 target_ulong flags = args[0]; 701 target_ulong lisn = args[1]; 702 703 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 704 return H_FUNCTION; 705 } 706 707 if (flags) { 708 return H_PARAMETER; 709 } 710 711 if (lisn >= xive->nr_irqs) { 712 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 713 lisn); 714 return H_P2; 715 } 716 717 if (!xive_eas_is_valid(&xive->eat[lisn])) { 718 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 719 lisn); 720 return H_P2; 721 } 722 723 /* 724 * All sources are emulated under the main XIVE object and share 725 * the same characteristics. 726 */ 727 args[0] = 0; 728 if (!xive_source_esb_has_2page(xsrc)) { 729 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 730 } 731 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 732 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 733 } 734 735 /* 736 * Force the use of the H_INT_ESB hcall in case of an LSI 737 * interrupt. This is necessary under KVM to re-trigger the 738 * interrupt if the level is still asserted 739 */ 740 if (xive_source_irq_is_lsi(xsrc, lisn)) { 741 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 742 } 743 744 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 745 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 746 } else { 747 args[1] = -1; 748 } 749 750 if (xive_source_esb_has_2page(xsrc) && 751 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 752 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 753 } else { 754 args[2] = -1; 755 } 756 757 if (xive_source_esb_has_2page(xsrc)) { 758 args[3] = xsrc->esb_shift - 1; 759 } else { 760 args[3] = xsrc->esb_shift; 761 } 762 763 return H_SUCCESS; 764 } 765 766 /* 767 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 768 * Interrupt Source to a target. The Logical Interrupt Source is 769 * designated with the "lisn" parameter and the target is designated 770 * with the "target" and "priority" parameters. Upon return from the 771 * hcall(), no additional interrupts will be directed to the old EQ. 772 * 773 * Parameters: 774 * Input: 775 * - R4: "flags" 776 * Bits 0-61: Reserved 777 * Bit 62: set the "eisn" in the EAS 778 * Bit 63: masks the interrupt source in the hardware interrupt 779 * control structure. An interrupt masked by this mechanism will 780 * be dropped, but it's source state bits will still be 781 * set. There is no race-free way of unmasking and restoring the 782 * source. Thus this should only be used in interrupts that are 783 * also masked at the source, and only in cases where the 784 * interrupt is not meant to be used for a large amount of time 785 * because no valid target exists for it for example 786 * - R5: "lisn" is per "interrupts", "interrupt-map", or 787 * "ibm,xive-lisn-ranges" properties, or as returned by the 788 * ibm,query-interrupt-source-number RTAS call, or as returned by 789 * the H_ALLOCATE_VAS_WINDOW hcall 790 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 791 * "ibm,ppc-interrupt-gserver#s" 792 * - R7: "priority" is a valid priority not in 793 * "ibm,plat-res-int-priorities" 794 * - R8: "eisn" is the guest EISN associated with the "lisn" 795 * 796 * Output: 797 * - None 798 */ 799 800 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 801 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 802 803 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 804 SpaprMachineState *spapr, 805 target_ulong opcode, 806 target_ulong *args) 807 { 808 SpaprXive *xive = spapr->xive; 809 XiveEAS eas, new_eas; 810 target_ulong flags = args[0]; 811 target_ulong lisn = args[1]; 812 target_ulong target = args[2]; 813 target_ulong priority = args[3]; 814 target_ulong eisn = args[4]; 815 uint8_t end_blk; 816 uint32_t end_idx; 817 818 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 819 return H_FUNCTION; 820 } 821 822 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 823 return H_PARAMETER; 824 } 825 826 if (lisn >= xive->nr_irqs) { 827 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 828 lisn); 829 return H_P2; 830 } 831 832 eas = xive->eat[lisn]; 833 if (!xive_eas_is_valid(&eas)) { 834 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 835 lisn); 836 return H_P2; 837 } 838 839 /* priority 0xff is used to reset the EAS */ 840 if (priority == 0xff) { 841 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 842 goto out; 843 } 844 845 if (flags & SPAPR_XIVE_SRC_MASK) { 846 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 847 } else { 848 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 849 } 850 851 if (spapr_xive_priority_is_reserved(priority)) { 852 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 853 " is reserved\n", priority); 854 return H_P4; 855 } 856 857 /* 858 * Validate that "target" is part of the list of threads allocated 859 * to the partition. For that, find the END corresponding to the 860 * target. 861 */ 862 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 863 return H_P3; 864 } 865 866 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 867 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 868 869 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 870 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 871 } 872 873 if (kvm_irqchip_in_kernel()) { 874 Error *local_err = NULL; 875 876 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 877 if (local_err) { 878 error_report_err(local_err); 879 return H_HARDWARE; 880 } 881 } 882 883 out: 884 xive->eat[lisn] = new_eas; 885 return H_SUCCESS; 886 } 887 888 /* 889 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 890 * target/priority pair is assigned to the specified Logical Interrupt 891 * Source. 892 * 893 * Parameters: 894 * Input: 895 * - R4: "flags" 896 * Bits 0-63 Reserved 897 * - R5: "lisn" is per "interrupts", "interrupt-map", or 898 * "ibm,xive-lisn-ranges" properties, or as returned by the 899 * ibm,query-interrupt-source-number RTAS call, or as 900 * returned by the H_ALLOCATE_VAS_WINDOW hcall 901 * 902 * Output: 903 * - R4: Target to which the specified Logical Interrupt Source is 904 * assigned 905 * - R5: Priority to which the specified Logical Interrupt Source is 906 * assigned 907 * - R6: EISN for the specified Logical Interrupt Source (this will be 908 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 909 */ 910 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 911 SpaprMachineState *spapr, 912 target_ulong opcode, 913 target_ulong *args) 914 { 915 SpaprXive *xive = spapr->xive; 916 target_ulong flags = args[0]; 917 target_ulong lisn = args[1]; 918 XiveEAS eas; 919 XiveEND *end; 920 uint8_t nvt_blk; 921 uint32_t end_idx, nvt_idx; 922 923 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 924 return H_FUNCTION; 925 } 926 927 if (flags) { 928 return H_PARAMETER; 929 } 930 931 if (lisn >= xive->nr_irqs) { 932 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 933 lisn); 934 return H_P2; 935 } 936 937 eas = xive->eat[lisn]; 938 if (!xive_eas_is_valid(&eas)) { 939 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 940 lisn); 941 return H_P2; 942 } 943 944 /* EAS_END_BLOCK is unused on sPAPR */ 945 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 946 947 assert(end_idx < xive->nr_ends); 948 end = &xive->endt[end_idx]; 949 950 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 951 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 952 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 953 954 if (xive_eas_is_masked(&eas)) { 955 args[1] = 0xff; 956 } else { 957 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 958 } 959 960 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 961 962 return H_SUCCESS; 963 } 964 965 /* 966 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 967 * address of the notification management page associated with the 968 * specified target and priority. 969 * 970 * Parameters: 971 * Input: 972 * - R4: "flags" 973 * Bits 0-63 Reserved 974 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 975 * "ibm,ppc-interrupt-gserver#s" 976 * - R6: "priority" is a valid priority not in 977 * "ibm,plat-res-int-priorities" 978 * 979 * Output: 980 * - R4: Logical real address of notification page 981 * - R5: Power of 2 page size of the notification page 982 */ 983 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 984 SpaprMachineState *spapr, 985 target_ulong opcode, 986 target_ulong *args) 987 { 988 SpaprXive *xive = spapr->xive; 989 XiveENDSource *end_xsrc = &xive->end_source; 990 target_ulong flags = args[0]; 991 target_ulong target = args[1]; 992 target_ulong priority = args[2]; 993 XiveEND *end; 994 uint8_t end_blk; 995 uint32_t end_idx; 996 997 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 998 return H_FUNCTION; 999 } 1000 1001 if (flags) { 1002 return H_PARAMETER; 1003 } 1004 1005 /* 1006 * H_STATE should be returned if a H_INT_RESET is in progress. 1007 * This is not needed when running the emulation under QEMU 1008 */ 1009 1010 if (spapr_xive_priority_is_reserved(priority)) { 1011 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1012 " is reserved\n", priority); 1013 return H_P3; 1014 } 1015 1016 /* 1017 * Validate that "target" is part of the list of threads allocated 1018 * to the partition. For that, find the END corresponding to the 1019 * target. 1020 */ 1021 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1022 return H_P2; 1023 } 1024 1025 assert(end_idx < xive->nr_ends); 1026 end = &xive->endt[end_idx]; 1027 1028 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1029 if (xive_end_is_enqueue(end)) { 1030 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1031 } else { 1032 args[1] = 0; 1033 } 1034 1035 return H_SUCCESS; 1036 } 1037 1038 /* 1039 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1040 * a given "target" and "priority". It is also used to set the 1041 * notification config associated with the EQ. An EQ size of 0 is 1042 * used to reset the EQ config for a given target and priority. If 1043 * resetting the EQ config, the END associated with the given "target" 1044 * and "priority" will be changed to disable queueing. 1045 * 1046 * Upon return from the hcall(), no additional interrupts will be 1047 * directed to the old EQ (if one was set). The old EQ (if one was 1048 * set) should be investigated for interrupts that occurred prior to 1049 * or during the hcall(). 1050 * 1051 * Parameters: 1052 * Input: 1053 * - R4: "flags" 1054 * Bits 0-62: Reserved 1055 * Bit 63: Unconditional Notify (n) per the XIVE spec 1056 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1057 * "ibm,ppc-interrupt-gserver#s" 1058 * - R6: "priority" is a valid priority not in 1059 * "ibm,plat-res-int-priorities" 1060 * - R7: "eventQueue": The logical real address of the start of the EQ 1061 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1062 * 1063 * Output: 1064 * - None 1065 */ 1066 1067 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1068 1069 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1070 SpaprMachineState *spapr, 1071 target_ulong opcode, 1072 target_ulong *args) 1073 { 1074 SpaprXive *xive = spapr->xive; 1075 target_ulong flags = args[0]; 1076 target_ulong target = args[1]; 1077 target_ulong priority = args[2]; 1078 target_ulong qpage = args[3]; 1079 target_ulong qsize = args[4]; 1080 XiveEND end; 1081 uint8_t end_blk, nvt_blk; 1082 uint32_t end_idx, nvt_idx; 1083 1084 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1085 return H_FUNCTION; 1086 } 1087 1088 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1089 return H_PARAMETER; 1090 } 1091 1092 /* 1093 * H_STATE should be returned if a H_INT_RESET is in progress. 1094 * This is not needed when running the emulation under QEMU 1095 */ 1096 1097 if (spapr_xive_priority_is_reserved(priority)) { 1098 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1099 " is reserved\n", priority); 1100 return H_P3; 1101 } 1102 1103 /* 1104 * Validate that "target" is part of the list of threads allocated 1105 * to the partition. For that, find the END corresponding to the 1106 * target. 1107 */ 1108 1109 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1110 return H_P2; 1111 } 1112 1113 assert(end_idx < xive->nr_ends); 1114 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1115 1116 switch (qsize) { 1117 case 12: 1118 case 16: 1119 case 21: 1120 case 24: 1121 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1122 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1123 " is not naturally aligned with %" HWADDR_PRIx "\n", 1124 qpage, (hwaddr)1 << qsize); 1125 return H_P4; 1126 } 1127 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1128 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1129 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1130 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1131 break; 1132 case 0: 1133 /* reset queue and disable queueing */ 1134 spapr_xive_end_reset(&end); 1135 goto out; 1136 1137 default: 1138 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1139 qsize); 1140 return H_P5; 1141 } 1142 1143 if (qsize) { 1144 hwaddr plen = 1 << qsize; 1145 void *eq; 1146 1147 /* 1148 * Validate the guest EQ. We should also check that the queue 1149 * has been zeroed by the OS. 1150 */ 1151 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1152 MEMTXATTRS_UNSPECIFIED); 1153 if (plen != 1 << qsize) { 1154 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1155 HWADDR_PRIx "\n", qpage); 1156 return H_P4; 1157 } 1158 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1159 } 1160 1161 /* "target" should have been validated above */ 1162 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1163 g_assert_not_reached(); 1164 } 1165 1166 /* 1167 * Ensure the priority and target are correctly set (they will not 1168 * be right after allocation) 1169 */ 1170 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1171 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1172 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1173 1174 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1175 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1176 } else { 1177 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1178 } 1179 1180 /* 1181 * The generation bit for the END starts at 1 and The END page 1182 * offset counter starts at 0. 1183 */ 1184 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1185 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1186 end.w0 |= cpu_to_be32(END_W0_VALID); 1187 1188 /* 1189 * TODO: issue syncs required to ensure all in-flight interrupts 1190 * are complete on the old END 1191 */ 1192 1193 out: 1194 if (kvm_irqchip_in_kernel()) { 1195 Error *local_err = NULL; 1196 1197 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1198 if (local_err) { 1199 error_report_err(local_err); 1200 return H_HARDWARE; 1201 } 1202 } 1203 1204 /* Update END */ 1205 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1206 return H_SUCCESS; 1207 } 1208 1209 /* 1210 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1211 * target and priority. 1212 * 1213 * Parameters: 1214 * Input: 1215 * - R4: "flags" 1216 * Bits 0-62: Reserved 1217 * Bit 63: Debug: Return debug data 1218 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1219 * "ibm,ppc-interrupt-gserver#s" 1220 * - R6: "priority" is a valid priority not in 1221 * "ibm,plat-res-int-priorities" 1222 * 1223 * Output: 1224 * - R4: "flags": 1225 * Bits 0-61: Reserved 1226 * Bit 62: The value of Event Queue Generation Number (g) per 1227 * the XIVE spec if "Debug" = 1 1228 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1229 * - R5: The logical real address of the start of the EQ 1230 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1231 * - R7: The value of Event Queue Offset Counter per XIVE spec 1232 * if "Debug" = 1, else 0 1233 * 1234 */ 1235 1236 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1237 1238 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1239 SpaprMachineState *spapr, 1240 target_ulong opcode, 1241 target_ulong *args) 1242 { 1243 SpaprXive *xive = spapr->xive; 1244 target_ulong flags = args[0]; 1245 target_ulong target = args[1]; 1246 target_ulong priority = args[2]; 1247 XiveEND *end; 1248 uint8_t end_blk; 1249 uint32_t end_idx; 1250 1251 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1252 return H_FUNCTION; 1253 } 1254 1255 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1256 return H_PARAMETER; 1257 } 1258 1259 /* 1260 * H_STATE should be returned if a H_INT_RESET is in progress. 1261 * This is not needed when running the emulation under QEMU 1262 */ 1263 1264 if (spapr_xive_priority_is_reserved(priority)) { 1265 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1266 " is reserved\n", priority); 1267 return H_P3; 1268 } 1269 1270 /* 1271 * Validate that "target" is part of the list of threads allocated 1272 * to the partition. For that, find the END corresponding to the 1273 * target. 1274 */ 1275 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1276 return H_P2; 1277 } 1278 1279 assert(end_idx < xive->nr_ends); 1280 end = &xive->endt[end_idx]; 1281 1282 args[0] = 0; 1283 if (xive_end_is_notify(end)) { 1284 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1285 } 1286 1287 if (xive_end_is_enqueue(end)) { 1288 args[1] = xive_end_qaddr(end); 1289 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1290 } else { 1291 args[1] = 0; 1292 args[2] = 0; 1293 } 1294 1295 if (kvm_irqchip_in_kernel()) { 1296 Error *local_err = NULL; 1297 1298 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1299 if (local_err) { 1300 error_report_err(local_err); 1301 return H_HARDWARE; 1302 } 1303 } 1304 1305 /* TODO: do we need any locking on the END ? */ 1306 if (flags & SPAPR_XIVE_END_DEBUG) { 1307 /* Load the event queue generation number into the return flags */ 1308 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1309 1310 /* Load R7 with the event queue offset counter */ 1311 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1312 } else { 1313 args[3] = 0; 1314 } 1315 1316 return H_SUCCESS; 1317 } 1318 1319 /* 1320 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1321 * reporting cache line pair for the calling thread. The reporting 1322 * cache lines will contain the OS interrupt context when the OS 1323 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1324 * interrupt. The reporting cache lines can be reset by inputting -1 1325 * in "reportingLine". Issuing the CI store byte without reporting 1326 * cache lines registered will result in the data not being accessible 1327 * to the OS. 1328 * 1329 * Parameters: 1330 * Input: 1331 * - R4: "flags" 1332 * Bits 0-63: Reserved 1333 * - R5: "reportingLine": The logical real address of the reporting cache 1334 * line pair 1335 * 1336 * Output: 1337 * - None 1338 */ 1339 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1340 SpaprMachineState *spapr, 1341 target_ulong opcode, 1342 target_ulong *args) 1343 { 1344 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1345 return H_FUNCTION; 1346 } 1347 1348 /* 1349 * H_STATE should be returned if a H_INT_RESET is in progress. 1350 * This is not needed when running the emulation under QEMU 1351 */ 1352 1353 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1354 return H_FUNCTION; 1355 } 1356 1357 /* 1358 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1359 * real address of the reporting cache line pair set for the input 1360 * "target". If no reporting cache line pair has been set, -1 is 1361 * returned. 1362 * 1363 * Parameters: 1364 * Input: 1365 * - R4: "flags" 1366 * Bits 0-63: Reserved 1367 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1368 * "ibm,ppc-interrupt-gserver#s" 1369 * - R6: "reportingLine": The logical real address of the reporting 1370 * cache line pair 1371 * 1372 * Output: 1373 * - R4: The logical real address of the reporting line if set, else -1 1374 */ 1375 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1376 SpaprMachineState *spapr, 1377 target_ulong opcode, 1378 target_ulong *args) 1379 { 1380 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1381 return H_FUNCTION; 1382 } 1383 1384 /* 1385 * H_STATE should be returned if a H_INT_RESET is in progress. 1386 * This is not needed when running the emulation under QEMU 1387 */ 1388 1389 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1390 return H_FUNCTION; 1391 } 1392 1393 /* 1394 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1395 * page for the input "lisn". This hcall is only supported for LISNs 1396 * that have the ESB hcall flag set to 1 when returned from hcall() 1397 * H_INT_GET_SOURCE_INFO. 1398 * 1399 * Parameters: 1400 * Input: 1401 * - R4: "flags" 1402 * Bits 0-62: Reserved 1403 * bit 63: Store: Store=1, store operation, else load operation 1404 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1405 * "ibm,xive-lisn-ranges" properties, or as returned by the 1406 * ibm,query-interrupt-source-number RTAS call, or as 1407 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1408 * - R6: "esbOffset" is the offset into the ESB page for the load or 1409 * store operation 1410 * - R7: "storeData" is the data to write for a store operation 1411 * 1412 * Output: 1413 * - R4: The value of the load if load operation, else -1 1414 */ 1415 1416 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1417 1418 static target_ulong h_int_esb(PowerPCCPU *cpu, 1419 SpaprMachineState *spapr, 1420 target_ulong opcode, 1421 target_ulong *args) 1422 { 1423 SpaprXive *xive = spapr->xive; 1424 XiveEAS eas; 1425 target_ulong flags = args[0]; 1426 target_ulong lisn = args[1]; 1427 target_ulong offset = args[2]; 1428 target_ulong data = args[3]; 1429 hwaddr mmio_addr; 1430 XiveSource *xsrc = &xive->source; 1431 1432 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1433 return H_FUNCTION; 1434 } 1435 1436 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1437 return H_PARAMETER; 1438 } 1439 1440 if (lisn >= xive->nr_irqs) { 1441 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1442 lisn); 1443 return H_P2; 1444 } 1445 1446 eas = xive->eat[lisn]; 1447 if (!xive_eas_is_valid(&eas)) { 1448 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1449 lisn); 1450 return H_P2; 1451 } 1452 1453 if (offset > (1ull << xsrc->esb_shift)) { 1454 return H_P3; 1455 } 1456 1457 if (kvm_irqchip_in_kernel()) { 1458 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1459 flags & SPAPR_XIVE_ESB_STORE); 1460 } else { 1461 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1462 1463 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1464 (flags & SPAPR_XIVE_ESB_STORE))) { 1465 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1466 HWADDR_PRIx "\n", mmio_addr); 1467 return H_HARDWARE; 1468 } 1469 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1470 } 1471 return H_SUCCESS; 1472 } 1473 1474 /* 1475 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1476 * ensure any in flight events for the input lisn are in the event 1477 * queue. 1478 * 1479 * Parameters: 1480 * Input: 1481 * - R4: "flags" 1482 * Bits 0-63: Reserved 1483 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1484 * "ibm,xive-lisn-ranges" properties, or as returned by the 1485 * ibm,query-interrupt-source-number RTAS call, or as 1486 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1487 * 1488 * Output: 1489 * - None 1490 */ 1491 static target_ulong h_int_sync(PowerPCCPU *cpu, 1492 SpaprMachineState *spapr, 1493 target_ulong opcode, 1494 target_ulong *args) 1495 { 1496 SpaprXive *xive = spapr->xive; 1497 XiveEAS eas; 1498 target_ulong flags = args[0]; 1499 target_ulong lisn = args[1]; 1500 1501 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1502 return H_FUNCTION; 1503 } 1504 1505 if (flags) { 1506 return H_PARAMETER; 1507 } 1508 1509 if (lisn >= xive->nr_irqs) { 1510 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1511 lisn); 1512 return H_P2; 1513 } 1514 1515 eas = xive->eat[lisn]; 1516 if (!xive_eas_is_valid(&eas)) { 1517 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1518 lisn); 1519 return H_P2; 1520 } 1521 1522 /* 1523 * H_STATE should be returned if a H_INT_RESET is in progress. 1524 * This is not needed when running the emulation under QEMU 1525 */ 1526 1527 /* 1528 * This is not real hardware. Nothing to be done unless when 1529 * under KVM 1530 */ 1531 1532 if (kvm_irqchip_in_kernel()) { 1533 Error *local_err = NULL; 1534 1535 kvmppc_xive_sync_source(xive, lisn, &local_err); 1536 if (local_err) { 1537 error_report_err(local_err); 1538 return H_HARDWARE; 1539 } 1540 } 1541 return H_SUCCESS; 1542 } 1543 1544 /* 1545 * The H_INT_RESET hcall() is used to reset all of the partition's 1546 * interrupt exploitation structures to their initial state. This 1547 * means losing all previously set interrupt state set via 1548 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1549 * 1550 * Parameters: 1551 * Input: 1552 * - R4: "flags" 1553 * Bits 0-63: Reserved 1554 * 1555 * Output: 1556 * - None 1557 */ 1558 static target_ulong h_int_reset(PowerPCCPU *cpu, 1559 SpaprMachineState *spapr, 1560 target_ulong opcode, 1561 target_ulong *args) 1562 { 1563 SpaprXive *xive = spapr->xive; 1564 target_ulong flags = args[0]; 1565 1566 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1567 return H_FUNCTION; 1568 } 1569 1570 if (flags) { 1571 return H_PARAMETER; 1572 } 1573 1574 device_reset(DEVICE(xive)); 1575 1576 if (kvm_irqchip_in_kernel()) { 1577 Error *local_err = NULL; 1578 1579 kvmppc_xive_reset(xive, &local_err); 1580 if (local_err) { 1581 error_report_err(local_err); 1582 return H_HARDWARE; 1583 } 1584 } 1585 return H_SUCCESS; 1586 } 1587 1588 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1589 { 1590 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1591 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1592 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1593 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1594 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1595 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1596 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1597 h_int_set_os_reporting_line); 1598 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1599 h_int_get_os_reporting_line); 1600 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1601 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1602 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1603 } 1604 1605 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1606 uint32_t phandle) 1607 { 1608 SpaprXive *xive = spapr->xive; 1609 int node; 1610 uint64_t timas[2 * 2]; 1611 /* Interrupt number ranges for the IPIs */ 1612 uint32_t lisn_ranges[] = { 1613 cpu_to_be32(0), 1614 cpu_to_be32(nr_servers), 1615 }; 1616 /* 1617 * EQ size - the sizes of pages supported by the system 4K, 64K, 1618 * 2M, 16M. We only advertise 64K for the moment. 1619 */ 1620 uint32_t eq_sizes[] = { 1621 cpu_to_be32(16), /* 64K */ 1622 }; 1623 /* 1624 * The following array is in sync with the reserved priorities 1625 * defined by the 'spapr_xive_priority_is_reserved' routine. 1626 */ 1627 uint32_t plat_res_int_priorities[] = { 1628 cpu_to_be32(7), /* start */ 1629 cpu_to_be32(0xf8), /* count */ 1630 }; 1631 1632 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1633 timas[0] = cpu_to_be64(xive->tm_base + 1634 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1635 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1636 timas[2] = cpu_to_be64(xive->tm_base + 1637 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1638 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1639 1640 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1641 1642 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1643 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1644 1645 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1646 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1647 sizeof(eq_sizes))); 1648 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1649 sizeof(lisn_ranges))); 1650 1651 /* For Linux to link the LSIs to the interrupt controller. */ 1652 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1653 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1654 1655 /* For SLOF */ 1656 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1657 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1658 1659 /* 1660 * The "ibm,plat-res-int-priorities" property defines the priority 1661 * ranges reserved by the hypervisor 1662 */ 1663 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1664 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1665 } 1666