1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "qemu/error-report.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/spapr.h" 19 #include "hw/ppc/spapr_cpu_core.h" 20 #include "hw/ppc/spapr_xive.h" 21 #include "hw/ppc/xive.h" 22 #include "hw/ppc/xive_regs.h" 23 24 /* 25 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 26 * use for the ESB pages and the TIMA pages 27 */ 28 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 29 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 30 31 /* 32 * The allocation of VP blocks is a complex operation in OPAL and the 33 * VP identifiers have a relation with the number of HW chips, the 34 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 35 * controller model does not have the same constraints and can use a 36 * simple mapping scheme of the CPU vcpu_id 37 * 38 * These identifiers are never returned to the OS. 39 */ 40 41 #define SPAPR_XIVE_NVT_BASE 0x400 42 43 /* 44 * sPAPR NVT and END indexing helpers 45 */ 46 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 47 { 48 return nvt_idx - SPAPR_XIVE_NVT_BASE; 49 } 50 51 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 52 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 53 { 54 assert(cpu); 55 56 if (out_nvt_blk) { 57 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 58 } 59 60 if (out_nvt_blk) { 61 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 62 } 63 } 64 65 static int spapr_xive_target_to_nvt(uint32_t target, 66 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 67 { 68 PowerPCCPU *cpu = spapr_find_cpu(target); 69 70 if (!cpu) { 71 return -1; 72 } 73 74 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 75 return 0; 76 } 77 78 /* 79 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 80 * priorities per CPU 81 */ 82 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 83 uint32_t *out_server, uint8_t *out_prio) 84 { 85 86 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 87 88 if (out_server) { 89 *out_server = end_idx >> 3; 90 } 91 92 if (out_prio) { 93 *out_prio = end_idx & 0x7; 94 } 95 return 0; 96 } 97 98 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 99 uint8_t *out_end_blk, uint32_t *out_end_idx) 100 { 101 assert(cpu); 102 103 if (out_end_blk) { 104 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 105 } 106 107 if (out_end_idx) { 108 *out_end_idx = (cpu->vcpu_id << 3) + prio; 109 } 110 } 111 112 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 113 uint8_t *out_end_blk, uint32_t *out_end_idx) 114 { 115 PowerPCCPU *cpu = spapr_find_cpu(target); 116 117 if (!cpu) { 118 return -1; 119 } 120 121 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 122 return 0; 123 } 124 125 /* 126 * On sPAPR machines, use a simplified output for the XIVE END 127 * structure dumping only the information related to the OS EQ. 128 */ 129 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 130 Monitor *mon) 131 { 132 uint64_t qaddr_base = xive_end_qaddr(end); 133 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 134 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 135 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 136 uint32_t qentries = 1 << (qsize + 10); 137 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 138 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 139 140 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 141 spapr_xive_nvt_to_target(0, nvt), 142 priority, qindex, qentries, qaddr_base, qgen); 143 144 xive_end_queue_pic_print_info(end, 6, mon); 145 monitor_printf(mon, "]"); 146 } 147 148 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 149 { 150 XiveSource *xsrc = &xive->source; 151 int i; 152 153 if (kvm_irqchip_in_kernel()) { 154 Error *local_err = NULL; 155 156 kvmppc_xive_synchronize_state(xive, &local_err); 157 if (local_err) { 158 error_report_err(local_err); 159 return; 160 } 161 } 162 163 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 164 165 for (i = 0; i < xive->nr_irqs; i++) { 166 uint8_t pq = xive_source_esb_get(xsrc, i); 167 XiveEAS *eas = &xive->eat[i]; 168 169 if (!xive_eas_is_valid(eas)) { 170 continue; 171 } 172 173 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 174 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 175 pq & XIVE_ESB_VAL_P ? 'P' : '-', 176 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 177 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 178 xive_eas_is_masked(eas) ? "M" : " ", 179 (int) xive_get_field64(EAS_END_DATA, eas->w)); 180 181 if (!xive_eas_is_masked(eas)) { 182 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 183 XiveEND *end; 184 185 assert(end_idx < xive->nr_ends); 186 end = &xive->endt[end_idx]; 187 188 if (xive_end_is_valid(end)) { 189 spapr_xive_end_pic_print_info(xive, end, mon); 190 } 191 } 192 monitor_printf(mon, "\n"); 193 } 194 } 195 196 void spapr_xive_map_mmio(SpaprXive *xive) 197 { 198 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 199 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 200 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 201 } 202 203 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 204 { 205 memory_region_set_enabled(&xive->source.esb_mmio, enable); 206 memory_region_set_enabled(&xive->tm_mmio, enable); 207 208 /* Disable the END ESBs until a guest OS makes use of them */ 209 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 210 } 211 212 /* 213 * When a Virtual Processor is scheduled to run on a HW thread, the 214 * hypervisor pushes its identifier in the OS CAM line. Emulate the 215 * same behavior under QEMU. 216 */ 217 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 218 { 219 uint8_t nvt_blk; 220 uint32_t nvt_idx; 221 uint32_t nvt_cam; 222 223 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 224 225 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 226 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 227 } 228 229 static void spapr_xive_end_reset(XiveEND *end) 230 { 231 memset(end, 0, sizeof(*end)); 232 233 /* switch off the escalation and notification ESBs */ 234 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 235 } 236 237 static void spapr_xive_reset(void *dev) 238 { 239 SpaprXive *xive = SPAPR_XIVE(dev); 240 int i; 241 242 /* 243 * The XiveSource has its own reset handler, which mask off all 244 * IRQs (!P|Q) 245 */ 246 247 /* Mask all valid EASs in the IRQ number space. */ 248 for (i = 0; i < xive->nr_irqs; i++) { 249 XiveEAS *eas = &xive->eat[i]; 250 if (xive_eas_is_valid(eas)) { 251 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 252 } else { 253 eas->w = 0; 254 } 255 } 256 257 /* Clear all ENDs */ 258 for (i = 0; i < xive->nr_ends; i++) { 259 spapr_xive_end_reset(&xive->endt[i]); 260 } 261 } 262 263 static void spapr_xive_instance_init(Object *obj) 264 { 265 SpaprXive *xive = SPAPR_XIVE(obj); 266 267 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 268 TYPE_XIVE_SOURCE, &error_abort, NULL); 269 270 object_initialize_child(obj, "end_source", &xive->end_source, 271 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 272 &error_abort, NULL); 273 274 /* Not connected to the KVM XIVE device */ 275 xive->fd = -1; 276 } 277 278 static void spapr_xive_realize(DeviceState *dev, Error **errp) 279 { 280 SpaprXive *xive = SPAPR_XIVE(dev); 281 XiveSource *xsrc = &xive->source; 282 XiveENDSource *end_xsrc = &xive->end_source; 283 Error *local_err = NULL; 284 MachineState *machine = MACHINE(qdev_get_machine()); 285 286 if (!xive->nr_irqs) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 if (!xive->nr_ends) { 292 error_setg(errp, "Number of interrupt needs to be greater 0"); 293 return; 294 } 295 296 /* 297 * Initialize the internal sources, for IPIs and virtual devices. 298 */ 299 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 300 &error_fatal); 301 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 302 &error_fatal); 303 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 304 if (local_err) { 305 error_propagate(errp, local_err); 306 return; 307 } 308 309 /* 310 * Initialize the END ESB source 311 */ 312 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 313 &error_fatal); 314 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 315 &error_fatal); 316 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 317 if (local_err) { 318 error_propagate(errp, local_err); 319 return; 320 } 321 322 /* Set the mapping address of the END ESB pages after the source ESBs */ 323 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 324 325 /* 326 * Allocate the routing tables 327 */ 328 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 329 xive->endt = g_new0(XiveEND, xive->nr_ends); 330 331 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 332 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 333 334 qemu_register_reset(spapr_xive_reset, dev); 335 336 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) { 337 kvmppc_xive_connect(xive, &local_err); 338 if (local_err && machine_kernel_irqchip_required(machine)) { 339 error_prepend(&local_err, 340 "kernel_irqchip requested but unavailable: "); 341 error_propagate(errp, local_err); 342 return; 343 } 344 345 if (!local_err) { 346 return; 347 } 348 349 /* 350 * We failed to initialize the XIVE KVM device, fallback to 351 * emulated mode 352 */ 353 error_prepend(&local_err, "kernel_irqchip allowed but unavailable: "); 354 warn_report_err(local_err); 355 } 356 357 /* TIMA initialization */ 358 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 359 "xive.tima", 4ull << TM_SHIFT); 360 361 /* Define all XIVE MMIO regions on SysBus */ 362 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 363 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 364 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 365 366 /* Map all regions */ 367 spapr_xive_map_mmio(xive); 368 } 369 370 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 371 uint32_t eas_idx, XiveEAS *eas) 372 { 373 SpaprXive *xive = SPAPR_XIVE(xrtr); 374 375 if (eas_idx >= xive->nr_irqs) { 376 return -1; 377 } 378 379 *eas = xive->eat[eas_idx]; 380 return 0; 381 } 382 383 static int spapr_xive_get_end(XiveRouter *xrtr, 384 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 385 { 386 SpaprXive *xive = SPAPR_XIVE(xrtr); 387 388 if (end_idx >= xive->nr_ends) { 389 return -1; 390 } 391 392 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 393 return 0; 394 } 395 396 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 397 uint32_t end_idx, XiveEND *end, 398 uint8_t word_number) 399 { 400 SpaprXive *xive = SPAPR_XIVE(xrtr); 401 402 if (end_idx >= xive->nr_ends) { 403 return -1; 404 } 405 406 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 407 return 0; 408 } 409 410 static int spapr_xive_get_nvt(XiveRouter *xrtr, 411 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 412 { 413 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 414 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 415 416 if (!cpu) { 417 /* TODO: should we assert() if we can find a NVT ? */ 418 return -1; 419 } 420 421 /* 422 * sPAPR does not maintain a NVT table. Return that the NVT is 423 * valid if we have found a matching CPU 424 */ 425 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 426 return 0; 427 } 428 429 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 430 uint32_t nvt_idx, XiveNVT *nvt, 431 uint8_t word_number) 432 { 433 /* 434 * We don't need to write back to the NVTs because the sPAPR 435 * machine should never hit a non-scheduled NVT. It should never 436 * get called. 437 */ 438 g_assert_not_reached(); 439 } 440 441 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 442 { 443 PowerPCCPU *cpu = POWERPC_CPU(cs); 444 445 return spapr_cpu_state(cpu)->tctx; 446 } 447 448 static const VMStateDescription vmstate_spapr_xive_end = { 449 .name = TYPE_SPAPR_XIVE "/end", 450 .version_id = 1, 451 .minimum_version_id = 1, 452 .fields = (VMStateField []) { 453 VMSTATE_UINT32(w0, XiveEND), 454 VMSTATE_UINT32(w1, XiveEND), 455 VMSTATE_UINT32(w2, XiveEND), 456 VMSTATE_UINT32(w3, XiveEND), 457 VMSTATE_UINT32(w4, XiveEND), 458 VMSTATE_UINT32(w5, XiveEND), 459 VMSTATE_UINT32(w6, XiveEND), 460 VMSTATE_UINT32(w7, XiveEND), 461 VMSTATE_END_OF_LIST() 462 }, 463 }; 464 465 static const VMStateDescription vmstate_spapr_xive_eas = { 466 .name = TYPE_SPAPR_XIVE "/eas", 467 .version_id = 1, 468 .minimum_version_id = 1, 469 .fields = (VMStateField []) { 470 VMSTATE_UINT64(w, XiveEAS), 471 VMSTATE_END_OF_LIST() 472 }, 473 }; 474 475 static int vmstate_spapr_xive_pre_save(void *opaque) 476 { 477 if (kvm_irqchip_in_kernel()) { 478 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 479 } 480 481 return 0; 482 } 483 484 /* 485 * Called by the sPAPR IRQ backend 'post_load' method at the machine 486 * level. 487 */ 488 int spapr_xive_post_load(SpaprXive *xive, int version_id) 489 { 490 if (kvm_irqchip_in_kernel()) { 491 return kvmppc_xive_post_load(xive, version_id); 492 } 493 494 return 0; 495 } 496 497 static const VMStateDescription vmstate_spapr_xive = { 498 .name = TYPE_SPAPR_XIVE, 499 .version_id = 1, 500 .minimum_version_id = 1, 501 .pre_save = vmstate_spapr_xive_pre_save, 502 .post_load = NULL, /* handled at the machine level */ 503 .fields = (VMStateField[]) { 504 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 505 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 506 vmstate_spapr_xive_eas, XiveEAS), 507 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 508 vmstate_spapr_xive_end, XiveEND), 509 VMSTATE_END_OF_LIST() 510 }, 511 }; 512 513 static Property spapr_xive_properties[] = { 514 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 515 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 516 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 517 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 518 DEFINE_PROP_END_OF_LIST(), 519 }; 520 521 static void spapr_xive_class_init(ObjectClass *klass, void *data) 522 { 523 DeviceClass *dc = DEVICE_CLASS(klass); 524 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 525 526 dc->desc = "sPAPR XIVE Interrupt Controller"; 527 dc->props = spapr_xive_properties; 528 dc->realize = spapr_xive_realize; 529 dc->vmsd = &vmstate_spapr_xive; 530 531 xrc->get_eas = spapr_xive_get_eas; 532 xrc->get_end = spapr_xive_get_end; 533 xrc->write_end = spapr_xive_write_end; 534 xrc->get_nvt = spapr_xive_get_nvt; 535 xrc->write_nvt = spapr_xive_write_nvt; 536 xrc->get_tctx = spapr_xive_get_tctx; 537 } 538 539 static const TypeInfo spapr_xive_info = { 540 .name = TYPE_SPAPR_XIVE, 541 .parent = TYPE_XIVE_ROUTER, 542 .instance_init = spapr_xive_instance_init, 543 .instance_size = sizeof(SpaprXive), 544 .class_init = spapr_xive_class_init, 545 }; 546 547 static void spapr_xive_register_types(void) 548 { 549 type_register_static(&spapr_xive_info); 550 } 551 552 type_init(spapr_xive_register_types) 553 554 bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi) 555 { 556 XiveSource *xsrc = &xive->source; 557 558 if (lisn >= xive->nr_irqs) { 559 return false; 560 } 561 562 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); 563 if (lsi) { 564 xive_source_irq_set_lsi(xsrc, lisn); 565 } 566 567 if (kvm_irqchip_in_kernel()) { 568 Error *local_err = NULL; 569 570 kvmppc_xive_source_reset_one(xsrc, lisn, &local_err); 571 if (local_err) { 572 error_report_err(local_err); 573 return false; 574 } 575 } 576 577 return true; 578 } 579 580 bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn) 581 { 582 if (lisn >= xive->nr_irqs) { 583 return false; 584 } 585 586 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 587 return true; 588 } 589 590 /* 591 * XIVE hcalls 592 * 593 * The terminology used by the XIVE hcalls is the following : 594 * 595 * TARGET vCPU number 596 * EQ Event Queue assigned by OS to receive event data 597 * ESB page for source interrupt management 598 * LISN Logical Interrupt Source Number identifying a source in the 599 * machine 600 * EISN Effective Interrupt Source Number used by guest OS to 601 * identify source in the guest 602 * 603 * The EAS, END, NVT structures are not exposed. 604 */ 605 606 /* 607 * Linux hosts under OPAL reserve priority 7 for their own escalation 608 * interrupts (DD2.X POWER9). So we only allow the guest to use 609 * priorities [0..6]. 610 */ 611 static bool spapr_xive_priority_is_reserved(uint8_t priority) 612 { 613 switch (priority) { 614 case 0 ... 6: 615 return false; 616 case 7: /* OPAL escalation queue */ 617 default: 618 return true; 619 } 620 } 621 622 /* 623 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 624 * real address of the MMIO page through which the Event State Buffer 625 * entry associated with the value of the "lisn" parameter is managed. 626 * 627 * Parameters: 628 * Input 629 * - R4: "flags" 630 * Bits 0-63 reserved 631 * - R5: "lisn" is per "interrupts", "interrupt-map", or 632 * "ibm,xive-lisn-ranges" properties, or as returned by the 633 * ibm,query-interrupt-source-number RTAS call, or as returned 634 * by the H_ALLOCATE_VAS_WINDOW hcall 635 * 636 * Output 637 * - R4: "flags" 638 * Bits 0-59: Reserved 639 * Bit 60: H_INT_ESB must be used for Event State Buffer 640 * management 641 * Bit 61: 1 == LSI 0 == MSI 642 * Bit 62: the full function page supports trigger 643 * Bit 63: Store EOI Supported 644 * - R5: Logical Real address of full function Event State Buffer 645 * management page, -1 if H_INT_ESB hcall flag is set to 1. 646 * - R6: Logical Real Address of trigger only Event State Buffer 647 * management page or -1. 648 * - R7: Power of 2 page size for the ESB management pages returned in 649 * R5 and R6. 650 */ 651 652 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 653 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 654 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 655 on same page */ 656 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 657 658 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 659 SpaprMachineState *spapr, 660 target_ulong opcode, 661 target_ulong *args) 662 { 663 SpaprXive *xive = spapr->xive; 664 XiveSource *xsrc = &xive->source; 665 target_ulong flags = args[0]; 666 target_ulong lisn = args[1]; 667 668 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 669 return H_FUNCTION; 670 } 671 672 if (flags) { 673 return H_PARAMETER; 674 } 675 676 if (lisn >= xive->nr_irqs) { 677 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 678 lisn); 679 return H_P2; 680 } 681 682 if (!xive_eas_is_valid(&xive->eat[lisn])) { 683 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 684 lisn); 685 return H_P2; 686 } 687 688 /* 689 * All sources are emulated under the main XIVE object and share 690 * the same characteristics. 691 */ 692 args[0] = 0; 693 if (!xive_source_esb_has_2page(xsrc)) { 694 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 695 } 696 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 697 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 698 } 699 700 /* 701 * Force the use of the H_INT_ESB hcall in case of an LSI 702 * interrupt. This is necessary under KVM to re-trigger the 703 * interrupt if the level is still asserted 704 */ 705 if (xive_source_irq_is_lsi(xsrc, lisn)) { 706 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 707 } 708 709 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 710 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 711 } else { 712 args[1] = -1; 713 } 714 715 if (xive_source_esb_has_2page(xsrc) && 716 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 717 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 718 } else { 719 args[2] = -1; 720 } 721 722 if (xive_source_esb_has_2page(xsrc)) { 723 args[3] = xsrc->esb_shift - 1; 724 } else { 725 args[3] = xsrc->esb_shift; 726 } 727 728 return H_SUCCESS; 729 } 730 731 /* 732 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 733 * Interrupt Source to a target. The Logical Interrupt Source is 734 * designated with the "lisn" parameter and the target is designated 735 * with the "target" and "priority" parameters. Upon return from the 736 * hcall(), no additional interrupts will be directed to the old EQ. 737 * 738 * Parameters: 739 * Input: 740 * - R4: "flags" 741 * Bits 0-61: Reserved 742 * Bit 62: set the "eisn" in the EAS 743 * Bit 63: masks the interrupt source in the hardware interrupt 744 * control structure. An interrupt masked by this mechanism will 745 * be dropped, but it's source state bits will still be 746 * set. There is no race-free way of unmasking and restoring the 747 * source. Thus this should only be used in interrupts that are 748 * also masked at the source, and only in cases where the 749 * interrupt is not meant to be used for a large amount of time 750 * because no valid target exists for it for example 751 * - R5: "lisn" is per "interrupts", "interrupt-map", or 752 * "ibm,xive-lisn-ranges" properties, or as returned by the 753 * ibm,query-interrupt-source-number RTAS call, or as returned by 754 * the H_ALLOCATE_VAS_WINDOW hcall 755 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 756 * "ibm,ppc-interrupt-gserver#s" 757 * - R7: "priority" is a valid priority not in 758 * "ibm,plat-res-int-priorities" 759 * - R8: "eisn" is the guest EISN associated with the "lisn" 760 * 761 * Output: 762 * - None 763 */ 764 765 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 766 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 767 768 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 769 SpaprMachineState *spapr, 770 target_ulong opcode, 771 target_ulong *args) 772 { 773 SpaprXive *xive = spapr->xive; 774 XiveEAS eas, new_eas; 775 target_ulong flags = args[0]; 776 target_ulong lisn = args[1]; 777 target_ulong target = args[2]; 778 target_ulong priority = args[3]; 779 target_ulong eisn = args[4]; 780 uint8_t end_blk; 781 uint32_t end_idx; 782 783 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 784 return H_FUNCTION; 785 } 786 787 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 788 return H_PARAMETER; 789 } 790 791 if (lisn >= xive->nr_irqs) { 792 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 793 lisn); 794 return H_P2; 795 } 796 797 eas = xive->eat[lisn]; 798 if (!xive_eas_is_valid(&eas)) { 799 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 800 lisn); 801 return H_P2; 802 } 803 804 /* priority 0xff is used to reset the EAS */ 805 if (priority == 0xff) { 806 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 807 goto out; 808 } 809 810 if (flags & SPAPR_XIVE_SRC_MASK) { 811 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 812 } else { 813 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 814 } 815 816 if (spapr_xive_priority_is_reserved(priority)) { 817 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 818 " is reserved\n", priority); 819 return H_P4; 820 } 821 822 /* 823 * Validate that "target" is part of the list of threads allocated 824 * to the partition. For that, find the END corresponding to the 825 * target. 826 */ 827 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 828 return H_P3; 829 } 830 831 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 832 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 833 834 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 835 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 836 } 837 838 if (kvm_irqchip_in_kernel()) { 839 Error *local_err = NULL; 840 841 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 842 if (local_err) { 843 error_report_err(local_err); 844 return H_HARDWARE; 845 } 846 } 847 848 out: 849 xive->eat[lisn] = new_eas; 850 return H_SUCCESS; 851 } 852 853 /* 854 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 855 * target/priority pair is assigned to the specified Logical Interrupt 856 * Source. 857 * 858 * Parameters: 859 * Input: 860 * - R4: "flags" 861 * Bits 0-63 Reserved 862 * - R5: "lisn" is per "interrupts", "interrupt-map", or 863 * "ibm,xive-lisn-ranges" properties, or as returned by the 864 * ibm,query-interrupt-source-number RTAS call, or as 865 * returned by the H_ALLOCATE_VAS_WINDOW hcall 866 * 867 * Output: 868 * - R4: Target to which the specified Logical Interrupt Source is 869 * assigned 870 * - R5: Priority to which the specified Logical Interrupt Source is 871 * assigned 872 * - R6: EISN for the specified Logical Interrupt Source (this will be 873 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 874 */ 875 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 876 SpaprMachineState *spapr, 877 target_ulong opcode, 878 target_ulong *args) 879 { 880 SpaprXive *xive = spapr->xive; 881 target_ulong flags = args[0]; 882 target_ulong lisn = args[1]; 883 XiveEAS eas; 884 XiveEND *end; 885 uint8_t nvt_blk; 886 uint32_t end_idx, nvt_idx; 887 888 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 889 return H_FUNCTION; 890 } 891 892 if (flags) { 893 return H_PARAMETER; 894 } 895 896 if (lisn >= xive->nr_irqs) { 897 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 898 lisn); 899 return H_P2; 900 } 901 902 eas = xive->eat[lisn]; 903 if (!xive_eas_is_valid(&eas)) { 904 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 905 lisn); 906 return H_P2; 907 } 908 909 /* EAS_END_BLOCK is unused on sPAPR */ 910 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 911 912 assert(end_idx < xive->nr_ends); 913 end = &xive->endt[end_idx]; 914 915 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 916 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 917 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 918 919 if (xive_eas_is_masked(&eas)) { 920 args[1] = 0xff; 921 } else { 922 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 923 } 924 925 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 926 927 return H_SUCCESS; 928 } 929 930 /* 931 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 932 * address of the notification management page associated with the 933 * specified target and priority. 934 * 935 * Parameters: 936 * Input: 937 * - R4: "flags" 938 * Bits 0-63 Reserved 939 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 940 * "ibm,ppc-interrupt-gserver#s" 941 * - R6: "priority" is a valid priority not in 942 * "ibm,plat-res-int-priorities" 943 * 944 * Output: 945 * - R4: Logical real address of notification page 946 * - R5: Power of 2 page size of the notification page 947 */ 948 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 949 SpaprMachineState *spapr, 950 target_ulong opcode, 951 target_ulong *args) 952 { 953 SpaprXive *xive = spapr->xive; 954 XiveENDSource *end_xsrc = &xive->end_source; 955 target_ulong flags = args[0]; 956 target_ulong target = args[1]; 957 target_ulong priority = args[2]; 958 XiveEND *end; 959 uint8_t end_blk; 960 uint32_t end_idx; 961 962 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 963 return H_FUNCTION; 964 } 965 966 if (flags) { 967 return H_PARAMETER; 968 } 969 970 /* 971 * H_STATE should be returned if a H_INT_RESET is in progress. 972 * This is not needed when running the emulation under QEMU 973 */ 974 975 if (spapr_xive_priority_is_reserved(priority)) { 976 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 977 " is reserved\n", priority); 978 return H_P3; 979 } 980 981 /* 982 * Validate that "target" is part of the list of threads allocated 983 * to the partition. For that, find the END corresponding to the 984 * target. 985 */ 986 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 987 return H_P2; 988 } 989 990 assert(end_idx < xive->nr_ends); 991 end = &xive->endt[end_idx]; 992 993 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 994 if (xive_end_is_enqueue(end)) { 995 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 996 } else { 997 args[1] = 0; 998 } 999 1000 return H_SUCCESS; 1001 } 1002 1003 /* 1004 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1005 * a given "target" and "priority". It is also used to set the 1006 * notification config associated with the EQ. An EQ size of 0 is 1007 * used to reset the EQ config for a given target and priority. If 1008 * resetting the EQ config, the END associated with the given "target" 1009 * and "priority" will be changed to disable queueing. 1010 * 1011 * Upon return from the hcall(), no additional interrupts will be 1012 * directed to the old EQ (if one was set). The old EQ (if one was 1013 * set) should be investigated for interrupts that occurred prior to 1014 * or during the hcall(). 1015 * 1016 * Parameters: 1017 * Input: 1018 * - R4: "flags" 1019 * Bits 0-62: Reserved 1020 * Bit 63: Unconditional Notify (n) per the XIVE spec 1021 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1022 * "ibm,ppc-interrupt-gserver#s" 1023 * - R6: "priority" is a valid priority not in 1024 * "ibm,plat-res-int-priorities" 1025 * - R7: "eventQueue": The logical real address of the start of the EQ 1026 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1027 * 1028 * Output: 1029 * - None 1030 */ 1031 1032 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1033 1034 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1035 SpaprMachineState *spapr, 1036 target_ulong opcode, 1037 target_ulong *args) 1038 { 1039 SpaprXive *xive = spapr->xive; 1040 target_ulong flags = args[0]; 1041 target_ulong target = args[1]; 1042 target_ulong priority = args[2]; 1043 target_ulong qpage = args[3]; 1044 target_ulong qsize = args[4]; 1045 XiveEND end; 1046 uint8_t end_blk, nvt_blk; 1047 uint32_t end_idx, nvt_idx; 1048 1049 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1050 return H_FUNCTION; 1051 } 1052 1053 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1054 return H_PARAMETER; 1055 } 1056 1057 /* 1058 * H_STATE should be returned if a H_INT_RESET is in progress. 1059 * This is not needed when running the emulation under QEMU 1060 */ 1061 1062 if (spapr_xive_priority_is_reserved(priority)) { 1063 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1064 " is reserved\n", priority); 1065 return H_P3; 1066 } 1067 1068 /* 1069 * Validate that "target" is part of the list of threads allocated 1070 * to the partition. For that, find the END corresponding to the 1071 * target. 1072 */ 1073 1074 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1075 return H_P2; 1076 } 1077 1078 assert(end_idx < xive->nr_ends); 1079 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1080 1081 switch (qsize) { 1082 case 12: 1083 case 16: 1084 case 21: 1085 case 24: 1086 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1087 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1088 " is not naturally aligned with %" HWADDR_PRIx "\n", 1089 qpage, (hwaddr)1 << qsize); 1090 return H_P4; 1091 } 1092 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1093 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1094 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1095 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1096 break; 1097 case 0: 1098 /* reset queue and disable queueing */ 1099 spapr_xive_end_reset(&end); 1100 goto out; 1101 1102 default: 1103 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1104 qsize); 1105 return H_P5; 1106 } 1107 1108 if (qsize) { 1109 hwaddr plen = 1 << qsize; 1110 void *eq; 1111 1112 /* 1113 * Validate the guest EQ. We should also check that the queue 1114 * has been zeroed by the OS. 1115 */ 1116 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1117 MEMTXATTRS_UNSPECIFIED); 1118 if (plen != 1 << qsize) { 1119 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1120 HWADDR_PRIx "\n", qpage); 1121 return H_P4; 1122 } 1123 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1124 } 1125 1126 /* "target" should have been validated above */ 1127 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1128 g_assert_not_reached(); 1129 } 1130 1131 /* 1132 * Ensure the priority and target are correctly set (they will not 1133 * be right after allocation) 1134 */ 1135 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1136 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1137 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1138 1139 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1140 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1141 } else { 1142 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1143 } 1144 1145 /* 1146 * The generation bit for the END starts at 1 and The END page 1147 * offset counter starts at 0. 1148 */ 1149 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1150 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1151 end.w0 |= cpu_to_be32(END_W0_VALID); 1152 1153 /* 1154 * TODO: issue syncs required to ensure all in-flight interrupts 1155 * are complete on the old END 1156 */ 1157 1158 out: 1159 if (kvm_irqchip_in_kernel()) { 1160 Error *local_err = NULL; 1161 1162 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1163 if (local_err) { 1164 error_report_err(local_err); 1165 return H_HARDWARE; 1166 } 1167 } 1168 1169 /* Update END */ 1170 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1171 return H_SUCCESS; 1172 } 1173 1174 /* 1175 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1176 * target and priority. 1177 * 1178 * Parameters: 1179 * Input: 1180 * - R4: "flags" 1181 * Bits 0-62: Reserved 1182 * Bit 63: Debug: Return debug data 1183 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1184 * "ibm,ppc-interrupt-gserver#s" 1185 * - R6: "priority" is a valid priority not in 1186 * "ibm,plat-res-int-priorities" 1187 * 1188 * Output: 1189 * - R4: "flags": 1190 * Bits 0-61: Reserved 1191 * Bit 62: The value of Event Queue Generation Number (g) per 1192 * the XIVE spec if "Debug" = 1 1193 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1194 * - R5: The logical real address of the start of the EQ 1195 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1196 * - R7: The value of Event Queue Offset Counter per XIVE spec 1197 * if "Debug" = 1, else 0 1198 * 1199 */ 1200 1201 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1202 1203 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1204 SpaprMachineState *spapr, 1205 target_ulong opcode, 1206 target_ulong *args) 1207 { 1208 SpaprXive *xive = spapr->xive; 1209 target_ulong flags = args[0]; 1210 target_ulong target = args[1]; 1211 target_ulong priority = args[2]; 1212 XiveEND *end; 1213 uint8_t end_blk; 1214 uint32_t end_idx; 1215 1216 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1217 return H_FUNCTION; 1218 } 1219 1220 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1221 return H_PARAMETER; 1222 } 1223 1224 /* 1225 * H_STATE should be returned if a H_INT_RESET is in progress. 1226 * This is not needed when running the emulation under QEMU 1227 */ 1228 1229 if (spapr_xive_priority_is_reserved(priority)) { 1230 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1231 " is reserved\n", priority); 1232 return H_P3; 1233 } 1234 1235 /* 1236 * Validate that "target" is part of the list of threads allocated 1237 * to the partition. For that, find the END corresponding to the 1238 * target. 1239 */ 1240 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1241 return H_P2; 1242 } 1243 1244 assert(end_idx < xive->nr_ends); 1245 end = &xive->endt[end_idx]; 1246 1247 args[0] = 0; 1248 if (xive_end_is_notify(end)) { 1249 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1250 } 1251 1252 if (xive_end_is_enqueue(end)) { 1253 args[1] = xive_end_qaddr(end); 1254 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1255 } else { 1256 args[1] = 0; 1257 args[2] = 0; 1258 } 1259 1260 if (kvm_irqchip_in_kernel()) { 1261 Error *local_err = NULL; 1262 1263 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1264 if (local_err) { 1265 error_report_err(local_err); 1266 return H_HARDWARE; 1267 } 1268 } 1269 1270 /* TODO: do we need any locking on the END ? */ 1271 if (flags & SPAPR_XIVE_END_DEBUG) { 1272 /* Load the event queue generation number into the return flags */ 1273 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1274 1275 /* Load R7 with the event queue offset counter */ 1276 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1277 } else { 1278 args[3] = 0; 1279 } 1280 1281 return H_SUCCESS; 1282 } 1283 1284 /* 1285 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1286 * reporting cache line pair for the calling thread. The reporting 1287 * cache lines will contain the OS interrupt context when the OS 1288 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1289 * interrupt. The reporting cache lines can be reset by inputting -1 1290 * in "reportingLine". Issuing the CI store byte without reporting 1291 * cache lines registered will result in the data not being accessible 1292 * to the OS. 1293 * 1294 * Parameters: 1295 * Input: 1296 * - R4: "flags" 1297 * Bits 0-63: Reserved 1298 * - R5: "reportingLine": The logical real address of the reporting cache 1299 * line pair 1300 * 1301 * Output: 1302 * - None 1303 */ 1304 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1305 SpaprMachineState *spapr, 1306 target_ulong opcode, 1307 target_ulong *args) 1308 { 1309 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1310 return H_FUNCTION; 1311 } 1312 1313 /* 1314 * H_STATE should be returned if a H_INT_RESET is in progress. 1315 * This is not needed when running the emulation under QEMU 1316 */ 1317 1318 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1319 return H_FUNCTION; 1320 } 1321 1322 /* 1323 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1324 * real address of the reporting cache line pair set for the input 1325 * "target". If no reporting cache line pair has been set, -1 is 1326 * returned. 1327 * 1328 * Parameters: 1329 * Input: 1330 * - R4: "flags" 1331 * Bits 0-63: Reserved 1332 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1333 * "ibm,ppc-interrupt-gserver#s" 1334 * - R6: "reportingLine": The logical real address of the reporting 1335 * cache line pair 1336 * 1337 * Output: 1338 * - R4: The logical real address of the reporting line if set, else -1 1339 */ 1340 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1341 SpaprMachineState *spapr, 1342 target_ulong opcode, 1343 target_ulong *args) 1344 { 1345 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1346 return H_FUNCTION; 1347 } 1348 1349 /* 1350 * H_STATE should be returned if a H_INT_RESET is in progress. 1351 * This is not needed when running the emulation under QEMU 1352 */ 1353 1354 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1355 return H_FUNCTION; 1356 } 1357 1358 /* 1359 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1360 * page for the input "lisn". This hcall is only supported for LISNs 1361 * that have the ESB hcall flag set to 1 when returned from hcall() 1362 * H_INT_GET_SOURCE_INFO. 1363 * 1364 * Parameters: 1365 * Input: 1366 * - R4: "flags" 1367 * Bits 0-62: Reserved 1368 * bit 63: Store: Store=1, store operation, else load operation 1369 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1370 * "ibm,xive-lisn-ranges" properties, or as returned by the 1371 * ibm,query-interrupt-source-number RTAS call, or as 1372 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1373 * - R6: "esbOffset" is the offset into the ESB page for the load or 1374 * store operation 1375 * - R7: "storeData" is the data to write for a store operation 1376 * 1377 * Output: 1378 * - R4: The value of the load if load operation, else -1 1379 */ 1380 1381 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1382 1383 static target_ulong h_int_esb(PowerPCCPU *cpu, 1384 SpaprMachineState *spapr, 1385 target_ulong opcode, 1386 target_ulong *args) 1387 { 1388 SpaprXive *xive = spapr->xive; 1389 XiveEAS eas; 1390 target_ulong flags = args[0]; 1391 target_ulong lisn = args[1]; 1392 target_ulong offset = args[2]; 1393 target_ulong data = args[3]; 1394 hwaddr mmio_addr; 1395 XiveSource *xsrc = &xive->source; 1396 1397 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1398 return H_FUNCTION; 1399 } 1400 1401 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1402 return H_PARAMETER; 1403 } 1404 1405 if (lisn >= xive->nr_irqs) { 1406 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1407 lisn); 1408 return H_P2; 1409 } 1410 1411 eas = xive->eat[lisn]; 1412 if (!xive_eas_is_valid(&eas)) { 1413 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1414 lisn); 1415 return H_P2; 1416 } 1417 1418 if (offset > (1ull << xsrc->esb_shift)) { 1419 return H_P3; 1420 } 1421 1422 if (kvm_irqchip_in_kernel()) { 1423 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1424 flags & SPAPR_XIVE_ESB_STORE); 1425 } else { 1426 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1427 1428 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1429 (flags & SPAPR_XIVE_ESB_STORE))) { 1430 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1431 HWADDR_PRIx "\n", mmio_addr); 1432 return H_HARDWARE; 1433 } 1434 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1435 } 1436 return H_SUCCESS; 1437 } 1438 1439 /* 1440 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1441 * ensure any in flight events for the input lisn are in the event 1442 * queue. 1443 * 1444 * Parameters: 1445 * Input: 1446 * - R4: "flags" 1447 * Bits 0-63: Reserved 1448 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1449 * "ibm,xive-lisn-ranges" properties, or as returned by the 1450 * ibm,query-interrupt-source-number RTAS call, or as 1451 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1452 * 1453 * Output: 1454 * - None 1455 */ 1456 static target_ulong h_int_sync(PowerPCCPU *cpu, 1457 SpaprMachineState *spapr, 1458 target_ulong opcode, 1459 target_ulong *args) 1460 { 1461 SpaprXive *xive = spapr->xive; 1462 XiveEAS eas; 1463 target_ulong flags = args[0]; 1464 target_ulong lisn = args[1]; 1465 1466 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1467 return H_FUNCTION; 1468 } 1469 1470 if (flags) { 1471 return H_PARAMETER; 1472 } 1473 1474 if (lisn >= xive->nr_irqs) { 1475 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1476 lisn); 1477 return H_P2; 1478 } 1479 1480 eas = xive->eat[lisn]; 1481 if (!xive_eas_is_valid(&eas)) { 1482 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1483 lisn); 1484 return H_P2; 1485 } 1486 1487 /* 1488 * H_STATE should be returned if a H_INT_RESET is in progress. 1489 * This is not needed when running the emulation under QEMU 1490 */ 1491 1492 /* 1493 * This is not real hardware. Nothing to be done unless when 1494 * under KVM 1495 */ 1496 1497 if (kvm_irqchip_in_kernel()) { 1498 Error *local_err = NULL; 1499 1500 kvmppc_xive_sync_source(xive, lisn, &local_err); 1501 if (local_err) { 1502 error_report_err(local_err); 1503 return H_HARDWARE; 1504 } 1505 } 1506 return H_SUCCESS; 1507 } 1508 1509 /* 1510 * The H_INT_RESET hcall() is used to reset all of the partition's 1511 * interrupt exploitation structures to their initial state. This 1512 * means losing all previously set interrupt state set via 1513 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1514 * 1515 * Parameters: 1516 * Input: 1517 * - R4: "flags" 1518 * Bits 0-63: Reserved 1519 * 1520 * Output: 1521 * - None 1522 */ 1523 static target_ulong h_int_reset(PowerPCCPU *cpu, 1524 SpaprMachineState *spapr, 1525 target_ulong opcode, 1526 target_ulong *args) 1527 { 1528 SpaprXive *xive = spapr->xive; 1529 target_ulong flags = args[0]; 1530 1531 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1532 return H_FUNCTION; 1533 } 1534 1535 if (flags) { 1536 return H_PARAMETER; 1537 } 1538 1539 device_reset(DEVICE(xive)); 1540 1541 if (kvm_irqchip_in_kernel()) { 1542 Error *local_err = NULL; 1543 1544 kvmppc_xive_reset(xive, &local_err); 1545 if (local_err) { 1546 error_report_err(local_err); 1547 return H_HARDWARE; 1548 } 1549 } 1550 return H_SUCCESS; 1551 } 1552 1553 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1554 { 1555 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1556 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1557 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1558 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1559 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1560 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1561 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1562 h_int_set_os_reporting_line); 1563 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1564 h_int_get_os_reporting_line); 1565 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1566 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1567 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1568 } 1569 1570 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1571 uint32_t phandle) 1572 { 1573 SpaprXive *xive = spapr->xive; 1574 int node; 1575 uint64_t timas[2 * 2]; 1576 /* Interrupt number ranges for the IPIs */ 1577 uint32_t lisn_ranges[] = { 1578 cpu_to_be32(0), 1579 cpu_to_be32(nr_servers), 1580 }; 1581 /* 1582 * EQ size - the sizes of pages supported by the system 4K, 64K, 1583 * 2M, 16M. We only advertise 64K for the moment. 1584 */ 1585 uint32_t eq_sizes[] = { 1586 cpu_to_be32(16), /* 64K */ 1587 }; 1588 /* 1589 * The following array is in sync with the reserved priorities 1590 * defined by the 'spapr_xive_priority_is_reserved' routine. 1591 */ 1592 uint32_t plat_res_int_priorities[] = { 1593 cpu_to_be32(7), /* start */ 1594 cpu_to_be32(0xf8), /* count */ 1595 }; 1596 1597 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1598 timas[0] = cpu_to_be64(xive->tm_base + 1599 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1600 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1601 timas[2] = cpu_to_be64(xive->tm_base + 1602 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1603 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1604 1605 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1606 1607 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1608 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1609 1610 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1611 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1612 sizeof(eq_sizes))); 1613 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1614 sizeof(lisn_ranges))); 1615 1616 /* For Linux to link the LSIs to the interrupt controller. */ 1617 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1618 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1619 1620 /* For SLOF */ 1621 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1622 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1623 1624 /* 1625 * The "ibm,plat-res-int-priorities" property defines the priority 1626 * ranges reserved by the hypervisor 1627 */ 1628 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1629 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1630 } 1631