1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "qemu/error-report.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/spapr.h" 19 #include "hw/ppc/spapr_cpu_core.h" 20 #include "hw/ppc/spapr_xive.h" 21 #include "hw/ppc/xive.h" 22 #include "hw/ppc/xive_regs.h" 23 24 /* 25 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 26 * use for the ESB pages and the TIMA pages 27 */ 28 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 29 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 30 31 /* 32 * The allocation of VP blocks is a complex operation in OPAL and the 33 * VP identifiers have a relation with the number of HW chips, the 34 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 35 * controller model does not have the same constraints and can use a 36 * simple mapping scheme of the CPU vcpu_id 37 * 38 * These identifiers are never returned to the OS. 39 */ 40 41 #define SPAPR_XIVE_NVT_BASE 0x400 42 43 /* 44 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value 45 * to the controller block id value. It can nevertheless be changed 46 * for testing purpose. 47 */ 48 #define SPAPR_XIVE_BLOCK_ID 0x0 49 50 /* 51 * sPAPR NVT and END indexing helpers 52 */ 53 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 54 { 55 return nvt_idx - SPAPR_XIVE_NVT_BASE; 56 } 57 58 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 59 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 60 { 61 assert(cpu); 62 63 if (out_nvt_blk) { 64 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 65 } 66 67 if (out_nvt_blk) { 68 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 69 } 70 } 71 72 static int spapr_xive_target_to_nvt(uint32_t target, 73 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 74 { 75 PowerPCCPU *cpu = spapr_find_cpu(target); 76 77 if (!cpu) { 78 return -1; 79 } 80 81 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 82 return 0; 83 } 84 85 /* 86 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 87 * priorities per CPU 88 */ 89 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 90 uint32_t *out_server, uint8_t *out_prio) 91 { 92 93 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 94 95 if (out_server) { 96 *out_server = end_idx >> 3; 97 } 98 99 if (out_prio) { 100 *out_prio = end_idx & 0x7; 101 } 102 return 0; 103 } 104 105 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 106 uint8_t *out_end_blk, uint32_t *out_end_idx) 107 { 108 assert(cpu); 109 110 if (out_end_blk) { 111 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 112 } 113 114 if (out_end_idx) { 115 *out_end_idx = (cpu->vcpu_id << 3) + prio; 116 } 117 } 118 119 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 120 uint8_t *out_end_blk, uint32_t *out_end_idx) 121 { 122 PowerPCCPU *cpu = spapr_find_cpu(target); 123 124 if (!cpu) { 125 return -1; 126 } 127 128 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 129 return 0; 130 } 131 132 /* 133 * On sPAPR machines, use a simplified output for the XIVE END 134 * structure dumping only the information related to the OS EQ. 135 */ 136 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 137 Monitor *mon) 138 { 139 uint64_t qaddr_base = xive_end_qaddr(end); 140 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 141 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 142 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 143 uint32_t qentries = 1 << (qsize + 10); 144 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 145 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 146 147 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 148 spapr_xive_nvt_to_target(0, nvt), 149 priority, qindex, qentries, qaddr_base, qgen); 150 151 xive_end_queue_pic_print_info(end, 6, mon); 152 monitor_printf(mon, "]"); 153 } 154 155 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 156 { 157 XiveSource *xsrc = &xive->source; 158 int i; 159 160 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 161 162 for (i = 0; i < xive->nr_irqs; i++) { 163 uint8_t pq = xive_source_esb_get(xsrc, i); 164 XiveEAS *eas = &xive->eat[i]; 165 166 if (!xive_eas_is_valid(eas)) { 167 continue; 168 } 169 170 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 171 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 172 pq & XIVE_ESB_VAL_P ? 'P' : '-', 173 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 174 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 175 xive_eas_is_masked(eas) ? "M" : " ", 176 (int) xive_get_field64(EAS_END_DATA, eas->w)); 177 178 if (!xive_eas_is_masked(eas)) { 179 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 180 XiveEND *end; 181 182 assert(end_idx < xive->nr_ends); 183 end = &xive->endt[end_idx]; 184 185 if (xive_end_is_valid(end)) { 186 spapr_xive_end_pic_print_info(xive, end, mon); 187 } 188 } 189 monitor_printf(mon, "\n"); 190 } 191 } 192 193 void spapr_xive_map_mmio(SpaprXive *xive) 194 { 195 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 196 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 197 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 198 } 199 200 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 201 { 202 memory_region_set_enabled(&xive->source.esb_mmio, enable); 203 memory_region_set_enabled(&xive->tm_mmio, enable); 204 205 /* Disable the END ESBs until a guest OS makes use of them */ 206 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 207 } 208 209 /* 210 * When a Virtual Processor is scheduled to run on a HW thread, the 211 * hypervisor pushes its identifier in the OS CAM line. Emulate the 212 * same behavior under QEMU. 213 */ 214 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 215 { 216 uint8_t nvt_blk; 217 uint32_t nvt_idx; 218 uint32_t nvt_cam; 219 220 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 221 222 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 223 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 224 } 225 226 static void spapr_xive_end_reset(XiveEND *end) 227 { 228 memset(end, 0, sizeof(*end)); 229 230 /* switch off the escalation and notification ESBs */ 231 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 232 } 233 234 static void spapr_xive_reset(void *dev) 235 { 236 SpaprXive *xive = SPAPR_XIVE(dev); 237 int i; 238 239 /* 240 * The XiveSource has its own reset handler, which mask off all 241 * IRQs (!P|Q) 242 */ 243 244 /* Mask all valid EASs in the IRQ number space. */ 245 for (i = 0; i < xive->nr_irqs; i++) { 246 XiveEAS *eas = &xive->eat[i]; 247 if (xive_eas_is_valid(eas)) { 248 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 249 } else { 250 eas->w = 0; 251 } 252 } 253 254 /* Clear all ENDs */ 255 for (i = 0; i < xive->nr_ends; i++) { 256 spapr_xive_end_reset(&xive->endt[i]); 257 } 258 } 259 260 static void spapr_xive_instance_init(Object *obj) 261 { 262 SpaprXive *xive = SPAPR_XIVE(obj); 263 264 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 265 TYPE_XIVE_SOURCE, &error_abort, NULL); 266 267 object_initialize_child(obj, "end_source", &xive->end_source, 268 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 269 &error_abort, NULL); 270 271 /* Not connected to the KVM XIVE device */ 272 xive->fd = -1; 273 } 274 275 static void spapr_xive_realize(DeviceState *dev, Error **errp) 276 { 277 SpaprXive *xive = SPAPR_XIVE(dev); 278 XiveSource *xsrc = &xive->source; 279 XiveENDSource *end_xsrc = &xive->end_source; 280 Error *local_err = NULL; 281 MachineState *machine = MACHINE(qdev_get_machine()); 282 283 if (!xive->nr_irqs) { 284 error_setg(errp, "Number of interrupt needs to be greater 0"); 285 return; 286 } 287 288 if (!xive->nr_ends) { 289 error_setg(errp, "Number of interrupt needs to be greater 0"); 290 return; 291 } 292 293 /* 294 * Initialize the internal sources, for IPIs and virtual devices. 295 */ 296 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 297 &error_fatal); 298 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 299 &error_fatal); 300 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 301 if (local_err) { 302 error_propagate(errp, local_err); 303 return; 304 } 305 306 /* 307 * Initialize the END ESB source 308 */ 309 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 310 &error_fatal); 311 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 312 &error_fatal); 313 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 314 if (local_err) { 315 error_propagate(errp, local_err); 316 return; 317 } 318 319 /* Set the mapping address of the END ESB pages after the source ESBs */ 320 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 321 322 /* 323 * Allocate the routing tables 324 */ 325 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 326 xive->endt = g_new0(XiveEND, xive->nr_ends); 327 328 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 329 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 330 331 qemu_register_reset(spapr_xive_reset, dev); 332 333 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) { 334 kvmppc_xive_connect(xive, &local_err); 335 if (local_err && machine_kernel_irqchip_required(machine)) { 336 error_prepend(&local_err, 337 "kernel_irqchip requested but unavailable: "); 338 error_propagate(errp, local_err); 339 return; 340 } 341 342 if (!local_err) { 343 return; 344 } 345 346 /* 347 * We failed to initialize the XIVE KVM device, fallback to 348 * emulated mode 349 */ 350 error_prepend(&local_err, "kernel_irqchip allowed but unavailable: "); 351 warn_report_err(local_err); 352 } 353 354 /* TIMA initialization */ 355 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 356 "xive.tima", 4ull << TM_SHIFT); 357 358 /* Define all XIVE MMIO regions on SysBus */ 359 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 360 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 361 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 362 363 /* Map all regions */ 364 spapr_xive_map_mmio(xive); 365 } 366 367 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 368 uint32_t eas_idx, XiveEAS *eas) 369 { 370 SpaprXive *xive = SPAPR_XIVE(xrtr); 371 372 if (eas_idx >= xive->nr_irqs) { 373 return -1; 374 } 375 376 *eas = xive->eat[eas_idx]; 377 return 0; 378 } 379 380 static int spapr_xive_get_end(XiveRouter *xrtr, 381 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 382 { 383 SpaprXive *xive = SPAPR_XIVE(xrtr); 384 385 if (end_idx >= xive->nr_ends) { 386 return -1; 387 } 388 389 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 390 return 0; 391 } 392 393 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 394 uint32_t end_idx, XiveEND *end, 395 uint8_t word_number) 396 { 397 SpaprXive *xive = SPAPR_XIVE(xrtr); 398 399 if (end_idx >= xive->nr_ends) { 400 return -1; 401 } 402 403 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 404 return 0; 405 } 406 407 static int spapr_xive_get_nvt(XiveRouter *xrtr, 408 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 409 { 410 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 411 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 412 413 if (!cpu) { 414 /* TODO: should we assert() if we can find a NVT ? */ 415 return -1; 416 } 417 418 /* 419 * sPAPR does not maintain a NVT table. Return that the NVT is 420 * valid if we have found a matching CPU 421 */ 422 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 423 return 0; 424 } 425 426 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 427 uint32_t nvt_idx, XiveNVT *nvt, 428 uint8_t word_number) 429 { 430 /* 431 * We don't need to write back to the NVTs because the sPAPR 432 * machine should never hit a non-scheduled NVT. It should never 433 * get called. 434 */ 435 g_assert_not_reached(); 436 } 437 438 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 439 { 440 PowerPCCPU *cpu = POWERPC_CPU(cs); 441 442 return spapr_cpu_state(cpu)->tctx; 443 } 444 445 static const VMStateDescription vmstate_spapr_xive_end = { 446 .name = TYPE_SPAPR_XIVE "/end", 447 .version_id = 1, 448 .minimum_version_id = 1, 449 .fields = (VMStateField []) { 450 VMSTATE_UINT32(w0, XiveEND), 451 VMSTATE_UINT32(w1, XiveEND), 452 VMSTATE_UINT32(w2, XiveEND), 453 VMSTATE_UINT32(w3, XiveEND), 454 VMSTATE_UINT32(w4, XiveEND), 455 VMSTATE_UINT32(w5, XiveEND), 456 VMSTATE_UINT32(w6, XiveEND), 457 VMSTATE_UINT32(w7, XiveEND), 458 VMSTATE_END_OF_LIST() 459 }, 460 }; 461 462 static const VMStateDescription vmstate_spapr_xive_eas = { 463 .name = TYPE_SPAPR_XIVE "/eas", 464 .version_id = 1, 465 .minimum_version_id = 1, 466 .fields = (VMStateField []) { 467 VMSTATE_UINT64(w, XiveEAS), 468 VMSTATE_END_OF_LIST() 469 }, 470 }; 471 472 static const VMStateDescription vmstate_spapr_xive = { 473 .name = TYPE_SPAPR_XIVE, 474 .version_id = 1, 475 .minimum_version_id = 1, 476 .fields = (VMStateField[]) { 477 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 478 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 479 vmstate_spapr_xive_eas, XiveEAS), 480 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 481 vmstate_spapr_xive_end, XiveEND), 482 VMSTATE_END_OF_LIST() 483 }, 484 }; 485 486 static Property spapr_xive_properties[] = { 487 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 488 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 489 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 490 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 491 DEFINE_PROP_END_OF_LIST(), 492 }; 493 494 static void spapr_xive_class_init(ObjectClass *klass, void *data) 495 { 496 DeviceClass *dc = DEVICE_CLASS(klass); 497 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 498 499 dc->desc = "sPAPR XIVE Interrupt Controller"; 500 dc->props = spapr_xive_properties; 501 dc->realize = spapr_xive_realize; 502 dc->vmsd = &vmstate_spapr_xive; 503 504 xrc->get_eas = spapr_xive_get_eas; 505 xrc->get_end = spapr_xive_get_end; 506 xrc->write_end = spapr_xive_write_end; 507 xrc->get_nvt = spapr_xive_get_nvt; 508 xrc->write_nvt = spapr_xive_write_nvt; 509 xrc->get_tctx = spapr_xive_get_tctx; 510 } 511 512 static const TypeInfo spapr_xive_info = { 513 .name = TYPE_SPAPR_XIVE, 514 .parent = TYPE_XIVE_ROUTER, 515 .instance_init = spapr_xive_instance_init, 516 .instance_size = sizeof(SpaprXive), 517 .class_init = spapr_xive_class_init, 518 }; 519 520 static void spapr_xive_register_types(void) 521 { 522 type_register_static(&spapr_xive_info); 523 } 524 525 type_init(spapr_xive_register_types) 526 527 bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi) 528 { 529 XiveSource *xsrc = &xive->source; 530 531 if (lisn >= xive->nr_irqs) { 532 return false; 533 } 534 535 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID); 536 if (lsi) { 537 xive_source_irq_set_lsi(xsrc, lisn); 538 } 539 540 if (kvm_irqchip_in_kernel()) { 541 Error *local_err = NULL; 542 543 kvmppc_xive_source_reset_one(xsrc, lisn, &local_err); 544 if (local_err) { 545 error_report_err(local_err); 546 return false; 547 } 548 } 549 550 return true; 551 } 552 553 bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn) 554 { 555 if (lisn >= xive->nr_irqs) { 556 return false; 557 } 558 559 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 560 return true; 561 } 562 563 /* 564 * XIVE hcalls 565 * 566 * The terminology used by the XIVE hcalls is the following : 567 * 568 * TARGET vCPU number 569 * EQ Event Queue assigned by OS to receive event data 570 * ESB page for source interrupt management 571 * LISN Logical Interrupt Source Number identifying a source in the 572 * machine 573 * EISN Effective Interrupt Source Number used by guest OS to 574 * identify source in the guest 575 * 576 * The EAS, END, NVT structures are not exposed. 577 */ 578 579 /* 580 * Linux hosts under OPAL reserve priority 7 for their own escalation 581 * interrupts (DD2.X POWER9). So we only allow the guest to use 582 * priorities [0..6]. 583 */ 584 static bool spapr_xive_priority_is_reserved(uint8_t priority) 585 { 586 switch (priority) { 587 case 0 ... 6: 588 return false; 589 case 7: /* OPAL escalation queue */ 590 default: 591 return true; 592 } 593 } 594 595 /* 596 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 597 * real address of the MMIO page through which the Event State Buffer 598 * entry associated with the value of the "lisn" parameter is managed. 599 * 600 * Parameters: 601 * Input 602 * - R4: "flags" 603 * Bits 0-63 reserved 604 * - R5: "lisn" is per "interrupts", "interrupt-map", or 605 * "ibm,xive-lisn-ranges" properties, or as returned by the 606 * ibm,query-interrupt-source-number RTAS call, or as returned 607 * by the H_ALLOCATE_VAS_WINDOW hcall 608 * 609 * Output 610 * - R4: "flags" 611 * Bits 0-59: Reserved 612 * Bit 60: H_INT_ESB must be used for Event State Buffer 613 * management 614 * Bit 61: 1 == LSI 0 == MSI 615 * Bit 62: the full function page supports trigger 616 * Bit 63: Store EOI Supported 617 * - R5: Logical Real address of full function Event State Buffer 618 * management page, -1 if H_INT_ESB hcall flag is set to 1. 619 * - R6: Logical Real Address of trigger only Event State Buffer 620 * management page or -1. 621 * - R7: Power of 2 page size for the ESB management pages returned in 622 * R5 and R6. 623 */ 624 625 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 626 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 627 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 628 on same page */ 629 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 630 631 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 632 SpaprMachineState *spapr, 633 target_ulong opcode, 634 target_ulong *args) 635 { 636 SpaprXive *xive = spapr->xive; 637 XiveSource *xsrc = &xive->source; 638 target_ulong flags = args[0]; 639 target_ulong lisn = args[1]; 640 641 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 642 return H_FUNCTION; 643 } 644 645 if (flags) { 646 return H_PARAMETER; 647 } 648 649 if (lisn >= xive->nr_irqs) { 650 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 651 lisn); 652 return H_P2; 653 } 654 655 if (!xive_eas_is_valid(&xive->eat[lisn])) { 656 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 657 lisn); 658 return H_P2; 659 } 660 661 /* 662 * All sources are emulated under the main XIVE object and share 663 * the same characteristics. 664 */ 665 args[0] = 0; 666 if (!xive_source_esb_has_2page(xsrc)) { 667 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 668 } 669 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 670 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 671 } 672 673 /* 674 * Force the use of the H_INT_ESB hcall in case of an LSI 675 * interrupt. This is necessary under KVM to re-trigger the 676 * interrupt if the level is still asserted 677 */ 678 if (xive_source_irq_is_lsi(xsrc, lisn)) { 679 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 680 } 681 682 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 683 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 684 } else { 685 args[1] = -1; 686 } 687 688 if (xive_source_esb_has_2page(xsrc) && 689 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 690 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 691 } else { 692 args[2] = -1; 693 } 694 695 if (xive_source_esb_has_2page(xsrc)) { 696 args[3] = xsrc->esb_shift - 1; 697 } else { 698 args[3] = xsrc->esb_shift; 699 } 700 701 return H_SUCCESS; 702 } 703 704 /* 705 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 706 * Interrupt Source to a target. The Logical Interrupt Source is 707 * designated with the "lisn" parameter and the target is designated 708 * with the "target" and "priority" parameters. Upon return from the 709 * hcall(), no additional interrupts will be directed to the old EQ. 710 * 711 * Parameters: 712 * Input: 713 * - R4: "flags" 714 * Bits 0-61: Reserved 715 * Bit 62: set the "eisn" in the EAS 716 * Bit 63: masks the interrupt source in the hardware interrupt 717 * control structure. An interrupt masked by this mechanism will 718 * be dropped, but it's source state bits will still be 719 * set. There is no race-free way of unmasking and restoring the 720 * source. Thus this should only be used in interrupts that are 721 * also masked at the source, and only in cases where the 722 * interrupt is not meant to be used for a large amount of time 723 * because no valid target exists for it for example 724 * - R5: "lisn" is per "interrupts", "interrupt-map", or 725 * "ibm,xive-lisn-ranges" properties, or as returned by the 726 * ibm,query-interrupt-source-number RTAS call, or as returned by 727 * the H_ALLOCATE_VAS_WINDOW hcall 728 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 729 * "ibm,ppc-interrupt-gserver#s" 730 * - R7: "priority" is a valid priority not in 731 * "ibm,plat-res-int-priorities" 732 * - R8: "eisn" is the guest EISN associated with the "lisn" 733 * 734 * Output: 735 * - None 736 */ 737 738 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 739 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 740 741 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 742 SpaprMachineState *spapr, 743 target_ulong opcode, 744 target_ulong *args) 745 { 746 SpaprXive *xive = spapr->xive; 747 XiveEAS eas, new_eas; 748 target_ulong flags = args[0]; 749 target_ulong lisn = args[1]; 750 target_ulong target = args[2]; 751 target_ulong priority = args[3]; 752 target_ulong eisn = args[4]; 753 uint8_t end_blk; 754 uint32_t end_idx; 755 756 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 757 return H_FUNCTION; 758 } 759 760 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 761 return H_PARAMETER; 762 } 763 764 if (lisn >= xive->nr_irqs) { 765 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 766 lisn); 767 return H_P2; 768 } 769 770 eas = xive->eat[lisn]; 771 if (!xive_eas_is_valid(&eas)) { 772 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 773 lisn); 774 return H_P2; 775 } 776 777 /* priority 0xff is used to reset the EAS */ 778 if (priority == 0xff) { 779 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 780 goto out; 781 } 782 783 if (flags & SPAPR_XIVE_SRC_MASK) { 784 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 785 } else { 786 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 787 } 788 789 if (spapr_xive_priority_is_reserved(priority)) { 790 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 791 " is reserved\n", priority); 792 return H_P4; 793 } 794 795 /* 796 * Validate that "target" is part of the list of threads allocated 797 * to the partition. For that, find the END corresponding to the 798 * target. 799 */ 800 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 801 return H_P3; 802 } 803 804 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 805 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 806 807 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 808 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 809 } 810 811 if (kvm_irqchip_in_kernel()) { 812 Error *local_err = NULL; 813 814 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 815 if (local_err) { 816 error_report_err(local_err); 817 return H_HARDWARE; 818 } 819 } 820 821 out: 822 xive->eat[lisn] = new_eas; 823 return H_SUCCESS; 824 } 825 826 /* 827 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 828 * target/priority pair is assigned to the specified Logical Interrupt 829 * Source. 830 * 831 * Parameters: 832 * Input: 833 * - R4: "flags" 834 * Bits 0-63 Reserved 835 * - R5: "lisn" is per "interrupts", "interrupt-map", or 836 * "ibm,xive-lisn-ranges" properties, or as returned by the 837 * ibm,query-interrupt-source-number RTAS call, or as 838 * returned by the H_ALLOCATE_VAS_WINDOW hcall 839 * 840 * Output: 841 * - R4: Target to which the specified Logical Interrupt Source is 842 * assigned 843 * - R5: Priority to which the specified Logical Interrupt Source is 844 * assigned 845 * - R6: EISN for the specified Logical Interrupt Source (this will be 846 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 847 */ 848 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 849 SpaprMachineState *spapr, 850 target_ulong opcode, 851 target_ulong *args) 852 { 853 SpaprXive *xive = spapr->xive; 854 target_ulong flags = args[0]; 855 target_ulong lisn = args[1]; 856 XiveEAS eas; 857 XiveEND *end; 858 uint8_t nvt_blk; 859 uint32_t end_idx, nvt_idx; 860 861 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 862 return H_FUNCTION; 863 } 864 865 if (flags) { 866 return H_PARAMETER; 867 } 868 869 if (lisn >= xive->nr_irqs) { 870 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 871 lisn); 872 return H_P2; 873 } 874 875 eas = xive->eat[lisn]; 876 if (!xive_eas_is_valid(&eas)) { 877 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 878 lisn); 879 return H_P2; 880 } 881 882 /* EAS_END_BLOCK is unused on sPAPR */ 883 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 884 885 assert(end_idx < xive->nr_ends); 886 end = &xive->endt[end_idx]; 887 888 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 889 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 890 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 891 892 if (xive_eas_is_masked(&eas)) { 893 args[1] = 0xff; 894 } else { 895 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 896 } 897 898 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 899 900 return H_SUCCESS; 901 } 902 903 /* 904 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 905 * address of the notification management page associated with the 906 * specified target and priority. 907 * 908 * Parameters: 909 * Input: 910 * - R4: "flags" 911 * Bits 0-63 Reserved 912 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 913 * "ibm,ppc-interrupt-gserver#s" 914 * - R6: "priority" is a valid priority not in 915 * "ibm,plat-res-int-priorities" 916 * 917 * Output: 918 * - R4: Logical real address of notification page 919 * - R5: Power of 2 page size of the notification page 920 */ 921 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 922 SpaprMachineState *spapr, 923 target_ulong opcode, 924 target_ulong *args) 925 { 926 SpaprXive *xive = spapr->xive; 927 XiveENDSource *end_xsrc = &xive->end_source; 928 target_ulong flags = args[0]; 929 target_ulong target = args[1]; 930 target_ulong priority = args[2]; 931 XiveEND *end; 932 uint8_t end_blk; 933 uint32_t end_idx; 934 935 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 936 return H_FUNCTION; 937 } 938 939 if (flags) { 940 return H_PARAMETER; 941 } 942 943 /* 944 * H_STATE should be returned if a H_INT_RESET is in progress. 945 * This is not needed when running the emulation under QEMU 946 */ 947 948 if (spapr_xive_priority_is_reserved(priority)) { 949 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 950 " is reserved\n", priority); 951 return H_P3; 952 } 953 954 /* 955 * Validate that "target" is part of the list of threads allocated 956 * to the partition. For that, find the END corresponding to the 957 * target. 958 */ 959 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 960 return H_P2; 961 } 962 963 assert(end_idx < xive->nr_ends); 964 end = &xive->endt[end_idx]; 965 966 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 967 if (xive_end_is_enqueue(end)) { 968 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 969 } else { 970 args[1] = 0; 971 } 972 973 return H_SUCCESS; 974 } 975 976 /* 977 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 978 * a given "target" and "priority". It is also used to set the 979 * notification config associated with the EQ. An EQ size of 0 is 980 * used to reset the EQ config for a given target and priority. If 981 * resetting the EQ config, the END associated with the given "target" 982 * and "priority" will be changed to disable queueing. 983 * 984 * Upon return from the hcall(), no additional interrupts will be 985 * directed to the old EQ (if one was set). The old EQ (if one was 986 * set) should be investigated for interrupts that occurred prior to 987 * or during the hcall(). 988 * 989 * Parameters: 990 * Input: 991 * - R4: "flags" 992 * Bits 0-62: Reserved 993 * Bit 63: Unconditional Notify (n) per the XIVE spec 994 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 995 * "ibm,ppc-interrupt-gserver#s" 996 * - R6: "priority" is a valid priority not in 997 * "ibm,plat-res-int-priorities" 998 * - R7: "eventQueue": The logical real address of the start of the EQ 999 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1000 * 1001 * Output: 1002 * - None 1003 */ 1004 1005 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1006 1007 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1008 SpaprMachineState *spapr, 1009 target_ulong opcode, 1010 target_ulong *args) 1011 { 1012 SpaprXive *xive = spapr->xive; 1013 target_ulong flags = args[0]; 1014 target_ulong target = args[1]; 1015 target_ulong priority = args[2]; 1016 target_ulong qpage = args[3]; 1017 target_ulong qsize = args[4]; 1018 XiveEND end; 1019 uint8_t end_blk, nvt_blk; 1020 uint32_t end_idx, nvt_idx; 1021 1022 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1023 return H_FUNCTION; 1024 } 1025 1026 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1027 return H_PARAMETER; 1028 } 1029 1030 /* 1031 * H_STATE should be returned if a H_INT_RESET is in progress. 1032 * This is not needed when running the emulation under QEMU 1033 */ 1034 1035 if (spapr_xive_priority_is_reserved(priority)) { 1036 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1037 " is reserved\n", priority); 1038 return H_P3; 1039 } 1040 1041 /* 1042 * Validate that "target" is part of the list of threads allocated 1043 * to the partition. For that, find the END corresponding to the 1044 * target. 1045 */ 1046 1047 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1048 return H_P2; 1049 } 1050 1051 assert(end_idx < xive->nr_ends); 1052 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1053 1054 switch (qsize) { 1055 case 12: 1056 case 16: 1057 case 21: 1058 case 24: 1059 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1060 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1061 " is not naturally aligned with %" HWADDR_PRIx "\n", 1062 qpage, (hwaddr)1 << qsize); 1063 return H_P4; 1064 } 1065 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1066 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1067 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1068 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1069 break; 1070 case 0: 1071 /* reset queue and disable queueing */ 1072 spapr_xive_end_reset(&end); 1073 goto out; 1074 1075 default: 1076 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1077 qsize); 1078 return H_P5; 1079 } 1080 1081 if (qsize) { 1082 hwaddr plen = 1 << qsize; 1083 void *eq; 1084 1085 /* 1086 * Validate the guest EQ. We should also check that the queue 1087 * has been zeroed by the OS. 1088 */ 1089 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1090 MEMTXATTRS_UNSPECIFIED); 1091 if (plen != 1 << qsize) { 1092 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1093 HWADDR_PRIx "\n", qpage); 1094 return H_P4; 1095 } 1096 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1097 } 1098 1099 /* "target" should have been validated above */ 1100 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1101 g_assert_not_reached(); 1102 } 1103 1104 /* 1105 * Ensure the priority and target are correctly set (they will not 1106 * be right after allocation) 1107 */ 1108 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1109 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1110 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1111 1112 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1113 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1114 } else { 1115 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1116 } 1117 1118 /* 1119 * The generation bit for the END starts at 1 and The END page 1120 * offset counter starts at 0. 1121 */ 1122 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1123 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1124 end.w0 |= cpu_to_be32(END_W0_VALID); 1125 1126 /* 1127 * TODO: issue syncs required to ensure all in-flight interrupts 1128 * are complete on the old END 1129 */ 1130 1131 out: 1132 if (kvm_irqchip_in_kernel()) { 1133 Error *local_err = NULL; 1134 1135 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1136 if (local_err) { 1137 error_report_err(local_err); 1138 return H_HARDWARE; 1139 } 1140 } 1141 1142 /* Update END */ 1143 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1144 return H_SUCCESS; 1145 } 1146 1147 /* 1148 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1149 * target and priority. 1150 * 1151 * Parameters: 1152 * Input: 1153 * - R4: "flags" 1154 * Bits 0-62: Reserved 1155 * Bit 63: Debug: Return debug data 1156 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1157 * "ibm,ppc-interrupt-gserver#s" 1158 * - R6: "priority" is a valid priority not in 1159 * "ibm,plat-res-int-priorities" 1160 * 1161 * Output: 1162 * - R4: "flags": 1163 * Bits 0-61: Reserved 1164 * Bit 62: The value of Event Queue Generation Number (g) per 1165 * the XIVE spec if "Debug" = 1 1166 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1167 * - R5: The logical real address of the start of the EQ 1168 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1169 * - R7: The value of Event Queue Offset Counter per XIVE spec 1170 * if "Debug" = 1, else 0 1171 * 1172 */ 1173 1174 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1175 1176 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1177 SpaprMachineState *spapr, 1178 target_ulong opcode, 1179 target_ulong *args) 1180 { 1181 SpaprXive *xive = spapr->xive; 1182 target_ulong flags = args[0]; 1183 target_ulong target = args[1]; 1184 target_ulong priority = args[2]; 1185 XiveEND *end; 1186 uint8_t end_blk; 1187 uint32_t end_idx; 1188 1189 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1190 return H_FUNCTION; 1191 } 1192 1193 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1194 return H_PARAMETER; 1195 } 1196 1197 /* 1198 * H_STATE should be returned if a H_INT_RESET is in progress. 1199 * This is not needed when running the emulation under QEMU 1200 */ 1201 1202 if (spapr_xive_priority_is_reserved(priority)) { 1203 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1204 " is reserved\n", priority); 1205 return H_P3; 1206 } 1207 1208 /* 1209 * Validate that "target" is part of the list of threads allocated 1210 * to the partition. For that, find the END corresponding to the 1211 * target. 1212 */ 1213 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1214 return H_P2; 1215 } 1216 1217 assert(end_idx < xive->nr_ends); 1218 end = &xive->endt[end_idx]; 1219 1220 args[0] = 0; 1221 if (xive_end_is_notify(end)) { 1222 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1223 } 1224 1225 if (xive_end_is_enqueue(end)) { 1226 args[1] = xive_end_qaddr(end); 1227 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1228 } else { 1229 args[1] = 0; 1230 args[2] = 0; 1231 } 1232 1233 if (kvm_irqchip_in_kernel()) { 1234 Error *local_err = NULL; 1235 1236 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1237 if (local_err) { 1238 error_report_err(local_err); 1239 return H_HARDWARE; 1240 } 1241 } 1242 1243 /* TODO: do we need any locking on the END ? */ 1244 if (flags & SPAPR_XIVE_END_DEBUG) { 1245 /* Load the event queue generation number into the return flags */ 1246 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1247 1248 /* Load R7 with the event queue offset counter */ 1249 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1250 } else { 1251 args[3] = 0; 1252 } 1253 1254 return H_SUCCESS; 1255 } 1256 1257 /* 1258 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1259 * reporting cache line pair for the calling thread. The reporting 1260 * cache lines will contain the OS interrupt context when the OS 1261 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1262 * interrupt. The reporting cache lines can be reset by inputting -1 1263 * in "reportingLine". Issuing the CI store byte without reporting 1264 * cache lines registered will result in the data not being accessible 1265 * to the OS. 1266 * 1267 * Parameters: 1268 * Input: 1269 * - R4: "flags" 1270 * Bits 0-63: Reserved 1271 * - R5: "reportingLine": The logical real address of the reporting cache 1272 * line pair 1273 * 1274 * Output: 1275 * - None 1276 */ 1277 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1278 SpaprMachineState *spapr, 1279 target_ulong opcode, 1280 target_ulong *args) 1281 { 1282 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1283 return H_FUNCTION; 1284 } 1285 1286 /* 1287 * H_STATE should be returned if a H_INT_RESET is in progress. 1288 * This is not needed when running the emulation under QEMU 1289 */ 1290 1291 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1292 return H_FUNCTION; 1293 } 1294 1295 /* 1296 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1297 * real address of the reporting cache line pair set for the input 1298 * "target". If no reporting cache line pair has been set, -1 is 1299 * returned. 1300 * 1301 * Parameters: 1302 * Input: 1303 * - R4: "flags" 1304 * Bits 0-63: Reserved 1305 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1306 * "ibm,ppc-interrupt-gserver#s" 1307 * - R6: "reportingLine": The logical real address of the reporting 1308 * cache line pair 1309 * 1310 * Output: 1311 * - R4: The logical real address of the reporting line if set, else -1 1312 */ 1313 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1314 SpaprMachineState *spapr, 1315 target_ulong opcode, 1316 target_ulong *args) 1317 { 1318 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1319 return H_FUNCTION; 1320 } 1321 1322 /* 1323 * H_STATE should be returned if a H_INT_RESET is in progress. 1324 * This is not needed when running the emulation under QEMU 1325 */ 1326 1327 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1328 return H_FUNCTION; 1329 } 1330 1331 /* 1332 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1333 * page for the input "lisn". This hcall is only supported for LISNs 1334 * that have the ESB hcall flag set to 1 when returned from hcall() 1335 * H_INT_GET_SOURCE_INFO. 1336 * 1337 * Parameters: 1338 * Input: 1339 * - R4: "flags" 1340 * Bits 0-62: Reserved 1341 * bit 63: Store: Store=1, store operation, else load operation 1342 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1343 * "ibm,xive-lisn-ranges" properties, or as returned by the 1344 * ibm,query-interrupt-source-number RTAS call, or as 1345 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1346 * - R6: "esbOffset" is the offset into the ESB page for the load or 1347 * store operation 1348 * - R7: "storeData" is the data to write for a store operation 1349 * 1350 * Output: 1351 * - R4: The value of the load if load operation, else -1 1352 */ 1353 1354 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1355 1356 static target_ulong h_int_esb(PowerPCCPU *cpu, 1357 SpaprMachineState *spapr, 1358 target_ulong opcode, 1359 target_ulong *args) 1360 { 1361 SpaprXive *xive = spapr->xive; 1362 XiveEAS eas; 1363 target_ulong flags = args[0]; 1364 target_ulong lisn = args[1]; 1365 target_ulong offset = args[2]; 1366 target_ulong data = args[3]; 1367 hwaddr mmio_addr; 1368 XiveSource *xsrc = &xive->source; 1369 1370 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1371 return H_FUNCTION; 1372 } 1373 1374 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1375 return H_PARAMETER; 1376 } 1377 1378 if (lisn >= xive->nr_irqs) { 1379 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1380 lisn); 1381 return H_P2; 1382 } 1383 1384 eas = xive->eat[lisn]; 1385 if (!xive_eas_is_valid(&eas)) { 1386 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1387 lisn); 1388 return H_P2; 1389 } 1390 1391 if (offset > (1ull << xsrc->esb_shift)) { 1392 return H_P3; 1393 } 1394 1395 if (kvm_irqchip_in_kernel()) { 1396 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1397 flags & SPAPR_XIVE_ESB_STORE); 1398 } else { 1399 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1400 1401 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1402 (flags & SPAPR_XIVE_ESB_STORE))) { 1403 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1404 HWADDR_PRIx "\n", mmio_addr); 1405 return H_HARDWARE; 1406 } 1407 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1408 } 1409 return H_SUCCESS; 1410 } 1411 1412 /* 1413 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1414 * ensure any in flight events for the input lisn are in the event 1415 * queue. 1416 * 1417 * Parameters: 1418 * Input: 1419 * - R4: "flags" 1420 * Bits 0-63: Reserved 1421 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1422 * "ibm,xive-lisn-ranges" properties, or as returned by the 1423 * ibm,query-interrupt-source-number RTAS call, or as 1424 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1425 * 1426 * Output: 1427 * - None 1428 */ 1429 static target_ulong h_int_sync(PowerPCCPU *cpu, 1430 SpaprMachineState *spapr, 1431 target_ulong opcode, 1432 target_ulong *args) 1433 { 1434 SpaprXive *xive = spapr->xive; 1435 XiveEAS eas; 1436 target_ulong flags = args[0]; 1437 target_ulong lisn = args[1]; 1438 1439 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1440 return H_FUNCTION; 1441 } 1442 1443 if (flags) { 1444 return H_PARAMETER; 1445 } 1446 1447 if (lisn >= xive->nr_irqs) { 1448 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1449 lisn); 1450 return H_P2; 1451 } 1452 1453 eas = xive->eat[lisn]; 1454 if (!xive_eas_is_valid(&eas)) { 1455 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1456 lisn); 1457 return H_P2; 1458 } 1459 1460 /* 1461 * H_STATE should be returned if a H_INT_RESET is in progress. 1462 * This is not needed when running the emulation under QEMU 1463 */ 1464 1465 /* 1466 * This is not real hardware. Nothing to be done unless when 1467 * under KVM 1468 */ 1469 1470 if (kvm_irqchip_in_kernel()) { 1471 Error *local_err = NULL; 1472 1473 kvmppc_xive_sync_source(xive, lisn, &local_err); 1474 if (local_err) { 1475 error_report_err(local_err); 1476 return H_HARDWARE; 1477 } 1478 } 1479 return H_SUCCESS; 1480 } 1481 1482 /* 1483 * The H_INT_RESET hcall() is used to reset all of the partition's 1484 * interrupt exploitation structures to their initial state. This 1485 * means losing all previously set interrupt state set via 1486 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1487 * 1488 * Parameters: 1489 * Input: 1490 * - R4: "flags" 1491 * Bits 0-63: Reserved 1492 * 1493 * Output: 1494 * - None 1495 */ 1496 static target_ulong h_int_reset(PowerPCCPU *cpu, 1497 SpaprMachineState *spapr, 1498 target_ulong opcode, 1499 target_ulong *args) 1500 { 1501 SpaprXive *xive = spapr->xive; 1502 target_ulong flags = args[0]; 1503 1504 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1505 return H_FUNCTION; 1506 } 1507 1508 if (flags) { 1509 return H_PARAMETER; 1510 } 1511 1512 device_reset(DEVICE(xive)); 1513 1514 if (kvm_irqchip_in_kernel()) { 1515 Error *local_err = NULL; 1516 1517 kvmppc_xive_reset(xive, &local_err); 1518 if (local_err) { 1519 error_report_err(local_err); 1520 return H_HARDWARE; 1521 } 1522 } 1523 return H_SUCCESS; 1524 } 1525 1526 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1527 { 1528 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1529 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1530 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1531 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1532 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1533 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1534 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1535 h_int_set_os_reporting_line); 1536 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1537 h_int_get_os_reporting_line); 1538 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1539 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1540 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1541 } 1542 1543 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1544 uint32_t phandle) 1545 { 1546 SpaprXive *xive = spapr->xive; 1547 int node; 1548 uint64_t timas[2 * 2]; 1549 /* Interrupt number ranges for the IPIs */ 1550 uint32_t lisn_ranges[] = { 1551 cpu_to_be32(0), 1552 cpu_to_be32(nr_servers), 1553 }; 1554 /* 1555 * EQ size - the sizes of pages supported by the system 4K, 64K, 1556 * 2M, 16M. We only advertise 64K for the moment. 1557 */ 1558 uint32_t eq_sizes[] = { 1559 cpu_to_be32(16), /* 64K */ 1560 }; 1561 /* 1562 * The following array is in sync with the reserved priorities 1563 * defined by the 'spapr_xive_priority_is_reserved' routine. 1564 */ 1565 uint32_t plat_res_int_priorities[] = { 1566 cpu_to_be32(7), /* start */ 1567 cpu_to_be32(0xf8), /* count */ 1568 }; 1569 1570 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1571 timas[0] = cpu_to_be64(xive->tm_base + 1572 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1573 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1574 timas[2] = cpu_to_be64(xive->tm_base + 1575 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1576 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1577 1578 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1579 1580 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1581 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1582 1583 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1584 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1585 sizeof(eq_sizes))); 1586 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1587 sizeof(lisn_ranges))); 1588 1589 /* For Linux to link the LSIs to the interrupt controller. */ 1590 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1591 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1592 1593 /* For SLOF */ 1594 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1595 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1596 1597 /* 1598 * The "ibm,plat-res-int-priorities" property defines the priority 1599 * ranges reserved by the hypervisor 1600 */ 1601 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1602 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1603 } 1604