1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 /* 209 * When a Virtual Processor is scheduled to run on a HW thread, the 210 * hypervisor pushes its identifier in the OS CAM line. Emulate the 211 * same behavior under QEMU. 212 */ 213 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 214 { 215 uint8_t nvt_blk; 216 uint32_t nvt_idx; 217 uint32_t nvt_cam; 218 219 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 220 221 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 222 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 223 } 224 225 static void spapr_xive_end_reset(XiveEND *end) 226 { 227 memset(end, 0, sizeof(*end)); 228 229 /* switch off the escalation and notification ESBs */ 230 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 231 } 232 233 static void spapr_xive_reset(void *dev) 234 { 235 SpaprXive *xive = SPAPR_XIVE(dev); 236 int i; 237 238 /* 239 * The XiveSource has its own reset handler, which mask off all 240 * IRQs (!P|Q) 241 */ 242 243 /* Mask all valid EASs in the IRQ number space. */ 244 for (i = 0; i < xive->nr_irqs; i++) { 245 XiveEAS *eas = &xive->eat[i]; 246 if (xive_eas_is_valid(eas)) { 247 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 248 } else { 249 eas->w = 0; 250 } 251 } 252 253 /* Clear all ENDs */ 254 for (i = 0; i < xive->nr_ends; i++) { 255 spapr_xive_end_reset(&xive->endt[i]); 256 } 257 } 258 259 static void spapr_xive_instance_init(Object *obj) 260 { 261 SpaprXive *xive = SPAPR_XIVE(obj); 262 263 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 264 TYPE_XIVE_SOURCE, &error_abort, NULL); 265 266 object_initialize_child(obj, "end_source", &xive->end_source, 267 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 268 &error_abort, NULL); 269 270 /* Not connected to the KVM XIVE device */ 271 xive->fd = -1; 272 } 273 274 static void spapr_xive_realize(DeviceState *dev, Error **errp) 275 { 276 SpaprXive *xive = SPAPR_XIVE(dev); 277 XiveSource *xsrc = &xive->source; 278 XiveENDSource *end_xsrc = &xive->end_source; 279 Error *local_err = NULL; 280 281 if (!xive->nr_irqs) { 282 error_setg(errp, "Number of interrupt needs to be greater 0"); 283 return; 284 } 285 286 if (!xive->nr_ends) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 /* 292 * Initialize the internal sources, for IPIs and virtual devices. 293 */ 294 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 295 &error_fatal); 296 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 297 &error_fatal); 298 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 299 if (local_err) { 300 error_propagate(errp, local_err); 301 return; 302 } 303 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 304 305 /* 306 * Initialize the END ESB source 307 */ 308 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 309 &error_fatal); 310 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 311 &error_fatal); 312 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 313 if (local_err) { 314 error_propagate(errp, local_err); 315 return; 316 } 317 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 318 319 /* Set the mapping address of the END ESB pages after the source ESBs */ 320 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 321 322 /* 323 * Allocate the routing tables 324 */ 325 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 326 xive->endt = g_new0(XiveEND, xive->nr_ends); 327 328 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 329 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 330 331 qemu_register_reset(spapr_xive_reset, dev); 332 333 /* TIMA initialization */ 334 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 335 "xive.tima", 4ull << TM_SHIFT); 336 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 337 338 /* 339 * Map all regions. These will be enabled or disabled at reset and 340 * can also be overridden by KVM memory regions if active 341 */ 342 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 343 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 344 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 345 } 346 347 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 348 uint32_t eas_idx, XiveEAS *eas) 349 { 350 SpaprXive *xive = SPAPR_XIVE(xrtr); 351 352 if (eas_idx >= xive->nr_irqs) { 353 return -1; 354 } 355 356 *eas = xive->eat[eas_idx]; 357 return 0; 358 } 359 360 static int spapr_xive_get_end(XiveRouter *xrtr, 361 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 362 { 363 SpaprXive *xive = SPAPR_XIVE(xrtr); 364 365 if (end_idx >= xive->nr_ends) { 366 return -1; 367 } 368 369 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 370 return 0; 371 } 372 373 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 374 uint32_t end_idx, XiveEND *end, 375 uint8_t word_number) 376 { 377 SpaprXive *xive = SPAPR_XIVE(xrtr); 378 379 if (end_idx >= xive->nr_ends) { 380 return -1; 381 } 382 383 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 384 return 0; 385 } 386 387 static int spapr_xive_get_nvt(XiveRouter *xrtr, 388 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 389 { 390 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 391 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 392 393 if (!cpu) { 394 /* TODO: should we assert() if we can find a NVT ? */ 395 return -1; 396 } 397 398 /* 399 * sPAPR does not maintain a NVT table. Return that the NVT is 400 * valid if we have found a matching CPU 401 */ 402 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 403 return 0; 404 } 405 406 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 407 uint32_t nvt_idx, XiveNVT *nvt, 408 uint8_t word_number) 409 { 410 /* 411 * We don't need to write back to the NVTs because the sPAPR 412 * machine should never hit a non-scheduled NVT. It should never 413 * get called. 414 */ 415 g_assert_not_reached(); 416 } 417 418 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 419 { 420 PowerPCCPU *cpu = POWERPC_CPU(cs); 421 422 return spapr_cpu_state(cpu)->tctx; 423 } 424 425 static const VMStateDescription vmstate_spapr_xive_end = { 426 .name = TYPE_SPAPR_XIVE "/end", 427 .version_id = 1, 428 .minimum_version_id = 1, 429 .fields = (VMStateField []) { 430 VMSTATE_UINT32(w0, XiveEND), 431 VMSTATE_UINT32(w1, XiveEND), 432 VMSTATE_UINT32(w2, XiveEND), 433 VMSTATE_UINT32(w3, XiveEND), 434 VMSTATE_UINT32(w4, XiveEND), 435 VMSTATE_UINT32(w5, XiveEND), 436 VMSTATE_UINT32(w6, XiveEND), 437 VMSTATE_UINT32(w7, XiveEND), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static const VMStateDescription vmstate_spapr_xive_eas = { 443 .name = TYPE_SPAPR_XIVE "/eas", 444 .version_id = 1, 445 .minimum_version_id = 1, 446 .fields = (VMStateField []) { 447 VMSTATE_UINT64(w, XiveEAS), 448 VMSTATE_END_OF_LIST() 449 }, 450 }; 451 452 static int vmstate_spapr_xive_pre_save(void *opaque) 453 { 454 if (kvm_irqchip_in_kernel()) { 455 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 456 } 457 458 return 0; 459 } 460 461 /* 462 * Called by the sPAPR IRQ backend 'post_load' method at the machine 463 * level. 464 */ 465 int spapr_xive_post_load(SpaprXive *xive, int version_id) 466 { 467 if (kvm_irqchip_in_kernel()) { 468 return kvmppc_xive_post_load(xive, version_id); 469 } 470 471 return 0; 472 } 473 474 static const VMStateDescription vmstate_spapr_xive = { 475 .name = TYPE_SPAPR_XIVE, 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .pre_save = vmstate_spapr_xive_pre_save, 479 .post_load = NULL, /* handled at the machine level */ 480 .fields = (VMStateField[]) { 481 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 483 vmstate_spapr_xive_eas, XiveEAS), 484 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 485 vmstate_spapr_xive_end, XiveEND), 486 VMSTATE_END_OF_LIST() 487 }, 488 }; 489 490 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 491 bool lsi, Error **errp) 492 { 493 SpaprXive *xive = SPAPR_XIVE(intc); 494 XiveSource *xsrc = &xive->source; 495 496 assert(lisn < xive->nr_irqs); 497 498 if (xive_eas_is_valid(&xive->eat[lisn])) { 499 error_setg(errp, "IRQ %d is not free", lisn); 500 return -EBUSY; 501 } 502 503 /* 504 * Set default values when allocating an IRQ number 505 */ 506 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 507 if (lsi) { 508 xive_source_irq_set_lsi(xsrc, lisn); 509 } 510 511 if (kvm_irqchip_in_kernel()) { 512 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 513 } 514 515 return 0; 516 } 517 518 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 519 { 520 SpaprXive *xive = SPAPR_XIVE(intc); 521 assert(lisn < xive->nr_irqs); 522 523 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 524 } 525 526 static Property spapr_xive_properties[] = { 527 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 528 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 529 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 530 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 531 DEFINE_PROP_END_OF_LIST(), 532 }; 533 534 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 535 PowerPCCPU *cpu, Error **errp) 536 { 537 SpaprXive *xive = SPAPR_XIVE(intc); 538 Object *obj; 539 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 540 541 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); 542 if (!obj) { 543 return -1; 544 } 545 546 spapr_cpu->tctx = XIVE_TCTX(obj); 547 548 /* 549 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they 550 * don't beneficiate from the reset of the XIVE IRQ backend 551 */ 552 spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); 553 return 0; 554 } 555 556 static void spapr_xive_class_init(ObjectClass *klass, void *data) 557 { 558 DeviceClass *dc = DEVICE_CLASS(klass); 559 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 560 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 561 562 dc->desc = "sPAPR XIVE Interrupt Controller"; 563 dc->props = spapr_xive_properties; 564 dc->realize = spapr_xive_realize; 565 dc->vmsd = &vmstate_spapr_xive; 566 567 xrc->get_eas = spapr_xive_get_eas; 568 xrc->get_end = spapr_xive_get_end; 569 xrc->write_end = spapr_xive_write_end; 570 xrc->get_nvt = spapr_xive_get_nvt; 571 xrc->write_nvt = spapr_xive_write_nvt; 572 xrc->get_tctx = spapr_xive_get_tctx; 573 574 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 575 sicc->claim_irq = spapr_xive_claim_irq; 576 sicc->free_irq = spapr_xive_free_irq; 577 } 578 579 static const TypeInfo spapr_xive_info = { 580 .name = TYPE_SPAPR_XIVE, 581 .parent = TYPE_XIVE_ROUTER, 582 .instance_init = spapr_xive_instance_init, 583 .instance_size = sizeof(SpaprXive), 584 .class_init = spapr_xive_class_init, 585 .interfaces = (InterfaceInfo[]) { 586 { TYPE_SPAPR_INTC }, 587 { } 588 }, 589 }; 590 591 static void spapr_xive_register_types(void) 592 { 593 type_register_static(&spapr_xive_info); 594 } 595 596 type_init(spapr_xive_register_types) 597 598 /* 599 * XIVE hcalls 600 * 601 * The terminology used by the XIVE hcalls is the following : 602 * 603 * TARGET vCPU number 604 * EQ Event Queue assigned by OS to receive event data 605 * ESB page for source interrupt management 606 * LISN Logical Interrupt Source Number identifying a source in the 607 * machine 608 * EISN Effective Interrupt Source Number used by guest OS to 609 * identify source in the guest 610 * 611 * The EAS, END, NVT structures are not exposed. 612 */ 613 614 /* 615 * Linux hosts under OPAL reserve priority 7 for their own escalation 616 * interrupts (DD2.X POWER9). So we only allow the guest to use 617 * priorities [0..6]. 618 */ 619 static bool spapr_xive_priority_is_reserved(uint8_t priority) 620 { 621 switch (priority) { 622 case 0 ... 6: 623 return false; 624 case 7: /* OPAL escalation queue */ 625 default: 626 return true; 627 } 628 } 629 630 /* 631 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 632 * real address of the MMIO page through which the Event State Buffer 633 * entry associated with the value of the "lisn" parameter is managed. 634 * 635 * Parameters: 636 * Input 637 * - R4: "flags" 638 * Bits 0-63 reserved 639 * - R5: "lisn" is per "interrupts", "interrupt-map", or 640 * "ibm,xive-lisn-ranges" properties, or as returned by the 641 * ibm,query-interrupt-source-number RTAS call, or as returned 642 * by the H_ALLOCATE_VAS_WINDOW hcall 643 * 644 * Output 645 * - R4: "flags" 646 * Bits 0-59: Reserved 647 * Bit 60: H_INT_ESB must be used for Event State Buffer 648 * management 649 * Bit 61: 1 == LSI 0 == MSI 650 * Bit 62: the full function page supports trigger 651 * Bit 63: Store EOI Supported 652 * - R5: Logical Real address of full function Event State Buffer 653 * management page, -1 if H_INT_ESB hcall flag is set to 1. 654 * - R6: Logical Real Address of trigger only Event State Buffer 655 * management page or -1. 656 * - R7: Power of 2 page size for the ESB management pages returned in 657 * R5 and R6. 658 */ 659 660 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 661 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 662 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 663 on same page */ 664 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 665 666 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 667 SpaprMachineState *spapr, 668 target_ulong opcode, 669 target_ulong *args) 670 { 671 SpaprXive *xive = spapr->xive; 672 XiveSource *xsrc = &xive->source; 673 target_ulong flags = args[0]; 674 target_ulong lisn = args[1]; 675 676 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 677 return H_FUNCTION; 678 } 679 680 if (flags) { 681 return H_PARAMETER; 682 } 683 684 if (lisn >= xive->nr_irqs) { 685 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 686 lisn); 687 return H_P2; 688 } 689 690 if (!xive_eas_is_valid(&xive->eat[lisn])) { 691 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 692 lisn); 693 return H_P2; 694 } 695 696 /* 697 * All sources are emulated under the main XIVE object and share 698 * the same characteristics. 699 */ 700 args[0] = 0; 701 if (!xive_source_esb_has_2page(xsrc)) { 702 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 703 } 704 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 705 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 706 } 707 708 /* 709 * Force the use of the H_INT_ESB hcall in case of an LSI 710 * interrupt. This is necessary under KVM to re-trigger the 711 * interrupt if the level is still asserted 712 */ 713 if (xive_source_irq_is_lsi(xsrc, lisn)) { 714 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 715 } 716 717 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 718 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 719 } else { 720 args[1] = -1; 721 } 722 723 if (xive_source_esb_has_2page(xsrc) && 724 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 725 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 726 } else { 727 args[2] = -1; 728 } 729 730 if (xive_source_esb_has_2page(xsrc)) { 731 args[3] = xsrc->esb_shift - 1; 732 } else { 733 args[3] = xsrc->esb_shift; 734 } 735 736 return H_SUCCESS; 737 } 738 739 /* 740 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 741 * Interrupt Source to a target. The Logical Interrupt Source is 742 * designated with the "lisn" parameter and the target is designated 743 * with the "target" and "priority" parameters. Upon return from the 744 * hcall(), no additional interrupts will be directed to the old EQ. 745 * 746 * Parameters: 747 * Input: 748 * - R4: "flags" 749 * Bits 0-61: Reserved 750 * Bit 62: set the "eisn" in the EAS 751 * Bit 63: masks the interrupt source in the hardware interrupt 752 * control structure. An interrupt masked by this mechanism will 753 * be dropped, but it's source state bits will still be 754 * set. There is no race-free way of unmasking and restoring the 755 * source. Thus this should only be used in interrupts that are 756 * also masked at the source, and only in cases where the 757 * interrupt is not meant to be used for a large amount of time 758 * because no valid target exists for it for example 759 * - R5: "lisn" is per "interrupts", "interrupt-map", or 760 * "ibm,xive-lisn-ranges" properties, or as returned by the 761 * ibm,query-interrupt-source-number RTAS call, or as returned by 762 * the H_ALLOCATE_VAS_WINDOW hcall 763 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 764 * "ibm,ppc-interrupt-gserver#s" 765 * - R7: "priority" is a valid priority not in 766 * "ibm,plat-res-int-priorities" 767 * - R8: "eisn" is the guest EISN associated with the "lisn" 768 * 769 * Output: 770 * - None 771 */ 772 773 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 774 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 775 776 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 777 SpaprMachineState *spapr, 778 target_ulong opcode, 779 target_ulong *args) 780 { 781 SpaprXive *xive = spapr->xive; 782 XiveEAS eas, new_eas; 783 target_ulong flags = args[0]; 784 target_ulong lisn = args[1]; 785 target_ulong target = args[2]; 786 target_ulong priority = args[3]; 787 target_ulong eisn = args[4]; 788 uint8_t end_blk; 789 uint32_t end_idx; 790 791 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 792 return H_FUNCTION; 793 } 794 795 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 796 return H_PARAMETER; 797 } 798 799 if (lisn >= xive->nr_irqs) { 800 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 801 lisn); 802 return H_P2; 803 } 804 805 eas = xive->eat[lisn]; 806 if (!xive_eas_is_valid(&eas)) { 807 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 808 lisn); 809 return H_P2; 810 } 811 812 /* priority 0xff is used to reset the EAS */ 813 if (priority == 0xff) { 814 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 815 goto out; 816 } 817 818 if (flags & SPAPR_XIVE_SRC_MASK) { 819 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 820 } else { 821 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 822 } 823 824 if (spapr_xive_priority_is_reserved(priority)) { 825 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 826 " is reserved\n", priority); 827 return H_P4; 828 } 829 830 /* 831 * Validate that "target" is part of the list of threads allocated 832 * to the partition. For that, find the END corresponding to the 833 * target. 834 */ 835 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 836 return H_P3; 837 } 838 839 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 840 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 841 842 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 843 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 844 } 845 846 if (kvm_irqchip_in_kernel()) { 847 Error *local_err = NULL; 848 849 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 850 if (local_err) { 851 error_report_err(local_err); 852 return H_HARDWARE; 853 } 854 } 855 856 out: 857 xive->eat[lisn] = new_eas; 858 return H_SUCCESS; 859 } 860 861 /* 862 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 863 * target/priority pair is assigned to the specified Logical Interrupt 864 * Source. 865 * 866 * Parameters: 867 * Input: 868 * - R4: "flags" 869 * Bits 0-63 Reserved 870 * - R5: "lisn" is per "interrupts", "interrupt-map", or 871 * "ibm,xive-lisn-ranges" properties, or as returned by the 872 * ibm,query-interrupt-source-number RTAS call, or as 873 * returned by the H_ALLOCATE_VAS_WINDOW hcall 874 * 875 * Output: 876 * - R4: Target to which the specified Logical Interrupt Source is 877 * assigned 878 * - R5: Priority to which the specified Logical Interrupt Source is 879 * assigned 880 * - R6: EISN for the specified Logical Interrupt Source (this will be 881 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 882 */ 883 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 884 SpaprMachineState *spapr, 885 target_ulong opcode, 886 target_ulong *args) 887 { 888 SpaprXive *xive = spapr->xive; 889 target_ulong flags = args[0]; 890 target_ulong lisn = args[1]; 891 XiveEAS eas; 892 XiveEND *end; 893 uint8_t nvt_blk; 894 uint32_t end_idx, nvt_idx; 895 896 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 897 return H_FUNCTION; 898 } 899 900 if (flags) { 901 return H_PARAMETER; 902 } 903 904 if (lisn >= xive->nr_irqs) { 905 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 906 lisn); 907 return H_P2; 908 } 909 910 eas = xive->eat[lisn]; 911 if (!xive_eas_is_valid(&eas)) { 912 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 913 lisn); 914 return H_P2; 915 } 916 917 /* EAS_END_BLOCK is unused on sPAPR */ 918 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 919 920 assert(end_idx < xive->nr_ends); 921 end = &xive->endt[end_idx]; 922 923 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 924 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 925 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 926 927 if (xive_eas_is_masked(&eas)) { 928 args[1] = 0xff; 929 } else { 930 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 931 } 932 933 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 934 935 return H_SUCCESS; 936 } 937 938 /* 939 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 940 * address of the notification management page associated with the 941 * specified target and priority. 942 * 943 * Parameters: 944 * Input: 945 * - R4: "flags" 946 * Bits 0-63 Reserved 947 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 948 * "ibm,ppc-interrupt-gserver#s" 949 * - R6: "priority" is a valid priority not in 950 * "ibm,plat-res-int-priorities" 951 * 952 * Output: 953 * - R4: Logical real address of notification page 954 * - R5: Power of 2 page size of the notification page 955 */ 956 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 957 SpaprMachineState *spapr, 958 target_ulong opcode, 959 target_ulong *args) 960 { 961 SpaprXive *xive = spapr->xive; 962 XiveENDSource *end_xsrc = &xive->end_source; 963 target_ulong flags = args[0]; 964 target_ulong target = args[1]; 965 target_ulong priority = args[2]; 966 XiveEND *end; 967 uint8_t end_blk; 968 uint32_t end_idx; 969 970 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 971 return H_FUNCTION; 972 } 973 974 if (flags) { 975 return H_PARAMETER; 976 } 977 978 /* 979 * H_STATE should be returned if a H_INT_RESET is in progress. 980 * This is not needed when running the emulation under QEMU 981 */ 982 983 if (spapr_xive_priority_is_reserved(priority)) { 984 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 985 " is reserved\n", priority); 986 return H_P3; 987 } 988 989 /* 990 * Validate that "target" is part of the list of threads allocated 991 * to the partition. For that, find the END corresponding to the 992 * target. 993 */ 994 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 995 return H_P2; 996 } 997 998 assert(end_idx < xive->nr_ends); 999 end = &xive->endt[end_idx]; 1000 1001 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1002 if (xive_end_is_enqueue(end)) { 1003 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1004 } else { 1005 args[1] = 0; 1006 } 1007 1008 return H_SUCCESS; 1009 } 1010 1011 /* 1012 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1013 * a given "target" and "priority". It is also used to set the 1014 * notification config associated with the EQ. An EQ size of 0 is 1015 * used to reset the EQ config for a given target and priority. If 1016 * resetting the EQ config, the END associated with the given "target" 1017 * and "priority" will be changed to disable queueing. 1018 * 1019 * Upon return from the hcall(), no additional interrupts will be 1020 * directed to the old EQ (if one was set). The old EQ (if one was 1021 * set) should be investigated for interrupts that occurred prior to 1022 * or during the hcall(). 1023 * 1024 * Parameters: 1025 * Input: 1026 * - R4: "flags" 1027 * Bits 0-62: Reserved 1028 * Bit 63: Unconditional Notify (n) per the XIVE spec 1029 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1030 * "ibm,ppc-interrupt-gserver#s" 1031 * - R6: "priority" is a valid priority not in 1032 * "ibm,plat-res-int-priorities" 1033 * - R7: "eventQueue": The logical real address of the start of the EQ 1034 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1035 * 1036 * Output: 1037 * - None 1038 */ 1039 1040 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1041 1042 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1043 SpaprMachineState *spapr, 1044 target_ulong opcode, 1045 target_ulong *args) 1046 { 1047 SpaprXive *xive = spapr->xive; 1048 target_ulong flags = args[0]; 1049 target_ulong target = args[1]; 1050 target_ulong priority = args[2]; 1051 target_ulong qpage = args[3]; 1052 target_ulong qsize = args[4]; 1053 XiveEND end; 1054 uint8_t end_blk, nvt_blk; 1055 uint32_t end_idx, nvt_idx; 1056 1057 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1058 return H_FUNCTION; 1059 } 1060 1061 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1062 return H_PARAMETER; 1063 } 1064 1065 /* 1066 * H_STATE should be returned if a H_INT_RESET is in progress. 1067 * This is not needed when running the emulation under QEMU 1068 */ 1069 1070 if (spapr_xive_priority_is_reserved(priority)) { 1071 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1072 " is reserved\n", priority); 1073 return H_P3; 1074 } 1075 1076 /* 1077 * Validate that "target" is part of the list of threads allocated 1078 * to the partition. For that, find the END corresponding to the 1079 * target. 1080 */ 1081 1082 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1083 return H_P2; 1084 } 1085 1086 assert(end_idx < xive->nr_ends); 1087 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1088 1089 switch (qsize) { 1090 case 12: 1091 case 16: 1092 case 21: 1093 case 24: 1094 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1095 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1096 " is not naturally aligned with %" HWADDR_PRIx "\n", 1097 qpage, (hwaddr)1 << qsize); 1098 return H_P4; 1099 } 1100 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1101 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1102 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1103 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1104 break; 1105 case 0: 1106 /* reset queue and disable queueing */ 1107 spapr_xive_end_reset(&end); 1108 goto out; 1109 1110 default: 1111 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1112 qsize); 1113 return H_P5; 1114 } 1115 1116 if (qsize) { 1117 hwaddr plen = 1 << qsize; 1118 void *eq; 1119 1120 /* 1121 * Validate the guest EQ. We should also check that the queue 1122 * has been zeroed by the OS. 1123 */ 1124 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1125 MEMTXATTRS_UNSPECIFIED); 1126 if (plen != 1 << qsize) { 1127 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1128 HWADDR_PRIx "\n", qpage); 1129 return H_P4; 1130 } 1131 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1132 } 1133 1134 /* "target" should have been validated above */ 1135 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1136 g_assert_not_reached(); 1137 } 1138 1139 /* 1140 * Ensure the priority and target are correctly set (they will not 1141 * be right after allocation) 1142 */ 1143 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1144 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1145 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1146 1147 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1148 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1149 } else { 1150 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1151 } 1152 1153 /* 1154 * The generation bit for the END starts at 1 and The END page 1155 * offset counter starts at 0. 1156 */ 1157 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1158 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1159 end.w0 |= cpu_to_be32(END_W0_VALID); 1160 1161 /* 1162 * TODO: issue syncs required to ensure all in-flight interrupts 1163 * are complete on the old END 1164 */ 1165 1166 out: 1167 if (kvm_irqchip_in_kernel()) { 1168 Error *local_err = NULL; 1169 1170 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1171 if (local_err) { 1172 error_report_err(local_err); 1173 return H_HARDWARE; 1174 } 1175 } 1176 1177 /* Update END */ 1178 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1179 return H_SUCCESS; 1180 } 1181 1182 /* 1183 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1184 * target and priority. 1185 * 1186 * Parameters: 1187 * Input: 1188 * - R4: "flags" 1189 * Bits 0-62: Reserved 1190 * Bit 63: Debug: Return debug data 1191 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1192 * "ibm,ppc-interrupt-gserver#s" 1193 * - R6: "priority" is a valid priority not in 1194 * "ibm,plat-res-int-priorities" 1195 * 1196 * Output: 1197 * - R4: "flags": 1198 * Bits 0-61: Reserved 1199 * Bit 62: The value of Event Queue Generation Number (g) per 1200 * the XIVE spec if "Debug" = 1 1201 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1202 * - R5: The logical real address of the start of the EQ 1203 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1204 * - R7: The value of Event Queue Offset Counter per XIVE spec 1205 * if "Debug" = 1, else 0 1206 * 1207 */ 1208 1209 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1210 1211 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1212 SpaprMachineState *spapr, 1213 target_ulong opcode, 1214 target_ulong *args) 1215 { 1216 SpaprXive *xive = spapr->xive; 1217 target_ulong flags = args[0]; 1218 target_ulong target = args[1]; 1219 target_ulong priority = args[2]; 1220 XiveEND *end; 1221 uint8_t end_blk; 1222 uint32_t end_idx; 1223 1224 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1225 return H_FUNCTION; 1226 } 1227 1228 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1229 return H_PARAMETER; 1230 } 1231 1232 /* 1233 * H_STATE should be returned if a H_INT_RESET is in progress. 1234 * This is not needed when running the emulation under QEMU 1235 */ 1236 1237 if (spapr_xive_priority_is_reserved(priority)) { 1238 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1239 " is reserved\n", priority); 1240 return H_P3; 1241 } 1242 1243 /* 1244 * Validate that "target" is part of the list of threads allocated 1245 * to the partition. For that, find the END corresponding to the 1246 * target. 1247 */ 1248 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1249 return H_P2; 1250 } 1251 1252 assert(end_idx < xive->nr_ends); 1253 end = &xive->endt[end_idx]; 1254 1255 args[0] = 0; 1256 if (xive_end_is_notify(end)) { 1257 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1258 } 1259 1260 if (xive_end_is_enqueue(end)) { 1261 args[1] = xive_end_qaddr(end); 1262 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1263 } else { 1264 args[1] = 0; 1265 args[2] = 0; 1266 } 1267 1268 if (kvm_irqchip_in_kernel()) { 1269 Error *local_err = NULL; 1270 1271 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1272 if (local_err) { 1273 error_report_err(local_err); 1274 return H_HARDWARE; 1275 } 1276 } 1277 1278 /* TODO: do we need any locking on the END ? */ 1279 if (flags & SPAPR_XIVE_END_DEBUG) { 1280 /* Load the event queue generation number into the return flags */ 1281 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1282 1283 /* Load R7 with the event queue offset counter */ 1284 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1285 } else { 1286 args[3] = 0; 1287 } 1288 1289 return H_SUCCESS; 1290 } 1291 1292 /* 1293 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1294 * reporting cache line pair for the calling thread. The reporting 1295 * cache lines will contain the OS interrupt context when the OS 1296 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1297 * interrupt. The reporting cache lines can be reset by inputting -1 1298 * in "reportingLine". Issuing the CI store byte without reporting 1299 * cache lines registered will result in the data not being accessible 1300 * to the OS. 1301 * 1302 * Parameters: 1303 * Input: 1304 * - R4: "flags" 1305 * Bits 0-63: Reserved 1306 * - R5: "reportingLine": The logical real address of the reporting cache 1307 * line pair 1308 * 1309 * Output: 1310 * - None 1311 */ 1312 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1313 SpaprMachineState *spapr, 1314 target_ulong opcode, 1315 target_ulong *args) 1316 { 1317 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1318 return H_FUNCTION; 1319 } 1320 1321 /* 1322 * H_STATE should be returned if a H_INT_RESET is in progress. 1323 * This is not needed when running the emulation under QEMU 1324 */ 1325 1326 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1327 return H_FUNCTION; 1328 } 1329 1330 /* 1331 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1332 * real address of the reporting cache line pair set for the input 1333 * "target". If no reporting cache line pair has been set, -1 is 1334 * returned. 1335 * 1336 * Parameters: 1337 * Input: 1338 * - R4: "flags" 1339 * Bits 0-63: Reserved 1340 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1341 * "ibm,ppc-interrupt-gserver#s" 1342 * - R6: "reportingLine": The logical real address of the reporting 1343 * cache line pair 1344 * 1345 * Output: 1346 * - R4: The logical real address of the reporting line if set, else -1 1347 */ 1348 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1349 SpaprMachineState *spapr, 1350 target_ulong opcode, 1351 target_ulong *args) 1352 { 1353 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1354 return H_FUNCTION; 1355 } 1356 1357 /* 1358 * H_STATE should be returned if a H_INT_RESET is in progress. 1359 * This is not needed when running the emulation under QEMU 1360 */ 1361 1362 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1363 return H_FUNCTION; 1364 } 1365 1366 /* 1367 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1368 * page for the input "lisn". This hcall is only supported for LISNs 1369 * that have the ESB hcall flag set to 1 when returned from hcall() 1370 * H_INT_GET_SOURCE_INFO. 1371 * 1372 * Parameters: 1373 * Input: 1374 * - R4: "flags" 1375 * Bits 0-62: Reserved 1376 * bit 63: Store: Store=1, store operation, else load operation 1377 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1378 * "ibm,xive-lisn-ranges" properties, or as returned by the 1379 * ibm,query-interrupt-source-number RTAS call, or as 1380 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1381 * - R6: "esbOffset" is the offset into the ESB page for the load or 1382 * store operation 1383 * - R7: "storeData" is the data to write for a store operation 1384 * 1385 * Output: 1386 * - R4: The value of the load if load operation, else -1 1387 */ 1388 1389 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1390 1391 static target_ulong h_int_esb(PowerPCCPU *cpu, 1392 SpaprMachineState *spapr, 1393 target_ulong opcode, 1394 target_ulong *args) 1395 { 1396 SpaprXive *xive = spapr->xive; 1397 XiveEAS eas; 1398 target_ulong flags = args[0]; 1399 target_ulong lisn = args[1]; 1400 target_ulong offset = args[2]; 1401 target_ulong data = args[3]; 1402 hwaddr mmio_addr; 1403 XiveSource *xsrc = &xive->source; 1404 1405 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1406 return H_FUNCTION; 1407 } 1408 1409 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1410 return H_PARAMETER; 1411 } 1412 1413 if (lisn >= xive->nr_irqs) { 1414 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1415 lisn); 1416 return H_P2; 1417 } 1418 1419 eas = xive->eat[lisn]; 1420 if (!xive_eas_is_valid(&eas)) { 1421 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1422 lisn); 1423 return H_P2; 1424 } 1425 1426 if (offset > (1ull << xsrc->esb_shift)) { 1427 return H_P3; 1428 } 1429 1430 if (kvm_irqchip_in_kernel()) { 1431 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1432 flags & SPAPR_XIVE_ESB_STORE); 1433 } else { 1434 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1435 1436 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1437 (flags & SPAPR_XIVE_ESB_STORE))) { 1438 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1439 HWADDR_PRIx "\n", mmio_addr); 1440 return H_HARDWARE; 1441 } 1442 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1443 } 1444 return H_SUCCESS; 1445 } 1446 1447 /* 1448 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1449 * ensure any in flight events for the input lisn are in the event 1450 * queue. 1451 * 1452 * Parameters: 1453 * Input: 1454 * - R4: "flags" 1455 * Bits 0-63: Reserved 1456 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1457 * "ibm,xive-lisn-ranges" properties, or as returned by the 1458 * ibm,query-interrupt-source-number RTAS call, or as 1459 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1460 * 1461 * Output: 1462 * - None 1463 */ 1464 static target_ulong h_int_sync(PowerPCCPU *cpu, 1465 SpaprMachineState *spapr, 1466 target_ulong opcode, 1467 target_ulong *args) 1468 { 1469 SpaprXive *xive = spapr->xive; 1470 XiveEAS eas; 1471 target_ulong flags = args[0]; 1472 target_ulong lisn = args[1]; 1473 1474 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1475 return H_FUNCTION; 1476 } 1477 1478 if (flags) { 1479 return H_PARAMETER; 1480 } 1481 1482 if (lisn >= xive->nr_irqs) { 1483 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1484 lisn); 1485 return H_P2; 1486 } 1487 1488 eas = xive->eat[lisn]; 1489 if (!xive_eas_is_valid(&eas)) { 1490 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1491 lisn); 1492 return H_P2; 1493 } 1494 1495 /* 1496 * H_STATE should be returned if a H_INT_RESET is in progress. 1497 * This is not needed when running the emulation under QEMU 1498 */ 1499 1500 /* 1501 * This is not real hardware. Nothing to be done unless when 1502 * under KVM 1503 */ 1504 1505 if (kvm_irqchip_in_kernel()) { 1506 Error *local_err = NULL; 1507 1508 kvmppc_xive_sync_source(xive, lisn, &local_err); 1509 if (local_err) { 1510 error_report_err(local_err); 1511 return H_HARDWARE; 1512 } 1513 } 1514 return H_SUCCESS; 1515 } 1516 1517 /* 1518 * The H_INT_RESET hcall() is used to reset all of the partition's 1519 * interrupt exploitation structures to their initial state. This 1520 * means losing all previously set interrupt state set via 1521 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1522 * 1523 * Parameters: 1524 * Input: 1525 * - R4: "flags" 1526 * Bits 0-63: Reserved 1527 * 1528 * Output: 1529 * - None 1530 */ 1531 static target_ulong h_int_reset(PowerPCCPU *cpu, 1532 SpaprMachineState *spapr, 1533 target_ulong opcode, 1534 target_ulong *args) 1535 { 1536 SpaprXive *xive = spapr->xive; 1537 target_ulong flags = args[0]; 1538 1539 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1540 return H_FUNCTION; 1541 } 1542 1543 if (flags) { 1544 return H_PARAMETER; 1545 } 1546 1547 device_reset(DEVICE(xive)); 1548 1549 if (kvm_irqchip_in_kernel()) { 1550 Error *local_err = NULL; 1551 1552 kvmppc_xive_reset(xive, &local_err); 1553 if (local_err) { 1554 error_report_err(local_err); 1555 return H_HARDWARE; 1556 } 1557 } 1558 return H_SUCCESS; 1559 } 1560 1561 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1562 { 1563 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1564 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1565 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1566 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1567 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1568 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1569 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1570 h_int_set_os_reporting_line); 1571 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1572 h_int_get_os_reporting_line); 1573 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1574 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1575 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1576 } 1577 1578 void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt, 1579 uint32_t phandle) 1580 { 1581 SpaprXive *xive = spapr->xive; 1582 int node; 1583 uint64_t timas[2 * 2]; 1584 /* Interrupt number ranges for the IPIs */ 1585 uint32_t lisn_ranges[] = { 1586 cpu_to_be32(0), 1587 cpu_to_be32(nr_servers), 1588 }; 1589 /* 1590 * EQ size - the sizes of pages supported by the system 4K, 64K, 1591 * 2M, 16M. We only advertise 64K for the moment. 1592 */ 1593 uint32_t eq_sizes[] = { 1594 cpu_to_be32(16), /* 64K */ 1595 }; 1596 /* 1597 * The following array is in sync with the reserved priorities 1598 * defined by the 'spapr_xive_priority_is_reserved' routine. 1599 */ 1600 uint32_t plat_res_int_priorities[] = { 1601 cpu_to_be32(7), /* start */ 1602 cpu_to_be32(0xf8), /* count */ 1603 }; 1604 1605 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 1606 timas[0] = cpu_to_be64(xive->tm_base + 1607 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 1608 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 1609 timas[2] = cpu_to_be64(xive->tm_base + 1610 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 1611 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 1612 1613 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 1614 1615 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 1616 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 1617 1618 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 1619 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 1620 sizeof(eq_sizes))); 1621 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 1622 sizeof(lisn_ranges))); 1623 1624 /* For Linux to link the LSIs to the interrupt controller. */ 1625 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 1626 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 1627 1628 /* For SLOF */ 1629 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 1630 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 1631 1632 /* 1633 * The "ibm,plat-res-int-priorities" property defines the priority 1634 * ranges reserved by the hypervisor 1635 */ 1636 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 1637 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 1638 } 1639