1 /* 2 * QEMU PowerPC sPAPR XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2018, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qemu/error-report.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/reset.h" 18 #include "migration/vmstate.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/fdt.h" 21 #include "hw/ppc/spapr.h" 22 #include "hw/ppc/spapr_cpu_core.h" 23 #include "hw/ppc/spapr_xive.h" 24 #include "hw/ppc/xive.h" 25 #include "hw/ppc/xive_regs.h" 26 #include "hw/qdev-properties.h" 27 28 /* 29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we 30 * use for the ESB pages and the TIMA pages 31 */ 32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull 33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull 34 35 /* 36 * The allocation of VP blocks is a complex operation in OPAL and the 37 * VP identifiers have a relation with the number of HW chips, the 38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE 39 * controller model does not have the same constraints and can use a 40 * simple mapping scheme of the CPU vcpu_id 41 * 42 * These identifiers are never returned to the OS. 43 */ 44 45 #define SPAPR_XIVE_NVT_BASE 0x400 46 47 /* 48 * sPAPR NVT and END indexing helpers 49 */ 50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk, uint32_t nvt_idx) 51 { 52 return nvt_idx - SPAPR_XIVE_NVT_BASE; 53 } 54 55 static void spapr_xive_cpu_to_nvt(PowerPCCPU *cpu, 56 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 57 { 58 assert(cpu); 59 60 if (out_nvt_blk) { 61 *out_nvt_blk = SPAPR_XIVE_BLOCK_ID; 62 } 63 64 if (out_nvt_blk) { 65 *out_nvt_idx = SPAPR_XIVE_NVT_BASE + cpu->vcpu_id; 66 } 67 } 68 69 static int spapr_xive_target_to_nvt(uint32_t target, 70 uint8_t *out_nvt_blk, uint32_t *out_nvt_idx) 71 { 72 PowerPCCPU *cpu = spapr_find_cpu(target); 73 74 if (!cpu) { 75 return -1; 76 } 77 78 spapr_xive_cpu_to_nvt(cpu, out_nvt_blk, out_nvt_idx); 79 return 0; 80 } 81 82 /* 83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8 84 * priorities per CPU 85 */ 86 int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, 87 uint32_t *out_server, uint8_t *out_prio) 88 { 89 90 assert(end_blk == SPAPR_XIVE_BLOCK_ID); 91 92 if (out_server) { 93 *out_server = end_idx >> 3; 94 } 95 96 if (out_prio) { 97 *out_prio = end_idx & 0x7; 98 } 99 return 0; 100 } 101 102 static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio, 103 uint8_t *out_end_blk, uint32_t *out_end_idx) 104 { 105 assert(cpu); 106 107 if (out_end_blk) { 108 *out_end_blk = SPAPR_XIVE_BLOCK_ID; 109 } 110 111 if (out_end_idx) { 112 *out_end_idx = (cpu->vcpu_id << 3) + prio; 113 } 114 } 115 116 static int spapr_xive_target_to_end(uint32_t target, uint8_t prio, 117 uint8_t *out_end_blk, uint32_t *out_end_idx) 118 { 119 PowerPCCPU *cpu = spapr_find_cpu(target); 120 121 if (!cpu) { 122 return -1; 123 } 124 125 spapr_xive_cpu_to_end(cpu, prio, out_end_blk, out_end_idx); 126 return 0; 127 } 128 129 /* 130 * On sPAPR machines, use a simplified output for the XIVE END 131 * structure dumping only the information related to the OS EQ. 132 */ 133 static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, 134 Monitor *mon) 135 { 136 uint64_t qaddr_base = xive_end_qaddr(end); 137 uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1); 138 uint32_t qgen = xive_get_field32(END_W1_GENERATION, end->w1); 139 uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0); 140 uint32_t qentries = 1 << (qsize + 10); 141 uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6); 142 uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 143 144 monitor_printf(mon, "%3d/%d % 6d/%5d @%"PRIx64" ^%d", 145 spapr_xive_nvt_to_target(0, nvt), 146 priority, qindex, qentries, qaddr_base, qgen); 147 148 xive_end_queue_pic_print_info(end, 6, mon); 149 } 150 151 void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) 152 { 153 XiveSource *xsrc = &xive->source; 154 int i; 155 156 if (kvm_irqchip_in_kernel()) { 157 Error *local_err = NULL; 158 159 kvmppc_xive_synchronize_state(xive, &local_err); 160 if (local_err) { 161 error_report_err(local_err); 162 return; 163 } 164 } 165 166 monitor_printf(mon, " LISN PQ EISN CPU/PRIO EQ\n"); 167 168 for (i = 0; i < xive->nr_irqs; i++) { 169 uint8_t pq = xive_source_esb_get(xsrc, i); 170 XiveEAS *eas = &xive->eat[i]; 171 172 if (!xive_eas_is_valid(eas)) { 173 continue; 174 } 175 176 monitor_printf(mon, " %08x %s %c%c%c %s %08x ", i, 177 xive_source_irq_is_lsi(xsrc, i) ? "LSI" : "MSI", 178 pq & XIVE_ESB_VAL_P ? 'P' : '-', 179 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 180 xsrc->status[i] & XIVE_STATUS_ASSERTED ? 'A' : ' ', 181 xive_eas_is_masked(eas) ? "M" : " ", 182 (int) xive_get_field64(EAS_END_DATA, eas->w)); 183 184 if (!xive_eas_is_masked(eas)) { 185 uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); 186 XiveEND *end; 187 188 assert(end_idx < xive->nr_ends); 189 end = &xive->endt[end_idx]; 190 191 if (xive_end_is_valid(end)) { 192 spapr_xive_end_pic_print_info(xive, end, mon); 193 } 194 } 195 monitor_printf(mon, "\n"); 196 } 197 } 198 199 void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) 200 { 201 memory_region_set_enabled(&xive->source.esb_mmio, enable); 202 memory_region_set_enabled(&xive->tm_mmio, enable); 203 204 /* Disable the END ESBs until a guest OS makes use of them */ 205 memory_region_set_enabled(&xive->end_source.esb_mmio, false); 206 } 207 208 /* 209 * When a Virtual Processor is scheduled to run on a HW thread, the 210 * hypervisor pushes its identifier in the OS CAM line. Emulate the 211 * same behavior under QEMU. 212 */ 213 void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) 214 { 215 uint8_t nvt_blk; 216 uint32_t nvt_idx; 217 uint32_t nvt_cam; 218 219 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); 220 221 nvt_cam = cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt_idx)); 222 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); 223 } 224 225 static void spapr_xive_end_reset(XiveEND *end) 226 { 227 memset(end, 0, sizeof(*end)); 228 229 /* switch off the escalation and notification ESBs */ 230 end->w1 = cpu_to_be32(END_W1_ESe_Q | END_W1_ESn_Q); 231 } 232 233 static void spapr_xive_reset(void *dev) 234 { 235 SpaprXive *xive = SPAPR_XIVE(dev); 236 int i; 237 238 /* 239 * The XiveSource has its own reset handler, which mask off all 240 * IRQs (!P|Q) 241 */ 242 243 /* Mask all valid EASs in the IRQ number space. */ 244 for (i = 0; i < xive->nr_irqs; i++) { 245 XiveEAS *eas = &xive->eat[i]; 246 if (xive_eas_is_valid(eas)) { 247 eas->w = cpu_to_be64(EAS_VALID | EAS_MASKED); 248 } else { 249 eas->w = 0; 250 } 251 } 252 253 /* Clear all ENDs */ 254 for (i = 0; i < xive->nr_ends; i++) { 255 spapr_xive_end_reset(&xive->endt[i]); 256 } 257 } 258 259 static void spapr_xive_instance_init(Object *obj) 260 { 261 SpaprXive *xive = SPAPR_XIVE(obj); 262 263 object_initialize_child(obj, "source", &xive->source, sizeof(xive->source), 264 TYPE_XIVE_SOURCE, &error_abort, NULL); 265 266 object_initialize_child(obj, "end_source", &xive->end_source, 267 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 268 &error_abort, NULL); 269 270 /* Not connected to the KVM XIVE device */ 271 xive->fd = -1; 272 } 273 274 static void spapr_xive_realize(DeviceState *dev, Error **errp) 275 { 276 SpaprXive *xive = SPAPR_XIVE(dev); 277 XiveSource *xsrc = &xive->source; 278 XiveENDSource *end_xsrc = &xive->end_source; 279 Error *local_err = NULL; 280 281 if (!xive->nr_irqs) { 282 error_setg(errp, "Number of interrupt needs to be greater 0"); 283 return; 284 } 285 286 if (!xive->nr_ends) { 287 error_setg(errp, "Number of interrupt needs to be greater 0"); 288 return; 289 } 290 291 /* 292 * Initialize the internal sources, for IPIs and virtual devices. 293 */ 294 object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 295 &error_fatal); 296 object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), 297 &error_fatal); 298 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 299 if (local_err) { 300 error_propagate(errp, local_err); 301 return; 302 } 303 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio); 304 305 /* 306 * Initialize the END ESB source 307 */ 308 object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 309 &error_fatal); 310 object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 311 &error_fatal); 312 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 313 if (local_err) { 314 error_propagate(errp, local_err); 315 return; 316 } 317 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio); 318 319 /* Set the mapping address of the END ESB pages after the source ESBs */ 320 xive->end_base = xive->vc_base + (1ull << xsrc->esb_shift) * xsrc->nr_irqs; 321 322 /* 323 * Allocate the routing tables 324 */ 325 xive->eat = g_new0(XiveEAS, xive->nr_irqs); 326 xive->endt = g_new0(XiveEND, xive->nr_ends); 327 328 xive->nodename = g_strdup_printf("interrupt-controller@%" PRIx64, 329 xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SHIFT)); 330 331 qemu_register_reset(spapr_xive_reset, dev); 332 333 /* TIMA initialization */ 334 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, 335 "xive.tima", 4ull << TM_SHIFT); 336 sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); 337 338 /* 339 * Map all regions. These will be enabled or disabled at reset and 340 * can also be overridden by KVM memory regions if active 341 */ 342 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base); 343 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base); 344 sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); 345 } 346 347 static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk, 348 uint32_t eas_idx, XiveEAS *eas) 349 { 350 SpaprXive *xive = SPAPR_XIVE(xrtr); 351 352 if (eas_idx >= xive->nr_irqs) { 353 return -1; 354 } 355 356 *eas = xive->eat[eas_idx]; 357 return 0; 358 } 359 360 static int spapr_xive_get_end(XiveRouter *xrtr, 361 uint8_t end_blk, uint32_t end_idx, XiveEND *end) 362 { 363 SpaprXive *xive = SPAPR_XIVE(xrtr); 364 365 if (end_idx >= xive->nr_ends) { 366 return -1; 367 } 368 369 memcpy(end, &xive->endt[end_idx], sizeof(XiveEND)); 370 return 0; 371 } 372 373 static int spapr_xive_write_end(XiveRouter *xrtr, uint8_t end_blk, 374 uint32_t end_idx, XiveEND *end, 375 uint8_t word_number) 376 { 377 SpaprXive *xive = SPAPR_XIVE(xrtr); 378 379 if (end_idx >= xive->nr_ends) { 380 return -1; 381 } 382 383 memcpy(&xive->endt[end_idx], end, sizeof(XiveEND)); 384 return 0; 385 } 386 387 static int spapr_xive_get_nvt(XiveRouter *xrtr, 388 uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt) 389 { 390 uint32_t vcpu_id = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 391 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 392 393 if (!cpu) { 394 /* TODO: should we assert() if we can find a NVT ? */ 395 return -1; 396 } 397 398 /* 399 * sPAPR does not maintain a NVT table. Return that the NVT is 400 * valid if we have found a matching CPU 401 */ 402 nvt->w0 = cpu_to_be32(NVT_W0_VALID); 403 return 0; 404 } 405 406 static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, 407 uint32_t nvt_idx, XiveNVT *nvt, 408 uint8_t word_number) 409 { 410 /* 411 * We don't need to write back to the NVTs because the sPAPR 412 * machine should never hit a non-scheduled NVT. It should never 413 * get called. 414 */ 415 g_assert_not_reached(); 416 } 417 418 static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 419 { 420 PowerPCCPU *cpu = POWERPC_CPU(cs); 421 422 return spapr_cpu_state(cpu)->tctx; 423 } 424 425 static const VMStateDescription vmstate_spapr_xive_end = { 426 .name = TYPE_SPAPR_XIVE "/end", 427 .version_id = 1, 428 .minimum_version_id = 1, 429 .fields = (VMStateField []) { 430 VMSTATE_UINT32(w0, XiveEND), 431 VMSTATE_UINT32(w1, XiveEND), 432 VMSTATE_UINT32(w2, XiveEND), 433 VMSTATE_UINT32(w3, XiveEND), 434 VMSTATE_UINT32(w4, XiveEND), 435 VMSTATE_UINT32(w5, XiveEND), 436 VMSTATE_UINT32(w6, XiveEND), 437 VMSTATE_UINT32(w7, XiveEND), 438 VMSTATE_END_OF_LIST() 439 }, 440 }; 441 442 static const VMStateDescription vmstate_spapr_xive_eas = { 443 .name = TYPE_SPAPR_XIVE "/eas", 444 .version_id = 1, 445 .minimum_version_id = 1, 446 .fields = (VMStateField []) { 447 VMSTATE_UINT64(w, XiveEAS), 448 VMSTATE_END_OF_LIST() 449 }, 450 }; 451 452 static int vmstate_spapr_xive_pre_save(void *opaque) 453 { 454 if (kvm_irqchip_in_kernel()) { 455 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque)); 456 } 457 458 return 0; 459 } 460 461 /* 462 * Called by the sPAPR IRQ backend 'post_load' method at the machine 463 * level. 464 */ 465 int spapr_xive_post_load(SpaprXive *xive, int version_id) 466 { 467 if (kvm_irqchip_in_kernel()) { 468 return kvmppc_xive_post_load(xive, version_id); 469 } 470 471 return 0; 472 } 473 474 static const VMStateDescription vmstate_spapr_xive = { 475 .name = TYPE_SPAPR_XIVE, 476 .version_id = 1, 477 .minimum_version_id = 1, 478 .pre_save = vmstate_spapr_xive_pre_save, 479 .post_load = NULL, /* handled at the machine level */ 480 .fields = (VMStateField[]) { 481 VMSTATE_UINT32_EQUAL(nr_irqs, SpaprXive, NULL), 482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat, SpaprXive, nr_irqs, 483 vmstate_spapr_xive_eas, XiveEAS), 484 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt, SpaprXive, nr_ends, 485 vmstate_spapr_xive_end, XiveEND), 486 VMSTATE_END_OF_LIST() 487 }, 488 }; 489 490 static int spapr_xive_claim_irq(SpaprInterruptController *intc, int lisn, 491 bool lsi, Error **errp) 492 { 493 SpaprXive *xive = SPAPR_XIVE(intc); 494 XiveSource *xsrc = &xive->source; 495 496 assert(lisn < xive->nr_irqs); 497 498 if (xive_eas_is_valid(&xive->eat[lisn])) { 499 error_setg(errp, "IRQ %d is not free", lisn); 500 return -EBUSY; 501 } 502 503 /* 504 * Set default values when allocating an IRQ number 505 */ 506 xive->eat[lisn].w |= cpu_to_be64(EAS_VALID | EAS_MASKED); 507 if (lsi) { 508 xive_source_irq_set_lsi(xsrc, lisn); 509 } 510 511 if (kvm_irqchip_in_kernel()) { 512 return kvmppc_xive_source_reset_one(xsrc, lisn, errp); 513 } 514 515 return 0; 516 } 517 518 static void spapr_xive_free_irq(SpaprInterruptController *intc, int lisn) 519 { 520 SpaprXive *xive = SPAPR_XIVE(intc); 521 assert(lisn < xive->nr_irqs); 522 523 xive->eat[lisn].w &= cpu_to_be64(~EAS_VALID); 524 } 525 526 static Property spapr_xive_properties[] = { 527 DEFINE_PROP_UINT32("nr-irqs", SpaprXive, nr_irqs, 0), 528 DEFINE_PROP_UINT32("nr-ends", SpaprXive, nr_ends, 0), 529 DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), 530 DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), 531 DEFINE_PROP_END_OF_LIST(), 532 }; 533 534 static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, 535 PowerPCCPU *cpu, Error **errp) 536 { 537 SpaprXive *xive = SPAPR_XIVE(intc); 538 Object *obj; 539 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 540 541 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); 542 if (!obj) { 543 return -1; 544 } 545 546 spapr_cpu->tctx = XIVE_TCTX(obj); 547 548 /* 549 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they 550 * don't beneficiate from the reset of the XIVE IRQ backend 551 */ 552 spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); 553 return 0; 554 } 555 556 static void spapr_xive_set_irq(SpaprInterruptController *intc, int irq, int val) 557 { 558 SpaprXive *xive = SPAPR_XIVE(intc); 559 560 if (kvm_irqchip_in_kernel()) { 561 kvmppc_xive_source_set_irq(&xive->source, irq, val); 562 } else { 563 xive_source_set_irq(&xive->source, irq, val); 564 } 565 } 566 567 static void spapr_xive_print_info(SpaprInterruptController *intc, Monitor *mon) 568 { 569 SpaprXive *xive = SPAPR_XIVE(intc); 570 CPUState *cs; 571 572 CPU_FOREACH(cs) { 573 PowerPCCPU *cpu = POWERPC_CPU(cs); 574 575 xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon); 576 } 577 578 spapr_xive_pic_print_info(xive, mon); 579 } 580 581 static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, 582 void *fdt, uint32_t phandle) 583 { 584 SpaprXive *xive = SPAPR_XIVE(intc); 585 int node; 586 uint64_t timas[2 * 2]; 587 /* Interrupt number ranges for the IPIs */ 588 uint32_t lisn_ranges[] = { 589 cpu_to_be32(0), 590 cpu_to_be32(nr_servers), 591 }; 592 /* 593 * EQ size - the sizes of pages supported by the system 4K, 64K, 594 * 2M, 16M. We only advertise 64K for the moment. 595 */ 596 uint32_t eq_sizes[] = { 597 cpu_to_be32(16), /* 64K */ 598 }; 599 /* 600 * The following array is in sync with the reserved priorities 601 * defined by the 'spapr_xive_priority_is_reserved' routine. 602 */ 603 uint32_t plat_res_int_priorities[] = { 604 cpu_to_be32(7), /* start */ 605 cpu_to_be32(0xf8), /* count */ 606 }; 607 608 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ 609 timas[0] = cpu_to_be64(xive->tm_base + 610 XIVE_TM_USER_PAGE * (1ull << TM_SHIFT)); 611 timas[1] = cpu_to_be64(1ull << TM_SHIFT); 612 timas[2] = cpu_to_be64(xive->tm_base + 613 XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); 614 timas[3] = cpu_to_be64(1ull << TM_SHIFT); 615 616 _FDT(node = fdt_add_subnode(fdt, 0, xive->nodename)); 617 618 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); 619 _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); 620 621 _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe")); 622 _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes, 623 sizeof(eq_sizes))); 624 _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges, 625 sizeof(lisn_ranges))); 626 627 /* For Linux to link the LSIs to the interrupt controller. */ 628 _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0)); 629 _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2)); 630 631 /* For SLOF */ 632 _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle)); 633 _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle)); 634 635 /* 636 * The "ibm,plat-res-int-priorities" property defines the priority 637 * ranges reserved by the hypervisor 638 */ 639 _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities", 640 plat_res_int_priorities, sizeof(plat_res_int_priorities))); 641 } 642 643 static void spapr_xive_class_init(ObjectClass *klass, void *data) 644 { 645 DeviceClass *dc = DEVICE_CLASS(klass); 646 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 647 SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); 648 649 dc->desc = "sPAPR XIVE Interrupt Controller"; 650 dc->props = spapr_xive_properties; 651 dc->realize = spapr_xive_realize; 652 dc->vmsd = &vmstate_spapr_xive; 653 654 xrc->get_eas = spapr_xive_get_eas; 655 xrc->get_end = spapr_xive_get_end; 656 xrc->write_end = spapr_xive_write_end; 657 xrc->get_nvt = spapr_xive_get_nvt; 658 xrc->write_nvt = spapr_xive_write_nvt; 659 xrc->get_tctx = spapr_xive_get_tctx; 660 661 sicc->cpu_intc_create = spapr_xive_cpu_intc_create; 662 sicc->claim_irq = spapr_xive_claim_irq; 663 sicc->free_irq = spapr_xive_free_irq; 664 sicc->set_irq = spapr_xive_set_irq; 665 sicc->print_info = spapr_xive_print_info; 666 sicc->dt = spapr_xive_dt; 667 } 668 669 static const TypeInfo spapr_xive_info = { 670 .name = TYPE_SPAPR_XIVE, 671 .parent = TYPE_XIVE_ROUTER, 672 .instance_init = spapr_xive_instance_init, 673 .instance_size = sizeof(SpaprXive), 674 .class_init = spapr_xive_class_init, 675 .interfaces = (InterfaceInfo[]) { 676 { TYPE_SPAPR_INTC }, 677 { } 678 }, 679 }; 680 681 static void spapr_xive_register_types(void) 682 { 683 type_register_static(&spapr_xive_info); 684 } 685 686 type_init(spapr_xive_register_types) 687 688 /* 689 * XIVE hcalls 690 * 691 * The terminology used by the XIVE hcalls is the following : 692 * 693 * TARGET vCPU number 694 * EQ Event Queue assigned by OS to receive event data 695 * ESB page for source interrupt management 696 * LISN Logical Interrupt Source Number identifying a source in the 697 * machine 698 * EISN Effective Interrupt Source Number used by guest OS to 699 * identify source in the guest 700 * 701 * The EAS, END, NVT structures are not exposed. 702 */ 703 704 /* 705 * Linux hosts under OPAL reserve priority 7 for their own escalation 706 * interrupts (DD2.X POWER9). So we only allow the guest to use 707 * priorities [0..6]. 708 */ 709 static bool spapr_xive_priority_is_reserved(uint8_t priority) 710 { 711 switch (priority) { 712 case 0 ... 6: 713 return false; 714 case 7: /* OPAL escalation queue */ 715 default: 716 return true; 717 } 718 } 719 720 /* 721 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical 722 * real address of the MMIO page through which the Event State Buffer 723 * entry associated with the value of the "lisn" parameter is managed. 724 * 725 * Parameters: 726 * Input 727 * - R4: "flags" 728 * Bits 0-63 reserved 729 * - R5: "lisn" is per "interrupts", "interrupt-map", or 730 * "ibm,xive-lisn-ranges" properties, or as returned by the 731 * ibm,query-interrupt-source-number RTAS call, or as returned 732 * by the H_ALLOCATE_VAS_WINDOW hcall 733 * 734 * Output 735 * - R4: "flags" 736 * Bits 0-59: Reserved 737 * Bit 60: H_INT_ESB must be used for Event State Buffer 738 * management 739 * Bit 61: 1 == LSI 0 == MSI 740 * Bit 62: the full function page supports trigger 741 * Bit 63: Store EOI Supported 742 * - R5: Logical Real address of full function Event State Buffer 743 * management page, -1 if H_INT_ESB hcall flag is set to 1. 744 * - R6: Logical Real Address of trigger only Event State Buffer 745 * management page or -1. 746 * - R7: Power of 2 page size for the ESB management pages returned in 747 * R5 and R6. 748 */ 749 750 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */ 751 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */ 752 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management 753 on same page */ 754 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */ 755 756 static target_ulong h_int_get_source_info(PowerPCCPU *cpu, 757 SpaprMachineState *spapr, 758 target_ulong opcode, 759 target_ulong *args) 760 { 761 SpaprXive *xive = spapr->xive; 762 XiveSource *xsrc = &xive->source; 763 target_ulong flags = args[0]; 764 target_ulong lisn = args[1]; 765 766 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 767 return H_FUNCTION; 768 } 769 770 if (flags) { 771 return H_PARAMETER; 772 } 773 774 if (lisn >= xive->nr_irqs) { 775 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 776 lisn); 777 return H_P2; 778 } 779 780 if (!xive_eas_is_valid(&xive->eat[lisn])) { 781 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 782 lisn); 783 return H_P2; 784 } 785 786 /* 787 * All sources are emulated under the main XIVE object and share 788 * the same characteristics. 789 */ 790 args[0] = 0; 791 if (!xive_source_esb_has_2page(xsrc)) { 792 args[0] |= SPAPR_XIVE_SRC_TRIGGER; 793 } 794 if (xsrc->esb_flags & XIVE_SRC_STORE_EOI) { 795 args[0] |= SPAPR_XIVE_SRC_STORE_EOI; 796 } 797 798 /* 799 * Force the use of the H_INT_ESB hcall in case of an LSI 800 * interrupt. This is necessary under KVM to re-trigger the 801 * interrupt if the level is still asserted 802 */ 803 if (xive_source_irq_is_lsi(xsrc, lisn)) { 804 args[0] |= SPAPR_XIVE_SRC_H_INT_ESB | SPAPR_XIVE_SRC_LSI; 805 } 806 807 if (!(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 808 args[1] = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn); 809 } else { 810 args[1] = -1; 811 } 812 813 if (xive_source_esb_has_2page(xsrc) && 814 !(args[0] & SPAPR_XIVE_SRC_H_INT_ESB)) { 815 args[2] = xive->vc_base + xive_source_esb_page(xsrc, lisn); 816 } else { 817 args[2] = -1; 818 } 819 820 if (xive_source_esb_has_2page(xsrc)) { 821 args[3] = xsrc->esb_shift - 1; 822 } else { 823 args[3] = xsrc->esb_shift; 824 } 825 826 return H_SUCCESS; 827 } 828 829 /* 830 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical 831 * Interrupt Source to a target. The Logical Interrupt Source is 832 * designated with the "lisn" parameter and the target is designated 833 * with the "target" and "priority" parameters. Upon return from the 834 * hcall(), no additional interrupts will be directed to the old EQ. 835 * 836 * Parameters: 837 * Input: 838 * - R4: "flags" 839 * Bits 0-61: Reserved 840 * Bit 62: set the "eisn" in the EAS 841 * Bit 63: masks the interrupt source in the hardware interrupt 842 * control structure. An interrupt masked by this mechanism will 843 * be dropped, but it's source state bits will still be 844 * set. There is no race-free way of unmasking and restoring the 845 * source. Thus this should only be used in interrupts that are 846 * also masked at the source, and only in cases where the 847 * interrupt is not meant to be used for a large amount of time 848 * because no valid target exists for it for example 849 * - R5: "lisn" is per "interrupts", "interrupt-map", or 850 * "ibm,xive-lisn-ranges" properties, or as returned by the 851 * ibm,query-interrupt-source-number RTAS call, or as returned by 852 * the H_ALLOCATE_VAS_WINDOW hcall 853 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or 854 * "ibm,ppc-interrupt-gserver#s" 855 * - R7: "priority" is a valid priority not in 856 * "ibm,plat-res-int-priorities" 857 * - R8: "eisn" is the guest EISN associated with the "lisn" 858 * 859 * Output: 860 * - None 861 */ 862 863 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62) 864 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63) 865 866 static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 867 SpaprMachineState *spapr, 868 target_ulong opcode, 869 target_ulong *args) 870 { 871 SpaprXive *xive = spapr->xive; 872 XiveEAS eas, new_eas; 873 target_ulong flags = args[0]; 874 target_ulong lisn = args[1]; 875 target_ulong target = args[2]; 876 target_ulong priority = args[3]; 877 target_ulong eisn = args[4]; 878 uint8_t end_blk; 879 uint32_t end_idx; 880 881 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 882 return H_FUNCTION; 883 } 884 885 if (flags & ~(SPAPR_XIVE_SRC_SET_EISN | SPAPR_XIVE_SRC_MASK)) { 886 return H_PARAMETER; 887 } 888 889 if (lisn >= xive->nr_irqs) { 890 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 891 lisn); 892 return H_P2; 893 } 894 895 eas = xive->eat[lisn]; 896 if (!xive_eas_is_valid(&eas)) { 897 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 898 lisn); 899 return H_P2; 900 } 901 902 /* priority 0xff is used to reset the EAS */ 903 if (priority == 0xff) { 904 new_eas.w = cpu_to_be64(EAS_VALID | EAS_MASKED); 905 goto out; 906 } 907 908 if (flags & SPAPR_XIVE_SRC_MASK) { 909 new_eas.w = eas.w | cpu_to_be64(EAS_MASKED); 910 } else { 911 new_eas.w = eas.w & cpu_to_be64(~EAS_MASKED); 912 } 913 914 if (spapr_xive_priority_is_reserved(priority)) { 915 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 916 " is reserved\n", priority); 917 return H_P4; 918 } 919 920 /* 921 * Validate that "target" is part of the list of threads allocated 922 * to the partition. For that, find the END corresponding to the 923 * target. 924 */ 925 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 926 return H_P3; 927 } 928 929 new_eas.w = xive_set_field64(EAS_END_BLOCK, new_eas.w, end_blk); 930 new_eas.w = xive_set_field64(EAS_END_INDEX, new_eas.w, end_idx); 931 932 if (flags & SPAPR_XIVE_SRC_SET_EISN) { 933 new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn); 934 } 935 936 if (kvm_irqchip_in_kernel()) { 937 Error *local_err = NULL; 938 939 kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err); 940 if (local_err) { 941 error_report_err(local_err); 942 return H_HARDWARE; 943 } 944 } 945 946 out: 947 xive->eat[lisn] = new_eas; 948 return H_SUCCESS; 949 } 950 951 /* 952 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which 953 * target/priority pair is assigned to the specified Logical Interrupt 954 * Source. 955 * 956 * Parameters: 957 * Input: 958 * - R4: "flags" 959 * Bits 0-63 Reserved 960 * - R5: "lisn" is per "interrupts", "interrupt-map", or 961 * "ibm,xive-lisn-ranges" properties, or as returned by the 962 * ibm,query-interrupt-source-number RTAS call, or as 963 * returned by the H_ALLOCATE_VAS_WINDOW hcall 964 * 965 * Output: 966 * - R4: Target to which the specified Logical Interrupt Source is 967 * assigned 968 * - R5: Priority to which the specified Logical Interrupt Source is 969 * assigned 970 * - R6: EISN for the specified Logical Interrupt Source (this will be 971 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG) 972 */ 973 static target_ulong h_int_get_source_config(PowerPCCPU *cpu, 974 SpaprMachineState *spapr, 975 target_ulong opcode, 976 target_ulong *args) 977 { 978 SpaprXive *xive = spapr->xive; 979 target_ulong flags = args[0]; 980 target_ulong lisn = args[1]; 981 XiveEAS eas; 982 XiveEND *end; 983 uint8_t nvt_blk; 984 uint32_t end_idx, nvt_idx; 985 986 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 987 return H_FUNCTION; 988 } 989 990 if (flags) { 991 return H_PARAMETER; 992 } 993 994 if (lisn >= xive->nr_irqs) { 995 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 996 lisn); 997 return H_P2; 998 } 999 1000 eas = xive->eat[lisn]; 1001 if (!xive_eas_is_valid(&eas)) { 1002 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1003 lisn); 1004 return H_P2; 1005 } 1006 1007 /* EAS_END_BLOCK is unused on sPAPR */ 1008 end_idx = xive_get_field64(EAS_END_INDEX, eas.w); 1009 1010 assert(end_idx < xive->nr_ends); 1011 end = &xive->endt[end_idx]; 1012 1013 nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6); 1014 nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6); 1015 args[0] = spapr_xive_nvt_to_target(nvt_blk, nvt_idx); 1016 1017 if (xive_eas_is_masked(&eas)) { 1018 args[1] = 0xff; 1019 } else { 1020 args[1] = xive_get_field32(END_W7_F0_PRIORITY, end->w7); 1021 } 1022 1023 args[2] = xive_get_field64(EAS_END_DATA, eas.w); 1024 1025 return H_SUCCESS; 1026 } 1027 1028 /* 1029 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real 1030 * address of the notification management page associated with the 1031 * specified target and priority. 1032 * 1033 * Parameters: 1034 * Input: 1035 * - R4: "flags" 1036 * Bits 0-63 Reserved 1037 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1038 * "ibm,ppc-interrupt-gserver#s" 1039 * - R6: "priority" is a valid priority not in 1040 * "ibm,plat-res-int-priorities" 1041 * 1042 * Output: 1043 * - R4: Logical real address of notification page 1044 * - R5: Power of 2 page size of the notification page 1045 */ 1046 static target_ulong h_int_get_queue_info(PowerPCCPU *cpu, 1047 SpaprMachineState *spapr, 1048 target_ulong opcode, 1049 target_ulong *args) 1050 { 1051 SpaprXive *xive = spapr->xive; 1052 XiveENDSource *end_xsrc = &xive->end_source; 1053 target_ulong flags = args[0]; 1054 target_ulong target = args[1]; 1055 target_ulong priority = args[2]; 1056 XiveEND *end; 1057 uint8_t end_blk; 1058 uint32_t end_idx; 1059 1060 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1061 return H_FUNCTION; 1062 } 1063 1064 if (flags) { 1065 return H_PARAMETER; 1066 } 1067 1068 /* 1069 * H_STATE should be returned if a H_INT_RESET is in progress. 1070 * This is not needed when running the emulation under QEMU 1071 */ 1072 1073 if (spapr_xive_priority_is_reserved(priority)) { 1074 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1075 " is reserved\n", priority); 1076 return H_P3; 1077 } 1078 1079 /* 1080 * Validate that "target" is part of the list of threads allocated 1081 * to the partition. For that, find the END corresponding to the 1082 * target. 1083 */ 1084 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1085 return H_P2; 1086 } 1087 1088 assert(end_idx < xive->nr_ends); 1089 end = &xive->endt[end_idx]; 1090 1091 args[0] = xive->end_base + (1ull << (end_xsrc->esb_shift + 1)) * end_idx; 1092 if (xive_end_is_enqueue(end)) { 1093 args[1] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1094 } else { 1095 args[1] = 0; 1096 } 1097 1098 return H_SUCCESS; 1099 } 1100 1101 /* 1102 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for 1103 * a given "target" and "priority". It is also used to set the 1104 * notification config associated with the EQ. An EQ size of 0 is 1105 * used to reset the EQ config for a given target and priority. If 1106 * resetting the EQ config, the END associated with the given "target" 1107 * and "priority" will be changed to disable queueing. 1108 * 1109 * Upon return from the hcall(), no additional interrupts will be 1110 * directed to the old EQ (if one was set). The old EQ (if one was 1111 * set) should be investigated for interrupts that occurred prior to 1112 * or during the hcall(). 1113 * 1114 * Parameters: 1115 * Input: 1116 * - R4: "flags" 1117 * Bits 0-62: Reserved 1118 * Bit 63: Unconditional Notify (n) per the XIVE spec 1119 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1120 * "ibm,ppc-interrupt-gserver#s" 1121 * - R6: "priority" is a valid priority not in 1122 * "ibm,plat-res-int-priorities" 1123 * - R7: "eventQueue": The logical real address of the start of the EQ 1124 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes" 1125 * 1126 * Output: 1127 * - None 1128 */ 1129 1130 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63) 1131 1132 static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 1133 SpaprMachineState *spapr, 1134 target_ulong opcode, 1135 target_ulong *args) 1136 { 1137 SpaprXive *xive = spapr->xive; 1138 target_ulong flags = args[0]; 1139 target_ulong target = args[1]; 1140 target_ulong priority = args[2]; 1141 target_ulong qpage = args[3]; 1142 target_ulong qsize = args[4]; 1143 XiveEND end; 1144 uint8_t end_blk, nvt_blk; 1145 uint32_t end_idx, nvt_idx; 1146 1147 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1148 return H_FUNCTION; 1149 } 1150 1151 if (flags & ~SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1152 return H_PARAMETER; 1153 } 1154 1155 /* 1156 * H_STATE should be returned if a H_INT_RESET is in progress. 1157 * This is not needed when running the emulation under QEMU 1158 */ 1159 1160 if (spapr_xive_priority_is_reserved(priority)) { 1161 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1162 " is reserved\n", priority); 1163 return H_P3; 1164 } 1165 1166 /* 1167 * Validate that "target" is part of the list of threads allocated 1168 * to the partition. For that, find the END corresponding to the 1169 * target. 1170 */ 1171 1172 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1173 return H_P2; 1174 } 1175 1176 assert(end_idx < xive->nr_ends); 1177 memcpy(&end, &xive->endt[end_idx], sizeof(XiveEND)); 1178 1179 switch (qsize) { 1180 case 12: 1181 case 16: 1182 case 21: 1183 case 24: 1184 if (!QEMU_IS_ALIGNED(qpage, 1ul << qsize)) { 1185 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: EQ @0x%" HWADDR_PRIx 1186 " is not naturally aligned with %" HWADDR_PRIx "\n", 1187 qpage, (hwaddr)1 << qsize); 1188 return H_P4; 1189 } 1190 end.w2 = cpu_to_be32((qpage >> 32) & 0x0fffffff); 1191 end.w3 = cpu_to_be32(qpage & 0xffffffff); 1192 end.w0 |= cpu_to_be32(END_W0_ENQUEUE); 1193 end.w0 = xive_set_field32(END_W0_QSIZE, end.w0, qsize - 12); 1194 break; 1195 case 0: 1196 /* reset queue and disable queueing */ 1197 spapr_xive_end_reset(&end); 1198 goto out; 1199 1200 default: 1201 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EQ size %"PRIx64"\n", 1202 qsize); 1203 return H_P5; 1204 } 1205 1206 if (qsize) { 1207 hwaddr plen = 1 << qsize; 1208 void *eq; 1209 1210 /* 1211 * Validate the guest EQ. We should also check that the queue 1212 * has been zeroed by the OS. 1213 */ 1214 eq = address_space_map(CPU(cpu)->as, qpage, &plen, true, 1215 MEMTXATTRS_UNSPECIFIED); 1216 if (plen != 1 << qsize) { 1217 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to map EQ @0x%" 1218 HWADDR_PRIx "\n", qpage); 1219 return H_P4; 1220 } 1221 address_space_unmap(CPU(cpu)->as, eq, plen, true, plen); 1222 } 1223 1224 /* "target" should have been validated above */ 1225 if (spapr_xive_target_to_nvt(target, &nvt_blk, &nvt_idx)) { 1226 g_assert_not_reached(); 1227 } 1228 1229 /* 1230 * Ensure the priority and target are correctly set (they will not 1231 * be right after allocation) 1232 */ 1233 end.w6 = xive_set_field32(END_W6_NVT_BLOCK, 0ul, nvt_blk) | 1234 xive_set_field32(END_W6_NVT_INDEX, 0ul, nvt_idx); 1235 end.w7 = xive_set_field32(END_W7_F0_PRIORITY, 0ul, priority); 1236 1237 if (flags & SPAPR_XIVE_END_ALWAYS_NOTIFY) { 1238 end.w0 |= cpu_to_be32(END_W0_UCOND_NOTIFY); 1239 } else { 1240 end.w0 &= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY); 1241 } 1242 1243 /* 1244 * The generation bit for the END starts at 1 and The END page 1245 * offset counter starts at 0. 1246 */ 1247 end.w1 = cpu_to_be32(END_W1_GENERATION) | 1248 xive_set_field32(END_W1_PAGE_OFF, 0ul, 0ul); 1249 end.w0 |= cpu_to_be32(END_W0_VALID); 1250 1251 /* 1252 * TODO: issue syncs required to ensure all in-flight interrupts 1253 * are complete on the old END 1254 */ 1255 1256 out: 1257 if (kvm_irqchip_in_kernel()) { 1258 Error *local_err = NULL; 1259 1260 kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err); 1261 if (local_err) { 1262 error_report_err(local_err); 1263 return H_HARDWARE; 1264 } 1265 } 1266 1267 /* Update END */ 1268 memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND)); 1269 return H_SUCCESS; 1270 } 1271 1272 /* 1273 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given 1274 * target and priority. 1275 * 1276 * Parameters: 1277 * Input: 1278 * - R4: "flags" 1279 * Bits 0-62: Reserved 1280 * Bit 63: Debug: Return debug data 1281 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1282 * "ibm,ppc-interrupt-gserver#s" 1283 * - R6: "priority" is a valid priority not in 1284 * "ibm,plat-res-int-priorities" 1285 * 1286 * Output: 1287 * - R4: "flags": 1288 * Bits 0-61: Reserved 1289 * Bit 62: The value of Event Queue Generation Number (g) per 1290 * the XIVE spec if "Debug" = 1 1291 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec 1292 * - R5: The logical real address of the start of the EQ 1293 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes" 1294 * - R7: The value of Event Queue Offset Counter per XIVE spec 1295 * if "Debug" = 1, else 0 1296 * 1297 */ 1298 1299 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63) 1300 1301 static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 1302 SpaprMachineState *spapr, 1303 target_ulong opcode, 1304 target_ulong *args) 1305 { 1306 SpaprXive *xive = spapr->xive; 1307 target_ulong flags = args[0]; 1308 target_ulong target = args[1]; 1309 target_ulong priority = args[2]; 1310 XiveEND *end; 1311 uint8_t end_blk; 1312 uint32_t end_idx; 1313 1314 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1315 return H_FUNCTION; 1316 } 1317 1318 if (flags & ~SPAPR_XIVE_END_DEBUG) { 1319 return H_PARAMETER; 1320 } 1321 1322 /* 1323 * H_STATE should be returned if a H_INT_RESET is in progress. 1324 * This is not needed when running the emulation under QEMU 1325 */ 1326 1327 if (spapr_xive_priority_is_reserved(priority)) { 1328 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: priority " TARGET_FMT_ld 1329 " is reserved\n", priority); 1330 return H_P3; 1331 } 1332 1333 /* 1334 * Validate that "target" is part of the list of threads allocated 1335 * to the partition. For that, find the END corresponding to the 1336 * target. 1337 */ 1338 if (spapr_xive_target_to_end(target, priority, &end_blk, &end_idx)) { 1339 return H_P2; 1340 } 1341 1342 assert(end_idx < xive->nr_ends); 1343 end = &xive->endt[end_idx]; 1344 1345 args[0] = 0; 1346 if (xive_end_is_notify(end)) { 1347 args[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY; 1348 } 1349 1350 if (xive_end_is_enqueue(end)) { 1351 args[1] = xive_end_qaddr(end); 1352 args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12; 1353 } else { 1354 args[1] = 0; 1355 args[2] = 0; 1356 } 1357 1358 if (kvm_irqchip_in_kernel()) { 1359 Error *local_err = NULL; 1360 1361 kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err); 1362 if (local_err) { 1363 error_report_err(local_err); 1364 return H_HARDWARE; 1365 } 1366 } 1367 1368 /* TODO: do we need any locking on the END ? */ 1369 if (flags & SPAPR_XIVE_END_DEBUG) { 1370 /* Load the event queue generation number into the return flags */ 1371 args[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION, end->w1) << 62; 1372 1373 /* Load R7 with the event queue offset counter */ 1374 args[3] = xive_get_field32(END_W1_PAGE_OFF, end->w1); 1375 } else { 1376 args[3] = 0; 1377 } 1378 1379 return H_SUCCESS; 1380 } 1381 1382 /* 1383 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the 1384 * reporting cache line pair for the calling thread. The reporting 1385 * cache lines will contain the OS interrupt context when the OS 1386 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS 1387 * interrupt. The reporting cache lines can be reset by inputting -1 1388 * in "reportingLine". Issuing the CI store byte without reporting 1389 * cache lines registered will result in the data not being accessible 1390 * to the OS. 1391 * 1392 * Parameters: 1393 * Input: 1394 * - R4: "flags" 1395 * Bits 0-63: Reserved 1396 * - R5: "reportingLine": The logical real address of the reporting cache 1397 * line pair 1398 * 1399 * Output: 1400 * - None 1401 */ 1402 static target_ulong h_int_set_os_reporting_line(PowerPCCPU *cpu, 1403 SpaprMachineState *spapr, 1404 target_ulong opcode, 1405 target_ulong *args) 1406 { 1407 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1408 return H_FUNCTION; 1409 } 1410 1411 /* 1412 * H_STATE should be returned if a H_INT_RESET is in progress. 1413 * This is not needed when running the emulation under QEMU 1414 */ 1415 1416 /* TODO: H_INT_SET_OS_REPORTING_LINE */ 1417 return H_FUNCTION; 1418 } 1419 1420 /* 1421 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical 1422 * real address of the reporting cache line pair set for the input 1423 * "target". If no reporting cache line pair has been set, -1 is 1424 * returned. 1425 * 1426 * Parameters: 1427 * Input: 1428 * - R4: "flags" 1429 * Bits 0-63: Reserved 1430 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or 1431 * "ibm,ppc-interrupt-gserver#s" 1432 * - R6: "reportingLine": The logical real address of the reporting 1433 * cache line pair 1434 * 1435 * Output: 1436 * - R4: The logical real address of the reporting line if set, else -1 1437 */ 1438 static target_ulong h_int_get_os_reporting_line(PowerPCCPU *cpu, 1439 SpaprMachineState *spapr, 1440 target_ulong opcode, 1441 target_ulong *args) 1442 { 1443 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1444 return H_FUNCTION; 1445 } 1446 1447 /* 1448 * H_STATE should be returned if a H_INT_RESET is in progress. 1449 * This is not needed when running the emulation under QEMU 1450 */ 1451 1452 /* TODO: H_INT_GET_OS_REPORTING_LINE */ 1453 return H_FUNCTION; 1454 } 1455 1456 /* 1457 * The H_INT_ESB hcall() is used to issue a load or store to the ESB 1458 * page for the input "lisn". This hcall is only supported for LISNs 1459 * that have the ESB hcall flag set to 1 when returned from hcall() 1460 * H_INT_GET_SOURCE_INFO. 1461 * 1462 * Parameters: 1463 * Input: 1464 * - R4: "flags" 1465 * Bits 0-62: Reserved 1466 * bit 63: Store: Store=1, store operation, else load operation 1467 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1468 * "ibm,xive-lisn-ranges" properties, or as returned by the 1469 * ibm,query-interrupt-source-number RTAS call, or as 1470 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1471 * - R6: "esbOffset" is the offset into the ESB page for the load or 1472 * store operation 1473 * - R7: "storeData" is the data to write for a store operation 1474 * 1475 * Output: 1476 * - R4: The value of the load if load operation, else -1 1477 */ 1478 1479 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63) 1480 1481 static target_ulong h_int_esb(PowerPCCPU *cpu, 1482 SpaprMachineState *spapr, 1483 target_ulong opcode, 1484 target_ulong *args) 1485 { 1486 SpaprXive *xive = spapr->xive; 1487 XiveEAS eas; 1488 target_ulong flags = args[0]; 1489 target_ulong lisn = args[1]; 1490 target_ulong offset = args[2]; 1491 target_ulong data = args[3]; 1492 hwaddr mmio_addr; 1493 XiveSource *xsrc = &xive->source; 1494 1495 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1496 return H_FUNCTION; 1497 } 1498 1499 if (flags & ~SPAPR_XIVE_ESB_STORE) { 1500 return H_PARAMETER; 1501 } 1502 1503 if (lisn >= xive->nr_irqs) { 1504 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1505 lisn); 1506 return H_P2; 1507 } 1508 1509 eas = xive->eat[lisn]; 1510 if (!xive_eas_is_valid(&eas)) { 1511 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1512 lisn); 1513 return H_P2; 1514 } 1515 1516 if (offset > (1ull << xsrc->esb_shift)) { 1517 return H_P3; 1518 } 1519 1520 if (kvm_irqchip_in_kernel()) { 1521 args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data, 1522 flags & SPAPR_XIVE_ESB_STORE); 1523 } else { 1524 mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset; 1525 1526 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, 1527 (flags & SPAPR_XIVE_ESB_STORE))) { 1528 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x%" 1529 HWADDR_PRIx "\n", mmio_addr); 1530 return H_HARDWARE; 1531 } 1532 args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data; 1533 } 1534 return H_SUCCESS; 1535 } 1536 1537 /* 1538 * The H_INT_SYNC hcall() is used to issue hardware syncs that will 1539 * ensure any in flight events for the input lisn are in the event 1540 * queue. 1541 * 1542 * Parameters: 1543 * Input: 1544 * - R4: "flags" 1545 * Bits 0-63: Reserved 1546 * - R5: "lisn" is per "interrupts", "interrupt-map", or 1547 * "ibm,xive-lisn-ranges" properties, or as returned by the 1548 * ibm,query-interrupt-source-number RTAS call, or as 1549 * returned by the H_ALLOCATE_VAS_WINDOW hcall 1550 * 1551 * Output: 1552 * - None 1553 */ 1554 static target_ulong h_int_sync(PowerPCCPU *cpu, 1555 SpaprMachineState *spapr, 1556 target_ulong opcode, 1557 target_ulong *args) 1558 { 1559 SpaprXive *xive = spapr->xive; 1560 XiveEAS eas; 1561 target_ulong flags = args[0]; 1562 target_ulong lisn = args[1]; 1563 1564 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1565 return H_FUNCTION; 1566 } 1567 1568 if (flags) { 1569 return H_PARAMETER; 1570 } 1571 1572 if (lisn >= xive->nr_irqs) { 1573 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", 1574 lisn); 1575 return H_P2; 1576 } 1577 1578 eas = xive->eat[lisn]; 1579 if (!xive_eas_is_valid(&eas)) { 1580 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", 1581 lisn); 1582 return H_P2; 1583 } 1584 1585 /* 1586 * H_STATE should be returned if a H_INT_RESET is in progress. 1587 * This is not needed when running the emulation under QEMU 1588 */ 1589 1590 /* 1591 * This is not real hardware. Nothing to be done unless when 1592 * under KVM 1593 */ 1594 1595 if (kvm_irqchip_in_kernel()) { 1596 Error *local_err = NULL; 1597 1598 kvmppc_xive_sync_source(xive, lisn, &local_err); 1599 if (local_err) { 1600 error_report_err(local_err); 1601 return H_HARDWARE; 1602 } 1603 } 1604 return H_SUCCESS; 1605 } 1606 1607 /* 1608 * The H_INT_RESET hcall() is used to reset all of the partition's 1609 * interrupt exploitation structures to their initial state. This 1610 * means losing all previously set interrupt state set via 1611 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. 1612 * 1613 * Parameters: 1614 * Input: 1615 * - R4: "flags" 1616 * Bits 0-63: Reserved 1617 * 1618 * Output: 1619 * - None 1620 */ 1621 static target_ulong h_int_reset(PowerPCCPU *cpu, 1622 SpaprMachineState *spapr, 1623 target_ulong opcode, 1624 target_ulong *args) 1625 { 1626 SpaprXive *xive = spapr->xive; 1627 target_ulong flags = args[0]; 1628 1629 if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { 1630 return H_FUNCTION; 1631 } 1632 1633 if (flags) { 1634 return H_PARAMETER; 1635 } 1636 1637 device_reset(DEVICE(xive)); 1638 1639 if (kvm_irqchip_in_kernel()) { 1640 Error *local_err = NULL; 1641 1642 kvmppc_xive_reset(xive, &local_err); 1643 if (local_err) { 1644 error_report_err(local_err); 1645 return H_HARDWARE; 1646 } 1647 } 1648 return H_SUCCESS; 1649 } 1650 1651 void spapr_xive_hcall_init(SpaprMachineState *spapr) 1652 { 1653 spapr_register_hypercall(H_INT_GET_SOURCE_INFO, h_int_get_source_info); 1654 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG, h_int_set_source_config); 1655 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG, h_int_get_source_config); 1656 spapr_register_hypercall(H_INT_GET_QUEUE_INFO, h_int_get_queue_info); 1657 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG, h_int_set_queue_config); 1658 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG, h_int_get_queue_config); 1659 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE, 1660 h_int_set_os_reporting_line); 1661 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE, 1662 h_int_get_os_reporting_line); 1663 spapr_register_hypercall(H_INT_ESB, h_int_esb); 1664 spapr_register_hypercall(H_INT_SYNC, h_int_sync); 1665 spapr_register_hypercall(H_INT_RESET, h_int_reset); 1666 } 1667