1 /* 2 * QEMU Sparc SLAVIO interrupt controller emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sparc/sun4m.h" 27 #include "monitor/monitor.h" 28 #include "hw/sysbus.h" 29 #include "trace.h" 30 31 //#define DEBUG_IRQ_COUNT 32 33 /* 34 * Registers of interrupt controller in sun4m. 35 * 36 * This is the interrupt controller part of chip STP2001 (Slave I/O), also 37 * produced as NCR89C105. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt 39 * 40 * There is a system master controller and one for each cpu. 41 * 42 */ 43 44 #define MAX_CPUS 16 45 #define MAX_PILS 16 46 47 struct SLAVIO_INTCTLState; 48 49 typedef struct SLAVIO_CPUINTCTLState { 50 MemoryRegion iomem; 51 struct SLAVIO_INTCTLState *master; 52 uint32_t intreg_pending; 53 uint32_t cpu; 54 uint32_t irl_out; 55 } SLAVIO_CPUINTCTLState; 56 57 #define TYPE_SLAVIO_INTCTL "slavio_intctl" 58 #define SLAVIO_INTCTL(obj) \ 59 OBJECT_CHECK(SLAVIO_INTCTLState, (obj), TYPE_SLAVIO_INTCTL) 60 61 typedef struct SLAVIO_INTCTLState { 62 SysBusDevice parent_obj; 63 64 MemoryRegion iomem; 65 #ifdef DEBUG_IRQ_COUNT 66 uint64_t irq_count[32]; 67 #endif 68 qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS]; 69 SLAVIO_CPUINTCTLState slaves[MAX_CPUS]; 70 uint32_t intregm_pending; 71 uint32_t intregm_disabled; 72 uint32_t target_cpu; 73 } SLAVIO_INTCTLState; 74 75 #define INTCTL_MAXADDR 0xf 76 #define INTCTL_SIZE (INTCTL_MAXADDR + 1) 77 #define INTCTLM_SIZE 0x14 78 #define MASTER_IRQ_MASK ~0x0fa2007f 79 #define MASTER_DISABLE 0x80000000 80 #define CPU_SOFTIRQ_MASK 0xfffe0000 81 #define CPU_IRQ_INT15_IN (1 << 15) 82 #define CPU_IRQ_TIMER_IN (1 << 14) 83 84 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs); 85 86 // per-cpu interrupt controller 87 static uint64_t slavio_intctl_mem_readl(void *opaque, hwaddr addr, 88 unsigned size) 89 { 90 SLAVIO_CPUINTCTLState *s = opaque; 91 uint32_t saddr, ret; 92 93 saddr = addr >> 2; 94 switch (saddr) { 95 case 0: 96 ret = s->intreg_pending; 97 break; 98 default: 99 ret = 0; 100 break; 101 } 102 trace_slavio_intctl_mem_readl(s->cpu, addr, ret); 103 104 return ret; 105 } 106 107 static void slavio_intctl_mem_writel(void *opaque, hwaddr addr, 108 uint64_t val, unsigned size) 109 { 110 SLAVIO_CPUINTCTLState *s = opaque; 111 uint32_t saddr; 112 113 saddr = addr >> 2; 114 trace_slavio_intctl_mem_writel(s->cpu, addr, val); 115 switch (saddr) { 116 case 1: // clear pending softints 117 val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN; 118 s->intreg_pending &= ~val; 119 slavio_check_interrupts(s->master, 1); 120 trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending); 121 break; 122 case 2: // set softint 123 val &= CPU_SOFTIRQ_MASK; 124 s->intreg_pending |= val; 125 slavio_check_interrupts(s->master, 1); 126 trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending); 127 break; 128 default: 129 break; 130 } 131 } 132 133 static const MemoryRegionOps slavio_intctl_mem_ops = { 134 .read = slavio_intctl_mem_readl, 135 .write = slavio_intctl_mem_writel, 136 .endianness = DEVICE_NATIVE_ENDIAN, 137 .valid = { 138 .min_access_size = 4, 139 .max_access_size = 4, 140 }, 141 }; 142 143 // master system interrupt controller 144 static uint64_t slavio_intctlm_mem_readl(void *opaque, hwaddr addr, 145 unsigned size) 146 { 147 SLAVIO_INTCTLState *s = opaque; 148 uint32_t saddr, ret; 149 150 saddr = addr >> 2; 151 switch (saddr) { 152 case 0: 153 ret = s->intregm_pending & ~MASTER_DISABLE; 154 break; 155 case 1: 156 ret = s->intregm_disabled & MASTER_IRQ_MASK; 157 break; 158 case 4: 159 ret = s->target_cpu; 160 break; 161 default: 162 ret = 0; 163 break; 164 } 165 trace_slavio_intctlm_mem_readl(addr, ret); 166 167 return ret; 168 } 169 170 static void slavio_intctlm_mem_writel(void *opaque, hwaddr addr, 171 uint64_t val, unsigned size) 172 { 173 SLAVIO_INTCTLState *s = opaque; 174 uint32_t saddr; 175 176 saddr = addr >> 2; 177 trace_slavio_intctlm_mem_writel(addr, val); 178 switch (saddr) { 179 case 2: // clear (enable) 180 // Force clear unused bits 181 val &= MASTER_IRQ_MASK; 182 s->intregm_disabled &= ~val; 183 trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled); 184 slavio_check_interrupts(s, 1); 185 break; 186 case 3: // set (disable; doesn't affect pending) 187 // Force clear unused bits 188 val &= MASTER_IRQ_MASK; 189 s->intregm_disabled |= val; 190 slavio_check_interrupts(s, 1); 191 trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled); 192 break; 193 case 4: 194 s->target_cpu = val & (MAX_CPUS - 1); 195 slavio_check_interrupts(s, 1); 196 trace_slavio_intctlm_mem_writel_target(s->target_cpu); 197 break; 198 default: 199 break; 200 } 201 } 202 203 static const MemoryRegionOps slavio_intctlm_mem_ops = { 204 .read = slavio_intctlm_mem_readl, 205 .write = slavio_intctlm_mem_writel, 206 .endianness = DEVICE_NATIVE_ENDIAN, 207 .valid = { 208 .min_access_size = 4, 209 .max_access_size = 4, 210 }, 211 }; 212 213 void slavio_pic_info(Monitor *mon, DeviceState *dev) 214 { 215 SLAVIO_INTCTLState *s = SLAVIO_INTCTL(dev); 216 int i; 217 218 for (i = 0; i < MAX_CPUS; i++) { 219 monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i, 220 s->slaves[i].intreg_pending); 221 } 222 monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n", 223 s->intregm_pending, s->intregm_disabled); 224 } 225 226 void slavio_irq_info(Monitor *mon, DeviceState *dev) 227 { 228 #ifndef DEBUG_IRQ_COUNT 229 monitor_printf(mon, "irq statistic code not compiled.\n"); 230 #else 231 SLAVIO_INTCTLState *s = SLAVIO_INTCTL(dev); 232 int i; 233 int64_t count; 234 235 s = SLAVIO_INTCTL(dev); 236 monitor_printf(mon, "IRQ statistics:\n"); 237 for (i = 0; i < 32; i++) { 238 count = s->irq_count[i]; 239 if (count > 0) 240 monitor_printf(mon, "%2d: %" PRId64 "\n", i, count); 241 } 242 #endif 243 } 244 245 static const uint32_t intbit_to_level[] = { 246 2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12, 247 6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0, 248 }; 249 250 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) 251 { 252 uint32_t pending = s->intregm_pending, pil_pending; 253 unsigned int i, j; 254 255 pending &= ~s->intregm_disabled; 256 257 trace_slavio_check_interrupts(pending, s->intregm_disabled); 258 for (i = 0; i < MAX_CPUS; i++) { 259 pil_pending = 0; 260 261 /* If we are the current interrupt target, get hard interrupts */ 262 if (pending && !(s->intregm_disabled & MASTER_DISABLE) && 263 (i == s->target_cpu)) { 264 for (j = 0; j < 32; j++) { 265 if ((pending & (1 << j)) && intbit_to_level[j]) { 266 pil_pending |= 1 << intbit_to_level[j]; 267 } 268 } 269 } 270 271 /* Calculate current pending hard interrupts for display */ 272 s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN | 273 CPU_IRQ_TIMER_IN; 274 if (i == s->target_cpu) { 275 for (j = 0; j < 32; j++) { 276 if ((s->intregm_pending & (1U << j)) && intbit_to_level[j]) { 277 s->slaves[i].intreg_pending |= 1 << intbit_to_level[j]; 278 } 279 } 280 } 281 282 /* Level 15 and CPU timer interrupts are only masked when 283 the MASTER_DISABLE bit is set */ 284 if (!(s->intregm_disabled & MASTER_DISABLE)) { 285 pil_pending |= s->slaves[i].intreg_pending & 286 (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN); 287 } 288 289 /* Add soft interrupts */ 290 pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16; 291 292 if (set_irqs) { 293 /* Since there is not really an interrupt 0 (and pil_pending 294 * and irl_out bit zero are thus always zero) there is no need 295 * to do anything with cpu_irqs[i][0] and it is OK not to do 296 * the j=0 iteration of this loop. 297 */ 298 for (j = MAX_PILS-1; j > 0; j--) { 299 if (pil_pending & (1 << j)) { 300 if (!(s->slaves[i].irl_out & (1 << j))) { 301 qemu_irq_raise(s->cpu_irqs[i][j]); 302 } 303 } else { 304 if (s->slaves[i].irl_out & (1 << j)) { 305 qemu_irq_lower(s->cpu_irqs[i][j]); 306 } 307 } 308 } 309 } 310 s->slaves[i].irl_out = pil_pending; 311 } 312 } 313 314 /* 315 * "irq" here is the bit number in the system interrupt register to 316 * separate serial and keyboard interrupts sharing a level. 317 */ 318 static void slavio_set_irq(void *opaque, int irq, int level) 319 { 320 SLAVIO_INTCTLState *s = opaque; 321 uint32_t mask = 1 << irq; 322 uint32_t pil = intbit_to_level[irq]; 323 unsigned int i; 324 325 trace_slavio_set_irq(s->target_cpu, irq, pil, level); 326 if (pil > 0) { 327 if (level) { 328 #ifdef DEBUG_IRQ_COUNT 329 s->irq_count[pil]++; 330 #endif 331 s->intregm_pending |= mask; 332 if (pil == 15) { 333 for (i = 0; i < MAX_CPUS; i++) { 334 s->slaves[i].intreg_pending |= 1 << pil; 335 } 336 } 337 } else { 338 s->intregm_pending &= ~mask; 339 if (pil == 15) { 340 for (i = 0; i < MAX_CPUS; i++) { 341 s->slaves[i].intreg_pending &= ~(1 << pil); 342 } 343 } 344 } 345 slavio_check_interrupts(s, 1); 346 } 347 } 348 349 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) 350 { 351 SLAVIO_INTCTLState *s = opaque; 352 353 trace_slavio_set_timer_irq_cpu(cpu, level); 354 355 if (level) { 356 s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN; 357 } else { 358 s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN; 359 } 360 361 slavio_check_interrupts(s, 1); 362 } 363 364 static void slavio_set_irq_all(void *opaque, int irq, int level) 365 { 366 if (irq < 32) { 367 slavio_set_irq(opaque, irq, level); 368 } else { 369 slavio_set_timer_irq_cpu(opaque, irq - 32, level); 370 } 371 } 372 373 static int vmstate_intctl_post_load(void *opaque, int version_id) 374 { 375 SLAVIO_INTCTLState *s = opaque; 376 377 slavio_check_interrupts(s, 0); 378 return 0; 379 } 380 381 static const VMStateDescription vmstate_intctl_cpu = { 382 .name ="slavio_intctl_cpu", 383 .version_id = 1, 384 .minimum_version_id = 1, 385 .fields = (VMStateField[]) { 386 VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState), 387 VMSTATE_END_OF_LIST() 388 } 389 }; 390 391 static const VMStateDescription vmstate_intctl = { 392 .name ="slavio_intctl", 393 .version_id = 1, 394 .minimum_version_id = 1, 395 .post_load = vmstate_intctl_post_load, 396 .fields = (VMStateField[]) { 397 VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1, 398 vmstate_intctl_cpu, SLAVIO_CPUINTCTLState), 399 VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState), 400 VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState), 401 VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState), 402 VMSTATE_END_OF_LIST() 403 } 404 }; 405 406 static void slavio_intctl_reset(DeviceState *d) 407 { 408 SLAVIO_INTCTLState *s = SLAVIO_INTCTL(d); 409 int i; 410 411 for (i = 0; i < MAX_CPUS; i++) { 412 s->slaves[i].intreg_pending = 0; 413 s->slaves[i].irl_out = 0; 414 } 415 s->intregm_disabled = ~MASTER_IRQ_MASK; 416 s->intregm_pending = 0; 417 s->target_cpu = 0; 418 slavio_check_interrupts(s, 0); 419 } 420 421 static void slavio_intctl_init(Object *obj) 422 { 423 DeviceState *dev = DEVICE(obj); 424 SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj); 425 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 426 unsigned int i, j; 427 char slave_name[45]; 428 429 qdev_init_gpio_in(dev, slavio_set_irq_all, 32 + MAX_CPUS); 430 memory_region_init_io(&s->iomem, obj, &slavio_intctlm_mem_ops, s, 431 "master-interrupt-controller", INTCTLM_SIZE); 432 sysbus_init_mmio(sbd, &s->iomem); 433 434 for (i = 0; i < MAX_CPUS; i++) { 435 snprintf(slave_name, sizeof(slave_name), 436 "slave-interrupt-controller-%i", i); 437 for (j = 0; j < MAX_PILS; j++) { 438 sysbus_init_irq(sbd, &s->cpu_irqs[i][j]); 439 } 440 memory_region_init_io(&s->slaves[i].iomem, OBJECT(s), 441 &slavio_intctl_mem_ops, 442 &s->slaves[i], slave_name, INTCTL_SIZE); 443 sysbus_init_mmio(sbd, &s->slaves[i].iomem); 444 s->slaves[i].cpu = i; 445 s->slaves[i].master = s; 446 } 447 } 448 449 static void slavio_intctl_class_init(ObjectClass *klass, void *data) 450 { 451 DeviceClass *dc = DEVICE_CLASS(klass); 452 453 dc->reset = slavio_intctl_reset; 454 dc->vmsd = &vmstate_intctl; 455 } 456 457 static const TypeInfo slavio_intctl_info = { 458 .name = TYPE_SLAVIO_INTCTL, 459 .parent = TYPE_SYS_BUS_DEVICE, 460 .instance_size = sizeof(SLAVIO_INTCTLState), 461 .instance_init = slavio_intctl_init, 462 .class_init = slavio_intctl_class_init, 463 }; 464 465 static void slavio_intctl_register_types(void) 466 { 467 type_register_static(&slavio_intctl_info); 468 } 469 470 type_init(slavio_intctl_register_types) 471