1 /* 2 * QEMU Sparc SLAVIO interrupt controller emulation 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sparc/sun4m.h" 27 #include "monitor/monitor.h" 28 #include "hw/sysbus.h" 29 #include "hw/intc/intc.h" 30 #include "trace.h" 31 32 //#define DEBUG_IRQ_COUNT 33 34 /* 35 * Registers of interrupt controller in sun4m. 36 * 37 * This is the interrupt controller part of chip STP2001 (Slave I/O), also 38 * produced as NCR89C105. See 39 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt 40 * 41 * There is a system master controller and one for each cpu. 42 * 43 */ 44 45 #define MAX_CPUS 16 46 #define MAX_PILS 16 47 48 struct SLAVIO_INTCTLState; 49 50 typedef struct SLAVIO_CPUINTCTLState { 51 MemoryRegion iomem; 52 struct SLAVIO_INTCTLState *master; 53 uint32_t intreg_pending; 54 uint32_t cpu; 55 uint32_t irl_out; 56 } SLAVIO_CPUINTCTLState; 57 58 #define TYPE_SLAVIO_INTCTL "slavio_intctl" 59 #define SLAVIO_INTCTL(obj) \ 60 OBJECT_CHECK(SLAVIO_INTCTLState, (obj), TYPE_SLAVIO_INTCTL) 61 62 typedef struct SLAVIO_INTCTLState { 63 SysBusDevice parent_obj; 64 65 MemoryRegion iomem; 66 #ifdef DEBUG_IRQ_COUNT 67 uint64_t irq_count[32]; 68 #endif 69 qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS]; 70 SLAVIO_CPUINTCTLState slaves[MAX_CPUS]; 71 uint32_t intregm_pending; 72 uint32_t intregm_disabled; 73 uint32_t target_cpu; 74 } SLAVIO_INTCTLState; 75 76 #define INTCTL_MAXADDR 0xf 77 #define INTCTL_SIZE (INTCTL_MAXADDR + 1) 78 #define INTCTLM_SIZE 0x14 79 #define MASTER_IRQ_MASK ~0x0fa2007f 80 #define MASTER_DISABLE 0x80000000 81 #define CPU_SOFTIRQ_MASK 0xfffe0000 82 #define CPU_IRQ_INT15_IN (1 << 15) 83 #define CPU_IRQ_TIMER_IN (1 << 14) 84 85 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs); 86 87 // per-cpu interrupt controller 88 static uint64_t slavio_intctl_mem_readl(void *opaque, hwaddr addr, 89 unsigned size) 90 { 91 SLAVIO_CPUINTCTLState *s = opaque; 92 uint32_t saddr, ret; 93 94 saddr = addr >> 2; 95 switch (saddr) { 96 case 0: 97 ret = s->intreg_pending; 98 break; 99 default: 100 ret = 0; 101 break; 102 } 103 trace_slavio_intctl_mem_readl(s->cpu, addr, ret); 104 105 return ret; 106 } 107 108 static void slavio_intctl_mem_writel(void *opaque, hwaddr addr, 109 uint64_t val, unsigned size) 110 { 111 SLAVIO_CPUINTCTLState *s = opaque; 112 uint32_t saddr; 113 114 saddr = addr >> 2; 115 trace_slavio_intctl_mem_writel(s->cpu, addr, val); 116 switch (saddr) { 117 case 1: // clear pending softints 118 val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN; 119 s->intreg_pending &= ~val; 120 slavio_check_interrupts(s->master, 1); 121 trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending); 122 break; 123 case 2: // set softint 124 val &= CPU_SOFTIRQ_MASK; 125 s->intreg_pending |= val; 126 slavio_check_interrupts(s->master, 1); 127 trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending); 128 break; 129 default: 130 break; 131 } 132 } 133 134 static const MemoryRegionOps slavio_intctl_mem_ops = { 135 .read = slavio_intctl_mem_readl, 136 .write = slavio_intctl_mem_writel, 137 .endianness = DEVICE_NATIVE_ENDIAN, 138 .valid = { 139 .min_access_size = 4, 140 .max_access_size = 4, 141 }, 142 }; 143 144 // master system interrupt controller 145 static uint64_t slavio_intctlm_mem_readl(void *opaque, hwaddr addr, 146 unsigned size) 147 { 148 SLAVIO_INTCTLState *s = opaque; 149 uint32_t saddr, ret; 150 151 saddr = addr >> 2; 152 switch (saddr) { 153 case 0: 154 ret = s->intregm_pending & ~MASTER_DISABLE; 155 break; 156 case 1: 157 ret = s->intregm_disabled & MASTER_IRQ_MASK; 158 break; 159 case 4: 160 ret = s->target_cpu; 161 break; 162 default: 163 ret = 0; 164 break; 165 } 166 trace_slavio_intctlm_mem_readl(addr, ret); 167 168 return ret; 169 } 170 171 static void slavio_intctlm_mem_writel(void *opaque, hwaddr addr, 172 uint64_t val, unsigned size) 173 { 174 SLAVIO_INTCTLState *s = opaque; 175 uint32_t saddr; 176 177 saddr = addr >> 2; 178 trace_slavio_intctlm_mem_writel(addr, val); 179 switch (saddr) { 180 case 2: // clear (enable) 181 // Force clear unused bits 182 val &= MASTER_IRQ_MASK; 183 s->intregm_disabled &= ~val; 184 trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled); 185 slavio_check_interrupts(s, 1); 186 break; 187 case 3: // set (disable; doesn't affect pending) 188 // Force clear unused bits 189 val &= MASTER_IRQ_MASK; 190 s->intregm_disabled |= val; 191 slavio_check_interrupts(s, 1); 192 trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled); 193 break; 194 case 4: 195 s->target_cpu = val & (MAX_CPUS - 1); 196 slavio_check_interrupts(s, 1); 197 trace_slavio_intctlm_mem_writel_target(s->target_cpu); 198 break; 199 default: 200 break; 201 } 202 } 203 204 static const MemoryRegionOps slavio_intctlm_mem_ops = { 205 .read = slavio_intctlm_mem_readl, 206 .write = slavio_intctlm_mem_writel, 207 .endianness = DEVICE_NATIVE_ENDIAN, 208 .valid = { 209 .min_access_size = 4, 210 .max_access_size = 4, 211 }, 212 }; 213 214 static const uint32_t intbit_to_level[] = { 215 2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12, 216 6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0, 217 }; 218 219 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) 220 { 221 uint32_t pending = s->intregm_pending, pil_pending; 222 unsigned int i, j; 223 224 pending &= ~s->intregm_disabled; 225 226 trace_slavio_check_interrupts(pending, s->intregm_disabled); 227 for (i = 0; i < MAX_CPUS; i++) { 228 pil_pending = 0; 229 230 /* If we are the current interrupt target, get hard interrupts */ 231 if (pending && !(s->intregm_disabled & MASTER_DISABLE) && 232 (i == s->target_cpu)) { 233 for (j = 0; j < 32; j++) { 234 if ((pending & (1 << j)) && intbit_to_level[j]) { 235 pil_pending |= 1 << intbit_to_level[j]; 236 } 237 } 238 } 239 240 /* Calculate current pending hard interrupts for display */ 241 s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN | 242 CPU_IRQ_TIMER_IN; 243 if (i == s->target_cpu) { 244 for (j = 0; j < 32; j++) { 245 if ((s->intregm_pending & (1U << j)) && intbit_to_level[j]) { 246 s->slaves[i].intreg_pending |= 1 << intbit_to_level[j]; 247 } 248 } 249 } 250 251 /* Level 15 and CPU timer interrupts are only masked when 252 the MASTER_DISABLE bit is set */ 253 if (!(s->intregm_disabled & MASTER_DISABLE)) { 254 pil_pending |= s->slaves[i].intreg_pending & 255 (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN); 256 } 257 258 /* Add soft interrupts */ 259 pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16; 260 261 if (set_irqs) { 262 /* Since there is not really an interrupt 0 (and pil_pending 263 * and irl_out bit zero are thus always zero) there is no need 264 * to do anything with cpu_irqs[i][0] and it is OK not to do 265 * the j=0 iteration of this loop. 266 */ 267 for (j = MAX_PILS-1; j > 0; j--) { 268 if (pil_pending & (1 << j)) { 269 if (!(s->slaves[i].irl_out & (1 << j))) { 270 qemu_irq_raise(s->cpu_irqs[i][j]); 271 } 272 } else { 273 if (s->slaves[i].irl_out & (1 << j)) { 274 qemu_irq_lower(s->cpu_irqs[i][j]); 275 } 276 } 277 } 278 } 279 s->slaves[i].irl_out = pil_pending; 280 } 281 } 282 283 /* 284 * "irq" here is the bit number in the system interrupt register to 285 * separate serial and keyboard interrupts sharing a level. 286 */ 287 static void slavio_set_irq(void *opaque, int irq, int level) 288 { 289 SLAVIO_INTCTLState *s = opaque; 290 uint32_t mask = 1 << irq; 291 uint32_t pil = intbit_to_level[irq]; 292 unsigned int i; 293 294 trace_slavio_set_irq(s->target_cpu, irq, pil, level); 295 if (pil > 0) { 296 if (level) { 297 #ifdef DEBUG_IRQ_COUNT 298 s->irq_count[pil]++; 299 #endif 300 s->intregm_pending |= mask; 301 if (pil == 15) { 302 for (i = 0; i < MAX_CPUS; i++) { 303 s->slaves[i].intreg_pending |= 1 << pil; 304 } 305 } 306 } else { 307 s->intregm_pending &= ~mask; 308 if (pil == 15) { 309 for (i = 0; i < MAX_CPUS; i++) { 310 s->slaves[i].intreg_pending &= ~(1 << pil); 311 } 312 } 313 } 314 slavio_check_interrupts(s, 1); 315 } 316 } 317 318 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) 319 { 320 SLAVIO_INTCTLState *s = opaque; 321 322 trace_slavio_set_timer_irq_cpu(cpu, level); 323 324 if (level) { 325 s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN; 326 } else { 327 s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN; 328 } 329 330 slavio_check_interrupts(s, 1); 331 } 332 333 static void slavio_set_irq_all(void *opaque, int irq, int level) 334 { 335 if (irq < 32) { 336 slavio_set_irq(opaque, irq, level); 337 } else { 338 slavio_set_timer_irq_cpu(opaque, irq - 32, level); 339 } 340 } 341 342 static int vmstate_intctl_post_load(void *opaque, int version_id) 343 { 344 SLAVIO_INTCTLState *s = opaque; 345 346 slavio_check_interrupts(s, 0); 347 return 0; 348 } 349 350 static const VMStateDescription vmstate_intctl_cpu = { 351 .name ="slavio_intctl_cpu", 352 .version_id = 1, 353 .minimum_version_id = 1, 354 .fields = (VMStateField[]) { 355 VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState), 356 VMSTATE_END_OF_LIST() 357 } 358 }; 359 360 static const VMStateDescription vmstate_intctl = { 361 .name ="slavio_intctl", 362 .version_id = 1, 363 .minimum_version_id = 1, 364 .post_load = vmstate_intctl_post_load, 365 .fields = (VMStateField[]) { 366 VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1, 367 vmstate_intctl_cpu, SLAVIO_CPUINTCTLState), 368 VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState), 369 VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState), 370 VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState), 371 VMSTATE_END_OF_LIST() 372 } 373 }; 374 375 static void slavio_intctl_reset(DeviceState *d) 376 { 377 SLAVIO_INTCTLState *s = SLAVIO_INTCTL(d); 378 int i; 379 380 for (i = 0; i < MAX_CPUS; i++) { 381 s->slaves[i].intreg_pending = 0; 382 s->slaves[i].irl_out = 0; 383 } 384 s->intregm_disabled = ~MASTER_IRQ_MASK; 385 s->intregm_pending = 0; 386 s->target_cpu = 0; 387 slavio_check_interrupts(s, 0); 388 } 389 390 #ifdef DEBUG_IRQ_COUNT 391 static bool slavio_intctl_get_statistics(InterruptStatsProvider *obj, 392 uint64_t **irq_counts, 393 unsigned int *nb_irqs) 394 { 395 SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj); 396 *irq_counts = s->irq_count; 397 *nb_irqs = ARRAY_SIZE(s->irq_count); 398 return true; 399 } 400 #endif 401 402 static void slavio_intctl_print_info(InterruptStatsProvider *obj, Monitor *mon) 403 { 404 SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj); 405 int i; 406 407 for (i = 0; i < MAX_CPUS; i++) { 408 monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i, 409 s->slaves[i].intreg_pending); 410 } 411 monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n", 412 s->intregm_pending, s->intregm_disabled); 413 } 414 415 static void slavio_intctl_init(Object *obj) 416 { 417 DeviceState *dev = DEVICE(obj); 418 SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj); 419 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 420 unsigned int i, j; 421 char slave_name[45]; 422 423 qdev_init_gpio_in(dev, slavio_set_irq_all, 32 + MAX_CPUS); 424 memory_region_init_io(&s->iomem, obj, &slavio_intctlm_mem_ops, s, 425 "master-interrupt-controller", INTCTLM_SIZE); 426 sysbus_init_mmio(sbd, &s->iomem); 427 428 for (i = 0; i < MAX_CPUS; i++) { 429 snprintf(slave_name, sizeof(slave_name), 430 "slave-interrupt-controller-%i", i); 431 for (j = 0; j < MAX_PILS; j++) { 432 sysbus_init_irq(sbd, &s->cpu_irqs[i][j]); 433 } 434 memory_region_init_io(&s->slaves[i].iomem, OBJECT(s), 435 &slavio_intctl_mem_ops, 436 &s->slaves[i], slave_name, INTCTL_SIZE); 437 sysbus_init_mmio(sbd, &s->slaves[i].iomem); 438 s->slaves[i].cpu = i; 439 s->slaves[i].master = s; 440 } 441 } 442 443 static void slavio_intctl_class_init(ObjectClass *klass, void *data) 444 { 445 DeviceClass *dc = DEVICE_CLASS(klass); 446 InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass); 447 448 dc->reset = slavio_intctl_reset; 449 dc->vmsd = &vmstate_intctl; 450 #ifdef DEBUG_IRQ_COUNT 451 ic->get_statistics = slavio_intctl_get_statistics; 452 #endif 453 ic->print_info = slavio_intctl_print_info; 454 } 455 456 static const TypeInfo slavio_intctl_info = { 457 .name = TYPE_SLAVIO_INTCTL, 458 .parent = TYPE_SYS_BUS_DEVICE, 459 .instance_size = sizeof(SLAVIO_INTCTLState), 460 .instance_init = slavio_intctl_init, 461 .class_init = slavio_intctl_class_init, 462 .interfaces = (InterfaceInfo[]) { 463 { TYPE_INTERRUPT_STATS_PROVIDER }, 464 { } 465 }, 466 }; 467 468 static void slavio_intctl_register_types(void) 469 { 470 type_register_static(&slavio_intctl_info); 471 } 472 473 type_init(slavio_intctl_register_types) 474