1 /* 2 * SiFive PLIC (Platform Level Interrupt Controller) 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This provides a parameterizable interrupt controller based on SiFive's PLIC. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "qemu/error-report.h" 26 #include "hw/sysbus.h" 27 #include "hw/pci/msi.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/intc/sifive_plic.h" 30 #include "target/riscv/cpu.h" 31 #include "migration/vmstate.h" 32 #include "hw/irq.h" 33 34 #define RISCV_DEBUG_PLIC 0 35 36 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num) 37 { 38 return addr >= base && addr - base < num; 39 } 40 41 static PLICMode char_to_mode(char c) 42 { 43 switch (c) { 44 case 'U': return PLICMode_U; 45 case 'S': return PLICMode_S; 46 case 'H': return PLICMode_H; 47 case 'M': return PLICMode_M; 48 default: 49 error_report("plic: invalid mode '%c'", c); 50 exit(1); 51 } 52 } 53 54 static char mode_to_char(PLICMode m) 55 { 56 switch (m) { 57 case PLICMode_U: return 'U'; 58 case PLICMode_S: return 'S'; 59 case PLICMode_H: return 'H'; 60 case PLICMode_M: return 'M'; 61 default: return '?'; 62 } 63 } 64 65 static void sifive_plic_print_state(SiFivePLICState *plic) 66 { 67 int i; 68 int addrid; 69 70 /* pending */ 71 qemu_log("pending : "); 72 for (i = plic->bitfield_words - 1; i >= 0; i--) { 73 qemu_log("%08x", plic->pending[i]); 74 } 75 qemu_log("\n"); 76 77 /* pending */ 78 qemu_log("claimed : "); 79 for (i = plic->bitfield_words - 1; i >= 0; i--) { 80 qemu_log("%08x", plic->claimed[i]); 81 } 82 qemu_log("\n"); 83 84 for (addrid = 0; addrid < plic->num_addrs; addrid++) { 85 qemu_log("hart%d-%c enable: ", 86 plic->addr_config[addrid].hartid, 87 mode_to_char(plic->addr_config[addrid].mode)); 88 for (i = plic->bitfield_words - 1; i >= 0; i--) { 89 qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]); 90 } 91 qemu_log("\n"); 92 } 93 } 94 95 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value) 96 { 97 uint32_t old, new, cmp = qatomic_read(a); 98 99 do { 100 old = cmp; 101 new = (old & ~mask) | (value & mask); 102 cmp = qatomic_cmpxchg(a, old, new); 103 } while (old != cmp); 104 105 return old; 106 } 107 108 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level) 109 { 110 atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level); 111 } 112 113 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level) 114 { 115 atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level); 116 } 117 118 static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid) 119 { 120 int i, j; 121 for (i = 0; i < plic->bitfield_words; i++) { 122 uint32_t pending_enabled_not_claimed = 123 (plic->pending[i] & ~plic->claimed[i]) & 124 plic->enable[addrid * plic->bitfield_words + i]; 125 if (!pending_enabled_not_claimed) { 126 continue; 127 } 128 for (j = 0; j < 32; j++) { 129 int irq = (i << 5) + j; 130 uint32_t prio = plic->source_priority[irq]; 131 int enabled = pending_enabled_not_claimed & (1 << j); 132 if (enabled && prio > plic->target_priority[addrid]) { 133 return 1; 134 } 135 } 136 } 137 return 0; 138 } 139 140 static void sifive_plic_update(SiFivePLICState *plic) 141 { 142 int addrid; 143 144 /* raise irq on harts where this irq is enabled */ 145 for (addrid = 0; addrid < plic->num_addrs; addrid++) { 146 uint32_t hartid = plic->addr_config[addrid].hartid; 147 PLICMode mode = plic->addr_config[addrid].mode; 148 int level = sifive_plic_irqs_pending(plic, addrid); 149 150 switch (mode) { 151 case PLICMode_M: 152 qemu_set_irq(plic->m_external_irqs[hartid - plic->hartid_base], level); 153 break; 154 case PLICMode_S: 155 qemu_set_irq(plic->s_external_irqs[hartid - plic->hartid_base], level); 156 break; 157 default: 158 break; 159 } 160 } 161 162 if (RISCV_DEBUG_PLIC) { 163 sifive_plic_print_state(plic); 164 } 165 } 166 167 static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid) 168 { 169 int i, j; 170 uint32_t max_irq = 0; 171 uint32_t max_prio = plic->target_priority[addrid]; 172 173 for (i = 0; i < plic->bitfield_words; i++) { 174 uint32_t pending_enabled_not_claimed = 175 (plic->pending[i] & ~plic->claimed[i]) & 176 plic->enable[addrid * plic->bitfield_words + i]; 177 if (!pending_enabled_not_claimed) { 178 continue; 179 } 180 for (j = 0; j < 32; j++) { 181 int irq = (i << 5) + j; 182 uint32_t prio = plic->source_priority[irq]; 183 int enabled = pending_enabled_not_claimed & (1 << j); 184 if (enabled && prio > max_prio) { 185 max_irq = irq; 186 max_prio = prio; 187 } 188 } 189 } 190 191 if (max_irq) { 192 sifive_plic_set_pending(plic, max_irq, false); 193 sifive_plic_set_claimed(plic, max_irq, true); 194 } 195 return max_irq; 196 } 197 198 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) 199 { 200 SiFivePLICState *plic = opaque; 201 202 /* writes must be 4 byte words */ 203 if ((addr & 0x3) != 0) { 204 goto err; 205 } 206 207 if (addr >= plic->priority_base && /* 4 bytes per source */ 208 addr < plic->priority_base + (plic->num_sources << 2)) 209 { 210 uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; 211 if (RISCV_DEBUG_PLIC) { 212 qemu_log("plic: read priority: irq=%d priority=%d\n", 213 irq, plic->source_priority[irq]); 214 } 215 return plic->source_priority[irq]; 216 } else if (addr >= plic->pending_base && /* 1 bit per source */ 217 addr < plic->pending_base + (plic->num_sources >> 3)) 218 { 219 uint32_t word = (addr - plic->pending_base) >> 2; 220 if (RISCV_DEBUG_PLIC) { 221 qemu_log("plic: read pending: word=%d value=%d\n", 222 word, plic->pending[word]); 223 } 224 return plic->pending[word]; 225 } else if (addr >= plic->enable_base && /* 1 bit per source */ 226 addr < plic->enable_base + plic->num_addrs * plic->enable_stride) 227 { 228 uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride; 229 uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2; 230 if (wordid < plic->bitfield_words) { 231 if (RISCV_DEBUG_PLIC) { 232 qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n", 233 plic->addr_config[addrid].hartid, 234 mode_to_char(plic->addr_config[addrid].mode), wordid, 235 plic->enable[addrid * plic->bitfield_words + wordid]); 236 } 237 return plic->enable[addrid * plic->bitfield_words + wordid]; 238 } 239 } else if (addr >= plic->context_base && /* 1 bit per source */ 240 addr < plic->context_base + plic->num_addrs * plic->context_stride) 241 { 242 uint32_t addrid = (addr - plic->context_base) / plic->context_stride; 243 uint32_t contextid = (addr & (plic->context_stride - 1)); 244 if (contextid == 0) { 245 if (RISCV_DEBUG_PLIC) { 246 qemu_log("plic: read priority: hart%d-%c priority=%x\n", 247 plic->addr_config[addrid].hartid, 248 mode_to_char(plic->addr_config[addrid].mode), 249 plic->target_priority[addrid]); 250 } 251 return plic->target_priority[addrid]; 252 } else if (contextid == 4) { 253 uint32_t value = sifive_plic_claim(plic, addrid); 254 if (RISCV_DEBUG_PLIC) { 255 qemu_log("plic: read claim: hart%d-%c irq=%x\n", 256 plic->addr_config[addrid].hartid, 257 mode_to_char(plic->addr_config[addrid].mode), 258 value); 259 } 260 sifive_plic_update(plic); 261 return value; 262 } 263 } 264 265 err: 266 qemu_log_mask(LOG_GUEST_ERROR, 267 "%s: Invalid register read 0x%" HWADDR_PRIx "\n", 268 __func__, addr); 269 return 0; 270 } 271 272 static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, 273 unsigned size) 274 { 275 SiFivePLICState *plic = opaque; 276 277 if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { 278 uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; 279 280 plic->source_priority[irq] = value & 7; 281 sifive_plic_update(plic); 282 } else if (addr_between(addr, plic->pending_base, 283 plic->num_sources >> 3)) { 284 qemu_log_mask(LOG_GUEST_ERROR, 285 "%s: invalid pending write: 0x%" HWADDR_PRIx "", 286 __func__, addr); 287 } else if (addr_between(addr, plic->enable_base, 288 plic->num_addrs * plic->enable_stride)) { 289 uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride; 290 uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2; 291 292 if (wordid < plic->bitfield_words) { 293 plic->enable[addrid * plic->bitfield_words + wordid] = value; 294 } else { 295 qemu_log_mask(LOG_GUEST_ERROR, 296 "%s: Invalid enable write 0x%" HWADDR_PRIx "\n", 297 __func__, addr); 298 } 299 } else if (addr_between(addr, plic->context_base, 300 plic->num_addrs * plic->context_stride)) { 301 uint32_t addrid = (addr - plic->context_base) / plic->context_stride; 302 uint32_t contextid = (addr & (plic->context_stride - 1)); 303 304 if (contextid == 0) { 305 if (value <= plic->num_priorities) { 306 plic->target_priority[addrid] = value; 307 sifive_plic_update(plic); 308 } 309 } else if (contextid == 4) { 310 if (value < plic->num_sources) { 311 sifive_plic_set_claimed(plic, value, false); 312 sifive_plic_update(plic); 313 } 314 } else { 315 qemu_log_mask(LOG_GUEST_ERROR, 316 "%s: Invalid context write 0x%" HWADDR_PRIx "\n", 317 __func__, addr); 318 } 319 } else { 320 qemu_log_mask(LOG_GUEST_ERROR, 321 "%s: Invalid register write 0x%" HWADDR_PRIx "\n", 322 __func__, addr); 323 } 324 } 325 326 static const MemoryRegionOps sifive_plic_ops = { 327 .read = sifive_plic_read, 328 .write = sifive_plic_write, 329 .endianness = DEVICE_LITTLE_ENDIAN, 330 .valid = { 331 .min_access_size = 4, 332 .max_access_size = 4 333 } 334 }; 335 336 static void sifive_plic_reset(DeviceState *dev) 337 { 338 SiFivePLICState *s = SIFIVE_PLIC(dev); 339 int i; 340 341 memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources); 342 memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs); 343 memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words); 344 memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words); 345 memset(s->enable, 0, sizeof(uint32_t) * s->num_enables); 346 347 for (i = 0; i < s->num_harts; i++) { 348 qemu_set_irq(s->m_external_irqs[i], 0); 349 qemu_set_irq(s->s_external_irqs[i], 0); 350 } 351 } 352 353 /* 354 * parse PLIC hart/mode address offset config 355 * 356 * "M" 1 hart with M mode 357 * "MS,MS" 2 harts, 0-1 with M and S mode 358 * "M,MS,MS,MS,MS" 5 harts, 0 with M mode, 1-5 with M and S mode 359 */ 360 static void parse_hart_config(SiFivePLICState *plic) 361 { 362 int addrid, hartid, modes; 363 const char *p; 364 char c; 365 366 /* count and validate hart/mode combinations */ 367 addrid = 0, hartid = 0, modes = 0; 368 p = plic->hart_config; 369 while ((c = *p++)) { 370 if (c == ',') { 371 addrid += ctpop8(modes); 372 modes = 0; 373 hartid++; 374 } else { 375 int m = 1 << char_to_mode(c); 376 if (modes == (modes | m)) { 377 error_report("plic: duplicate mode '%c' in config: %s", 378 c, plic->hart_config); 379 exit(1); 380 } 381 modes |= m; 382 } 383 } 384 if (modes) { 385 addrid += ctpop8(modes); 386 } 387 hartid++; 388 389 plic->num_addrs = addrid; 390 plic->num_harts = hartid; 391 392 /* store hart/mode combinations */ 393 plic->addr_config = g_new(PLICAddr, plic->num_addrs); 394 addrid = 0, hartid = plic->hartid_base; 395 p = plic->hart_config; 396 while ((c = *p++)) { 397 if (c == ',') { 398 hartid++; 399 } else { 400 plic->addr_config[addrid].addrid = addrid; 401 plic->addr_config[addrid].hartid = hartid; 402 plic->addr_config[addrid].mode = char_to_mode(c); 403 addrid++; 404 } 405 } 406 } 407 408 static void sifive_plic_irq_request(void *opaque, int irq, int level) 409 { 410 SiFivePLICState *s = opaque; 411 412 sifive_plic_set_pending(s, irq, level > 0); 413 sifive_plic_update(s); 414 } 415 416 static void sifive_plic_realize(DeviceState *dev, Error **errp) 417 { 418 SiFivePLICState *s = SIFIVE_PLIC(dev); 419 int i; 420 421 memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s, 422 TYPE_SIFIVE_PLIC, s->aperture_size); 423 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); 424 425 parse_hart_config(s); 426 427 s->bitfield_words = (s->num_sources + 31) >> 5; 428 s->num_enables = s->bitfield_words * s->num_addrs; 429 s->source_priority = g_new0(uint32_t, s->num_sources); 430 s->target_priority = g_new(uint32_t, s->num_addrs); 431 s->pending = g_new0(uint32_t, s->bitfield_words); 432 s->claimed = g_new0(uint32_t, s->bitfield_words); 433 s->enable = g_new0(uint32_t, s->num_enables); 434 435 qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources); 436 437 s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts); 438 qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts); 439 440 s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts); 441 qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts); 442 443 /* We can't allow the supervisor to control SEIP as this would allow the 444 * supervisor to clear a pending external interrupt which will result in 445 * lost a interrupt in the case a PLIC is attached. The SEIP bit must be 446 * hardware controlled when a PLIC is attached. 447 */ 448 for (i = 0; i < s->num_harts; i++) { 449 RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); 450 if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { 451 error_report("SEIP already claimed"); 452 exit(1); 453 } 454 } 455 456 msi_nonbroken = true; 457 } 458 459 static const VMStateDescription vmstate_sifive_plic = { 460 .name = "riscv_sifive_plic", 461 .version_id = 1, 462 .minimum_version_id = 1, 463 .fields = (VMStateField[]) { 464 VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState, 465 num_sources, 0, 466 vmstate_info_uint32, uint32_t), 467 VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState, 468 num_addrs, 0, 469 vmstate_info_uint32, uint32_t), 470 VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0, 471 vmstate_info_uint32, uint32_t), 472 VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0, 473 vmstate_info_uint32, uint32_t), 474 VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0, 475 vmstate_info_uint32, uint32_t), 476 VMSTATE_END_OF_LIST() 477 } 478 }; 479 480 static Property sifive_plic_properties[] = { 481 DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config), 482 DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0), 483 DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0), 484 DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0), 485 DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0), 486 DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0), 487 DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0), 488 DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0), 489 DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0), 490 DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0), 491 DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0), 492 DEFINE_PROP_END_OF_LIST(), 493 }; 494 495 static void sifive_plic_class_init(ObjectClass *klass, void *data) 496 { 497 DeviceClass *dc = DEVICE_CLASS(klass); 498 499 dc->reset = sifive_plic_reset; 500 device_class_set_props(dc, sifive_plic_properties); 501 dc->realize = sifive_plic_realize; 502 dc->vmsd = &vmstate_sifive_plic; 503 } 504 505 static const TypeInfo sifive_plic_info = { 506 .name = TYPE_SIFIVE_PLIC, 507 .parent = TYPE_SYS_BUS_DEVICE, 508 .instance_size = sizeof(SiFivePLICState), 509 .class_init = sifive_plic_class_init, 510 }; 511 512 static void sifive_plic_register_types(void) 513 { 514 type_register_static(&sifive_plic_info); 515 } 516 517 type_init(sifive_plic_register_types) 518 519 /* 520 * Create PLIC device. 521 */ 522 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, 523 uint32_t num_harts, 524 uint32_t hartid_base, uint32_t num_sources, 525 uint32_t num_priorities, uint32_t priority_base, 526 uint32_t pending_base, uint32_t enable_base, 527 uint32_t enable_stride, uint32_t context_base, 528 uint32_t context_stride, uint32_t aperture_size) 529 { 530 DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC); 531 int i; 532 533 assert(enable_stride == (enable_stride & -enable_stride)); 534 assert(context_stride == (context_stride & -context_stride)); 535 qdev_prop_set_string(dev, "hart-config", hart_config); 536 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); 537 qdev_prop_set_uint32(dev, "num-sources", num_sources); 538 qdev_prop_set_uint32(dev, "num-priorities", num_priorities); 539 qdev_prop_set_uint32(dev, "priority-base", priority_base); 540 qdev_prop_set_uint32(dev, "pending-base", pending_base); 541 qdev_prop_set_uint32(dev, "enable-base", enable_base); 542 qdev_prop_set_uint32(dev, "enable-stride", enable_stride); 543 qdev_prop_set_uint32(dev, "context-base", context_base); 544 qdev_prop_set_uint32(dev, "context-stride", context_stride); 545 qdev_prop_set_uint32(dev, "aperture-size", aperture_size); 546 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 547 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 548 549 for (i = 0; i < num_harts; i++) { 550 CPUState *cpu = qemu_get_cpu(hartid_base + i); 551 552 qdev_connect_gpio_out(dev, i, 553 qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT)); 554 qdev_connect_gpio_out(dev, num_harts + i, 555 qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); 556 } 557 558 return dev; 559 } 560