1 /* 2 * SiFive PLIC (Platform Level Interrupt Controller) 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This provides a parameterizable interrupt controller based on SiFive's PLIC. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "qemu/error-report.h" 26 #include "hw/sysbus.h" 27 #include "hw/pci/msi.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/intc/sifive_plic.h" 30 #include "target/riscv/cpu.h" 31 #include "migration/vmstate.h" 32 #include "hw/irq.h" 33 #include "sysemu/kvm.h" 34 35 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num) 36 { 37 return addr >= base && addr - base < num; 38 } 39 40 static PLICMode char_to_mode(char c) 41 { 42 switch (c) { 43 case 'U': return PLICMode_U; 44 case 'S': return PLICMode_S; 45 case 'H': return PLICMode_H; 46 case 'M': return PLICMode_M; 47 default: 48 error_report("plic: invalid mode '%c'", c); 49 exit(1); 50 } 51 } 52 53 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value) 54 { 55 uint32_t old, new, cmp = qatomic_read(a); 56 57 do { 58 old = cmp; 59 new = (old & ~mask) | (value & mask); 60 cmp = qatomic_cmpxchg(a, old, new); 61 } while (old != cmp); 62 63 return old; 64 } 65 66 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level) 67 { 68 atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level); 69 } 70 71 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level) 72 { 73 atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level); 74 } 75 76 static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid) 77 { 78 uint32_t max_irq = 0; 79 uint32_t max_prio = plic->target_priority[addrid]; 80 int i, j; 81 int num_irq_in_word = 32; 82 83 for (i = 0; i < plic->bitfield_words; i++) { 84 uint32_t pending_enabled_not_claimed = 85 (plic->pending[i] & ~plic->claimed[i]) & 86 plic->enable[addrid * plic->bitfield_words + i]; 87 88 if (!pending_enabled_not_claimed) { 89 continue; 90 } 91 92 if (i == (plic->bitfield_words - 1)) { 93 /* 94 * If plic->num_sources is not multiple of 32, num-of-irq in last 95 * word is not 32. Compute the num-of-irq of last word to avoid 96 * out-of-bound access of source_priority array. 97 */ 98 num_irq_in_word = plic->num_sources - ((plic->bitfield_words - 1) << 5); 99 } 100 101 for (j = 0; j < num_irq_in_word; j++) { 102 int irq = (i << 5) + j; 103 uint32_t prio = plic->source_priority[irq]; 104 int enabled = pending_enabled_not_claimed & (1 << j); 105 106 if (enabled && prio > max_prio) { 107 max_irq = irq; 108 max_prio = prio; 109 } 110 } 111 } 112 113 return max_irq; 114 } 115 116 static void sifive_plic_update(SiFivePLICState *plic) 117 { 118 int addrid; 119 120 /* raise irq on harts where this irq is enabled */ 121 for (addrid = 0; addrid < plic->num_addrs; addrid++) { 122 uint32_t hartid = plic->addr_config[addrid].hartid; 123 PLICMode mode = plic->addr_config[addrid].mode; 124 bool level = !!sifive_plic_claimed(plic, addrid); 125 126 switch (mode) { 127 case PLICMode_M: 128 qemu_set_irq(plic->m_external_irqs[hartid - plic->hartid_base], level); 129 break; 130 case PLICMode_S: 131 qemu_set_irq(plic->s_external_irqs[hartid - plic->hartid_base], level); 132 break; 133 default: 134 break; 135 } 136 } 137 } 138 139 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) 140 { 141 SiFivePLICState *plic = opaque; 142 143 if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { 144 uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; 145 146 return plic->source_priority[irq]; 147 } else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) { 148 uint32_t word = (addr - plic->pending_base) >> 2; 149 150 return plic->pending[word]; 151 } else if (addr_between(addr, plic->enable_base, 152 plic->num_addrs * plic->enable_stride)) { 153 uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride; 154 uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2; 155 156 if (wordid < plic->bitfield_words) { 157 return plic->enable[addrid * plic->bitfield_words + wordid]; 158 } 159 } else if (addr_between(addr, plic->context_base, 160 plic->num_addrs * plic->context_stride)) { 161 uint32_t addrid = (addr - plic->context_base) / plic->context_stride; 162 uint32_t contextid = (addr & (plic->context_stride - 1)); 163 164 if (contextid == 0) { 165 return plic->target_priority[addrid]; 166 } else if (contextid == 4) { 167 uint32_t max_irq = sifive_plic_claimed(plic, addrid); 168 169 if (max_irq) { 170 sifive_plic_set_pending(plic, max_irq, false); 171 sifive_plic_set_claimed(plic, max_irq, true); 172 } 173 174 sifive_plic_update(plic); 175 return max_irq; 176 } 177 } 178 179 qemu_log_mask(LOG_GUEST_ERROR, 180 "%s: Invalid register read 0x%" HWADDR_PRIx "\n", 181 __func__, addr); 182 return 0; 183 } 184 185 static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, 186 unsigned size) 187 { 188 SiFivePLICState *plic = opaque; 189 190 if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { 191 uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; 192 193 if (((plic->num_priorities + 1) & plic->num_priorities) == 0) { 194 /* 195 * if "num_priorities + 1" is power-of-2, make each register bit of 196 * interrupt priority WARL (Write-Any-Read-Legal). Just filter 197 * out the access to unsupported priority bits. 198 */ 199 plic->source_priority[irq] = value % (plic->num_priorities + 1); 200 sifive_plic_update(plic); 201 } else if (value <= plic->num_priorities) { 202 plic->source_priority[irq] = value; 203 sifive_plic_update(plic); 204 } 205 } else if (addr_between(addr, plic->pending_base, 206 plic->num_sources >> 3)) { 207 qemu_log_mask(LOG_GUEST_ERROR, 208 "%s: invalid pending write: 0x%" HWADDR_PRIx "", 209 __func__, addr); 210 } else if (addr_between(addr, plic->enable_base, 211 plic->num_addrs * plic->enable_stride)) { 212 uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride; 213 uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2; 214 215 if (wordid < plic->bitfield_words) { 216 plic->enable[addrid * plic->bitfield_words + wordid] = value; 217 } else { 218 qemu_log_mask(LOG_GUEST_ERROR, 219 "%s: Invalid enable write 0x%" HWADDR_PRIx "\n", 220 __func__, addr); 221 } 222 } else if (addr_between(addr, plic->context_base, 223 plic->num_addrs * plic->context_stride)) { 224 uint32_t addrid = (addr - plic->context_base) / plic->context_stride; 225 uint32_t contextid = (addr & (plic->context_stride - 1)); 226 227 if (contextid == 0) { 228 if (((plic->num_priorities + 1) & plic->num_priorities) == 0) { 229 /* 230 * if "num_priorities + 1" is power-of-2, each register bit of 231 * interrupt priority is WARL (Write-Any-Read-Legal). Just 232 * filter out the access to unsupported priority bits. 233 */ 234 plic->target_priority[addrid] = value % 235 (plic->num_priorities + 1); 236 sifive_plic_update(plic); 237 } else if (value <= plic->num_priorities) { 238 plic->target_priority[addrid] = value; 239 sifive_plic_update(plic); 240 } 241 } else if (contextid == 4) { 242 if (value < plic->num_sources) { 243 sifive_plic_set_claimed(plic, value, false); 244 sifive_plic_update(plic); 245 } 246 } else { 247 qemu_log_mask(LOG_GUEST_ERROR, 248 "%s: Invalid context write 0x%" HWADDR_PRIx "\n", 249 __func__, addr); 250 } 251 } else { 252 qemu_log_mask(LOG_GUEST_ERROR, 253 "%s: Invalid register write 0x%" HWADDR_PRIx "\n", 254 __func__, addr); 255 } 256 } 257 258 static const MemoryRegionOps sifive_plic_ops = { 259 .read = sifive_plic_read, 260 .write = sifive_plic_write, 261 .endianness = DEVICE_LITTLE_ENDIAN, 262 .valid = { 263 .min_access_size = 4, 264 .max_access_size = 4 265 } 266 }; 267 268 static void sifive_plic_reset(DeviceState *dev) 269 { 270 SiFivePLICState *s = SIFIVE_PLIC(dev); 271 int i; 272 273 memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources); 274 memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs); 275 memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words); 276 memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words); 277 memset(s->enable, 0, sizeof(uint32_t) * s->num_enables); 278 279 for (i = 0; i < s->num_harts; i++) { 280 qemu_set_irq(s->m_external_irqs[i], 0); 281 qemu_set_irq(s->s_external_irqs[i], 0); 282 } 283 } 284 285 /* 286 * parse PLIC hart/mode address offset config 287 * 288 * "M" 1 hart with M mode 289 * "MS,MS" 2 harts, 0-1 with M and S mode 290 * "M,MS,MS,MS,MS" 5 harts, 0 with M mode, 1-5 with M and S mode 291 */ 292 static void parse_hart_config(SiFivePLICState *plic) 293 { 294 int addrid, hartid, modes; 295 const char *p; 296 char c; 297 298 /* count and validate hart/mode combinations */ 299 addrid = 0, hartid = 0, modes = 0; 300 p = plic->hart_config; 301 while ((c = *p++)) { 302 if (c == ',') { 303 addrid += ctpop8(modes); 304 modes = 0; 305 hartid++; 306 } else { 307 int m = 1 << char_to_mode(c); 308 if (modes == (modes | m)) { 309 error_report("plic: duplicate mode '%c' in config: %s", 310 c, plic->hart_config); 311 exit(1); 312 } 313 modes |= m; 314 } 315 } 316 if (modes) { 317 addrid += ctpop8(modes); 318 } 319 hartid++; 320 321 plic->num_addrs = addrid; 322 plic->num_harts = hartid; 323 324 /* store hart/mode combinations */ 325 plic->addr_config = g_new(PLICAddr, plic->num_addrs); 326 addrid = 0, hartid = plic->hartid_base; 327 p = plic->hart_config; 328 while ((c = *p++)) { 329 if (c == ',') { 330 hartid++; 331 } else { 332 plic->addr_config[addrid].addrid = addrid; 333 plic->addr_config[addrid].hartid = hartid; 334 plic->addr_config[addrid].mode = char_to_mode(c); 335 addrid++; 336 } 337 } 338 } 339 340 static void sifive_plic_irq_request(void *opaque, int irq, int level) 341 { 342 SiFivePLICState *s = opaque; 343 344 sifive_plic_set_pending(s, irq, level > 0); 345 sifive_plic_update(s); 346 } 347 348 static void sifive_plic_realize(DeviceState *dev, Error **errp) 349 { 350 SiFivePLICState *s = SIFIVE_PLIC(dev); 351 int i; 352 353 memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s, 354 TYPE_SIFIVE_PLIC, s->aperture_size); 355 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); 356 357 parse_hart_config(s); 358 359 s->bitfield_words = (s->num_sources + 31) >> 5; 360 s->num_enables = s->bitfield_words * s->num_addrs; 361 s->source_priority = g_new0(uint32_t, s->num_sources); 362 s->target_priority = g_new(uint32_t, s->num_addrs); 363 s->pending = g_new0(uint32_t, s->bitfield_words); 364 s->claimed = g_new0(uint32_t, s->bitfield_words); 365 s->enable = g_new0(uint32_t, s->num_enables); 366 367 qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources); 368 369 s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts); 370 qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts); 371 372 s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts); 373 qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts); 374 375 /* We can't allow the supervisor to control SEIP as this would allow the 376 * supervisor to clear a pending external interrupt which will result in 377 * lost a interrupt in the case a PLIC is attached. The SEIP bit must be 378 * hardware controlled when a PLIC is attached. 379 */ 380 for (i = 0; i < s->num_harts; i++) { 381 RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); 382 if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) { 383 error_report("SEIP already claimed"); 384 exit(1); 385 } 386 } 387 388 msi_nonbroken = true; 389 } 390 391 static const VMStateDescription vmstate_sifive_plic = { 392 .name = "riscv_sifive_plic", 393 .version_id = 1, 394 .minimum_version_id = 1, 395 .fields = (VMStateField[]) { 396 VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState, 397 num_sources, 0, 398 vmstate_info_uint32, uint32_t), 399 VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState, 400 num_addrs, 0, 401 vmstate_info_uint32, uint32_t), 402 VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0, 403 vmstate_info_uint32, uint32_t), 404 VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0, 405 vmstate_info_uint32, uint32_t), 406 VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0, 407 vmstate_info_uint32, uint32_t), 408 VMSTATE_END_OF_LIST() 409 } 410 }; 411 412 static Property sifive_plic_properties[] = { 413 DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config), 414 DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0), 415 DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0), 416 DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0), 417 DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0), 418 DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0), 419 DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0), 420 DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0), 421 DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0), 422 DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0), 423 DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0), 424 DEFINE_PROP_END_OF_LIST(), 425 }; 426 427 static void sifive_plic_class_init(ObjectClass *klass, void *data) 428 { 429 DeviceClass *dc = DEVICE_CLASS(klass); 430 431 dc->reset = sifive_plic_reset; 432 device_class_set_props(dc, sifive_plic_properties); 433 dc->realize = sifive_plic_realize; 434 dc->vmsd = &vmstate_sifive_plic; 435 } 436 437 static const TypeInfo sifive_plic_info = { 438 .name = TYPE_SIFIVE_PLIC, 439 .parent = TYPE_SYS_BUS_DEVICE, 440 .instance_size = sizeof(SiFivePLICState), 441 .class_init = sifive_plic_class_init, 442 }; 443 444 static void sifive_plic_register_types(void) 445 { 446 type_register_static(&sifive_plic_info); 447 } 448 449 type_init(sifive_plic_register_types) 450 451 /* 452 * Create PLIC device. 453 */ 454 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, 455 uint32_t num_harts, 456 uint32_t hartid_base, uint32_t num_sources, 457 uint32_t num_priorities, uint32_t priority_base, 458 uint32_t pending_base, uint32_t enable_base, 459 uint32_t enable_stride, uint32_t context_base, 460 uint32_t context_stride, uint32_t aperture_size) 461 { 462 DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC); 463 int i; 464 SiFivePLICState *plic; 465 466 assert(enable_stride == (enable_stride & -enable_stride)); 467 assert(context_stride == (context_stride & -context_stride)); 468 qdev_prop_set_string(dev, "hart-config", hart_config); 469 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); 470 qdev_prop_set_uint32(dev, "num-sources", num_sources); 471 qdev_prop_set_uint32(dev, "num-priorities", num_priorities); 472 qdev_prop_set_uint32(dev, "priority-base", priority_base); 473 qdev_prop_set_uint32(dev, "pending-base", pending_base); 474 qdev_prop_set_uint32(dev, "enable-base", enable_base); 475 qdev_prop_set_uint32(dev, "enable-stride", enable_stride); 476 qdev_prop_set_uint32(dev, "context-base", context_base); 477 qdev_prop_set_uint32(dev, "context-stride", context_stride); 478 qdev_prop_set_uint32(dev, "aperture-size", aperture_size); 479 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 480 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 481 482 plic = SIFIVE_PLIC(dev); 483 484 for (i = 0; i < plic->num_addrs; i++) { 485 int cpu_num = plic->addr_config[i].hartid; 486 CPUState *cpu = qemu_get_cpu(cpu_num); 487 488 if (plic->addr_config[i].mode == PLICMode_M) { 489 qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts, 490 qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); 491 } 492 if (plic->addr_config[i].mode == PLICMode_S) { 493 qdev_connect_gpio_out(dev, cpu_num - hartid_base, 494 qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT)); 495 } 496 } 497 498 return dev; 499 } 500