xref: /openbmc/qemu/hw/intc/sh_intc.c (revision 85208f7a9756948ed16ef09d7982584528904430)
1 /*
2  * SuperH interrupt controller module
3  *
4  * Copyright (c) 2007 Magnus Damm
5  * Based on sh_timer.c and arm_timer.c by Paul Brook
6  * Copyright (c) 2005-2006 CodeSourcery.
7  *
8  * This code is licensed under the GPL.
9  */
10 
11 #include "qemu/osdep.h"
12 #include "qemu/log.h"
13 #include "cpu.h"
14 #include "hw/sh4/sh_intc.h"
15 #include "hw/irq.h"
16 #include "hw/sh4/sh.h"
17 #include "trace.h"
18 
19 void sh_intc_toggle_source(struct intc_source *source,
20                            int enable_adj, int assert_adj)
21 {
22     int enable_changed = 0;
23     int pending_changed = 0;
24     int old_pending;
25 
26     if (source->enable_count == source->enable_max && enable_adj == -1) {
27         enable_changed = -1;
28     }
29     source->enable_count += enable_adj;
30 
31     if (source->enable_count == source->enable_max) {
32         enable_changed = 1;
33     }
34     source->asserted += assert_adj;
35 
36     old_pending = source->pending;
37     source->pending = source->asserted &&
38       (source->enable_count == source->enable_max);
39 
40     if (old_pending != source->pending) {
41         pending_changed = 1;
42     }
43     if (pending_changed) {
44         if (source->pending) {
45             source->parent->pending++;
46             if (source->parent->pending == 1) {
47                 cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
48             }
49         } else {
50             source->parent->pending--;
51             if (source->parent->pending == 0) {
52                 cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
53             }
54         }
55     }
56 
57     if (enable_changed || assert_adj || pending_changed) {
58         trace_sh_intc_sources(source->parent->pending, source->asserted,
59                               source->enable_count, source->enable_max,
60                               source->vect, source->asserted ? "asserted " :
61                               assert_adj ? "deasserted" : "",
62                               enable_changed == 1 ? "enabled " :
63                               enable_changed == -1 ? "disabled " : "",
64                               source->pending ? "pending" : "");
65     }
66 }
67 
68 static void sh_intc_set_irq(void *opaque, int n, int level)
69 {
70     struct intc_desc *desc = opaque;
71     struct intc_source *source = &desc->sources[n];
72 
73     if (level && !source->asserted) {
74         sh_intc_toggle_source(source, 0, 1);
75     } else if (!level && source->asserted) {
76         sh_intc_toggle_source(source, 0, -1);
77     }
78 }
79 
80 int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
81 {
82     unsigned int i;
83 
84     /* slow: use a linked lists of pending sources instead */
85     /* wrong: take interrupt priority into account (one list per priority) */
86 
87     if (imask == 0x0f) {
88         return -1; /* FIXME, update code to include priority per source */
89     }
90 
91     for (i = 0; i < desc->nr_sources; i++) {
92         struct intc_source *source = &desc->sources[i];
93 
94         if (source->pending) {
95             trace_sh_intc_pending(desc->pending, source->vect);
96             return source->vect;
97         }
98     }
99     g_assert_not_reached();
100 }
101 
102 typedef enum {
103     INTC_MODE_NONE,
104     INTC_MODE_DUAL_SET,
105     INTC_MODE_DUAL_CLR,
106     INTC_MODE_ENABLE_REG,
107     INTC_MODE_MASK_REG,
108 } SHIntCMode;
109 #define INTC_MODE_IS_PRIO 0x80
110 
111 static SHIntCMode sh_intc_mode(unsigned long address, unsigned long set_reg,
112                                unsigned long clr_reg)
113 {
114     if (address != A7ADDR(set_reg) && address != A7ADDR(clr_reg)) {
115         return INTC_MODE_NONE;
116     }
117     if (set_reg && clr_reg) {
118         return address == A7ADDR(set_reg) ?
119                INTC_MODE_DUAL_SET : INTC_MODE_DUAL_CLR;
120     }
121     return set_reg ? INTC_MODE_ENABLE_REG : INTC_MODE_MASK_REG;
122 }
123 
124 static void sh_intc_locate(struct intc_desc *desc,
125                            unsigned long address,
126                            unsigned long **datap,
127                            intc_enum **enums,
128                            unsigned int *first,
129                            unsigned int *width,
130                            unsigned int *modep)
131 {
132     SHIntCMode mode;
133     unsigned int i;
134 
135     /* this is slow but works for now */
136 
137     if (desc->mask_regs) {
138         for (i = 0; i < desc->nr_mask_regs; i++) {
139             struct intc_mask_reg *mr = &desc->mask_regs[i];
140 
141             mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
142             if (mode == INTC_MODE_NONE) {
143                 continue;
144             }
145             *modep = mode;
146             *datap = &mr->value;
147             *enums = mr->enum_ids;
148             *first = mr->reg_width - 1;
149             *width = 1;
150             return;
151         }
152     }
153 
154     if (desc->prio_regs) {
155         for (i = 0; i < desc->nr_prio_regs; i++) {
156             struct intc_prio_reg *pr = &desc->prio_regs[i];
157 
158             mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
159             if (mode == INTC_MODE_NONE) {
160                 continue;
161             }
162             *modep = mode | INTC_MODE_IS_PRIO;
163             *datap = &pr->value;
164             *enums = pr->enum_ids;
165             *first = pr->reg_width / pr->field_width - 1;
166             *width = pr->field_width;
167             return;
168         }
169     }
170     g_assert_not_reached();
171 }
172 
173 static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
174                                 int enable, int is_group)
175 {
176     struct intc_source *source = &desc->sources[id];
177 
178     if (!id) {
179         return;
180     }
181     if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
182         qemu_log_mask(LOG_UNIMP,
183                       "sh_intc: reserved interrupt source %d modified\n", id);
184         return;
185     }
186 
187     if (source->vect) {
188         sh_intc_toggle_source(source, enable ? 1 : -1, 0);
189     }
190 
191     if ((is_group || !source->vect) && source->next_enum_id) {
192         sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
193     }
194 
195     if (!source->vect) {
196         trace_sh_intc_set(id, !!enable);
197     }
198 }
199 
200 static uint64_t sh_intc_read(void *opaque, hwaddr offset,
201                              unsigned size)
202 {
203     struct intc_desc *desc = opaque;
204     intc_enum *enum_ids = NULL;
205     unsigned int first = 0;
206     unsigned int width = 0;
207     unsigned int mode = 0;
208     unsigned long *valuep;
209 
210     sh_intc_locate(desc, (unsigned long)offset, &valuep,
211                    &enum_ids, &first, &width, &mode);
212     trace_sh_intc_read(size, (uint64_t)offset, *valuep);
213     return *valuep;
214 }
215 
216 static void sh_intc_write(void *opaque, hwaddr offset,
217                           uint64_t value, unsigned size)
218 {
219     struct intc_desc *desc = opaque;
220     intc_enum *enum_ids = NULL;
221     unsigned int first = 0;
222     unsigned int width = 0;
223     unsigned int mode = 0;
224     unsigned int k;
225     unsigned long *valuep;
226     unsigned long mask;
227 
228     trace_sh_intc_write(size, (uint64_t)offset, value);
229     sh_intc_locate(desc, (unsigned long)offset, &valuep,
230                    &enum_ids, &first, &width, &mode);
231     switch (mode) {
232     case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO:
233         break;
234     case INTC_MODE_DUAL_SET:
235         value |= *valuep;
236         break;
237     case INTC_MODE_DUAL_CLR:
238         value = *valuep & ~value;
239         break;
240     default:
241         g_assert_not_reached();
242     }
243 
244     for (k = 0; k <= first; k++) {
245         mask = (1 << width) - 1;
246         mask <<= (first - k) * width;
247 
248         if ((*valuep & mask) == (value & mask)) {
249             continue;
250         }
251         sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
252     }
253 
254     *valuep = value;
255 }
256 
257 static const MemoryRegionOps sh_intc_ops = {
258     .read = sh_intc_read,
259     .write = sh_intc_write,
260     .endianness = DEVICE_NATIVE_ENDIAN,
261 };
262 
263 static void sh_intc_register_source(struct intc_desc *desc,
264                                     intc_enum source,
265                                     struct intc_group *groups,
266                                     int nr_groups)
267 {
268     unsigned int i, k;
269     intc_enum id;
270 
271     if (desc->mask_regs) {
272         for (i = 0; i < desc->nr_mask_regs; i++) {
273             struct intc_mask_reg *mr = &desc->mask_regs[i];
274 
275             for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
276                 id = mr->enum_ids[k];
277                 if (id && id == source) {
278                     desc->sources[id].enable_max++;
279                 }
280             }
281         }
282     }
283 
284     if (desc->prio_regs) {
285         for (i = 0; i < desc->nr_prio_regs; i++) {
286             struct intc_prio_reg *pr = &desc->prio_regs[i];
287 
288             for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
289                 id = pr->enum_ids[k];
290                 if (id && id == source) {
291                     desc->sources[id].enable_max++;
292                 }
293             }
294         }
295     }
296 
297     if (groups) {
298         for (i = 0; i < nr_groups; i++) {
299             struct intc_group *gr = &groups[i];
300 
301             for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
302                 id = gr->enum_ids[k];
303                 if (id && id == source) {
304                     desc->sources[id].enable_max++;
305                 }
306             }
307         }
308     }
309 
310 }
311 
312 void sh_intc_register_sources(struct intc_desc *desc,
313                               struct intc_vect *vectors,
314                               int nr_vectors,
315                               struct intc_group *groups,
316                               int nr_groups)
317 {
318     unsigned int i, k;
319     intc_enum id;
320     struct intc_source *s;
321 
322     for (i = 0; i < nr_vectors; i++) {
323         struct intc_vect *vect = &vectors[i];
324 
325         sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
326         id = vect->enum_id;
327         if (id) {
328             s = &desc->sources[id];
329             s->vect = vect->vect;
330             trace_sh_intc_register("source", vect->enum_id, s->vect,
331                                    s->enable_count, s->enable_max);
332         }
333     }
334 
335     if (groups) {
336         for (i = 0; i < nr_groups; i++) {
337             struct intc_group *gr = &groups[i];
338 
339             id = gr->enum_id;
340             s = &desc->sources[id];
341             s->next_enum_id = gr->enum_ids[0];
342 
343             for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
344                 if (!gr->enum_ids[k]) {
345                     continue;
346                 }
347                 id = gr->enum_ids[k - 1];
348                 s = &desc->sources[id];
349                 s->next_enum_id = gr->enum_ids[k];
350             }
351             trace_sh_intc_register("group", gr->enum_id, 0xffff,
352                                    s->enable_count, s->enable_max);
353         }
354     }
355 }
356 
357 static unsigned int sh_intc_register(MemoryRegion *sysmem,
358                                      struct intc_desc *desc,
359                                      const unsigned long address,
360                                      const char *type,
361                                      const char *action,
362                                      const unsigned int index)
363 {
364     char name[60];
365     MemoryRegion *iomem, *iomem_p4, *iomem_a7;
366 
367     if (!address) {
368         return 0;
369     }
370 
371     iomem = &desc->iomem;
372     iomem_p4 = &desc->iomem_aliases[index];
373     iomem_a7 = iomem_p4 + 1;
374 
375     snprintf(name, sizeof(name), "intc-%s-%s-%s", type, action, "p4");
376     memory_region_init_alias(iomem_p4, NULL, name, iomem, A7ADDR(address), 4);
377     memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
378 
379     snprintf(name, sizeof(name), "intc-%s-%s-%s", type, action, "a7");
380     memory_region_init_alias(iomem_a7, NULL, name, iomem, A7ADDR(address), 4);
381     memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
382 
383     /* used to increment aliases index */
384     return 2;
385 }
386 
387 int sh_intc_init(MemoryRegion *sysmem,
388                  struct intc_desc *desc,
389                  int nr_sources,
390                  struct intc_mask_reg *mask_regs,
391                  int nr_mask_regs,
392                  struct intc_prio_reg *prio_regs,
393                  int nr_prio_regs)
394 {
395     unsigned int i, j;
396 
397     desc->pending = 0;
398     desc->nr_sources = nr_sources;
399     desc->mask_regs = mask_regs;
400     desc->nr_mask_regs = nr_mask_regs;
401     desc->prio_regs = prio_regs;
402     desc->nr_prio_regs = nr_prio_regs;
403     /* Allocate 4 MemoryRegions per register (2 actions * 2 aliases) */
404     desc->iomem_aliases = g_new0(MemoryRegion,
405                                  (nr_mask_regs + nr_prio_regs) * 4);
406 
407     j = 0;
408     i = sizeof(struct intc_source) * nr_sources;
409     desc->sources = g_malloc0(i);
410 
411     for (i = 0; i < desc->nr_sources; i++) {
412         struct intc_source *source = &desc->sources[i];
413 
414         source->parent = desc;
415     }
416 
417     desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
418     memory_region_init_io(&desc->iomem, NULL, &sh_intc_ops, desc, "intc",
419                           0x100000000ULL);
420 
421     if (desc->mask_regs) {
422         for (i = 0; i < desc->nr_mask_regs; i++) {
423             struct intc_mask_reg *mr = &desc->mask_regs[i];
424 
425             j += sh_intc_register(sysmem, desc, mr->set_reg, "mask", "set", j);
426             j += sh_intc_register(sysmem, desc, mr->clr_reg, "mask", "clr", j);
427         }
428     }
429 
430     if (desc->prio_regs) {
431         for (i = 0; i < desc->nr_prio_regs; i++) {
432             struct intc_prio_reg *pr = &desc->prio_regs[i];
433 
434             j += sh_intc_register(sysmem, desc, pr->set_reg, "prio", "set", j);
435             j += sh_intc_register(sysmem, desc, pr->clr_reg, "prio", "clr", j);
436         }
437     }
438 
439     return 0;
440 }
441 
442 /*
443  * Assert level <n> IRL interrupt.
444  * 0:deassert. 1:lowest priority,... 15:highest priority
445  */
446 void sh_intc_set_irl(void *opaque, int n, int level)
447 {
448     struct intc_source *s = opaque;
449     int i, irl = level ^ 15;
450     intc_enum id = s->next_enum_id;
451 
452     for (i = 0; id; id = s->next_enum_id, i++) {
453         s = &s->parent->sources[id];
454         if (i == irl) {
455             sh_intc_toggle_source(s, s->enable_count ? 0 : 1,
456                                   s->asserted ? 0 : 1);
457         } else if (s->asserted) {
458             sh_intc_toggle_source(s, 0, -1);
459         }
460     }
461 }
462