xref: /openbmc/qemu/hw/intc/sh_intc.c (revision 418a221c2b8a97838980e61cdfef356ec6976e4b)
1 /*
2  * SuperH interrupt controller module
3  *
4  * Copyright (c) 2007 Magnus Damm
5  * Based on sh_timer.c and arm_timer.c by Paul Brook
6  * Copyright (c) 2005-2006 CodeSourcery.
7  *
8  * This code is licensed under the GPL.
9  */
10 
11 #include "qemu/osdep.h"
12 #include "qemu/log.h"
13 #include "cpu.h"
14 #include "hw/sh4/sh_intc.h"
15 #include "hw/irq.h"
16 #include "hw/sh4/sh.h"
17 #include "trace.h"
18 
19 void sh_intc_toggle_source(struct intc_source *source,
20                            int enable_adj, int assert_adj)
21 {
22     int enable_changed = 0;
23     int pending_changed = 0;
24     int old_pending;
25 
26     if (source->enable_count == source->enable_max && enable_adj == -1) {
27         enable_changed = -1;
28     }
29     source->enable_count += enable_adj;
30 
31     if (source->enable_count == source->enable_max) {
32         enable_changed = 1;
33     }
34     source->asserted += assert_adj;
35 
36     old_pending = source->pending;
37     source->pending = source->asserted &&
38       (source->enable_count == source->enable_max);
39 
40     if (old_pending != source->pending) {
41         pending_changed = 1;
42     }
43     if (pending_changed) {
44         if (source->pending) {
45             source->parent->pending++;
46             if (source->parent->pending == 1) {
47                 cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
48             }
49         } else {
50             source->parent->pending--;
51             if (source->parent->pending == 0) {
52                 cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
53             }
54         }
55     }
56 
57     if (enable_changed || assert_adj || pending_changed) {
58         trace_sh_intc_sources(source->parent->pending, source->asserted,
59                               source->enable_count, source->enable_max,
60                               source->vect, source->asserted ? "asserted " :
61                               assert_adj ? "deasserted" : "",
62                               enable_changed == 1 ? "enabled " :
63                               enable_changed == -1 ? "disabled " : "",
64                               source->pending ? "pending" : "");
65     }
66 }
67 
68 static void sh_intc_set_irq(void *opaque, int n, int level)
69 {
70     struct intc_desc *desc = opaque;
71     struct intc_source *source = &desc->sources[n];
72 
73     if (level && !source->asserted) {
74         sh_intc_toggle_source(source, 0, 1);
75     } else if (!level && source->asserted) {
76         sh_intc_toggle_source(source, 0, -1);
77     }
78 }
79 
80 int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
81 {
82     unsigned int i;
83 
84     /* slow: use a linked lists of pending sources instead */
85     /* wrong: take interrupt priority into account (one list per priority) */
86 
87     if (imask == 0x0f) {
88         return -1; /* FIXME, update code to include priority per source */
89     }
90 
91     for (i = 0; i < desc->nr_sources; i++) {
92         struct intc_source *source = &desc->sources[i];
93 
94         if (source->pending) {
95             trace_sh_intc_pending(desc->pending, source->vect);
96             return source->vect;
97         }
98     }
99     g_assert_not_reached();
100 }
101 
102 typedef enum {
103     INTC_MODE_NONE,
104     INTC_MODE_DUAL_SET,
105     INTC_MODE_DUAL_CLR,
106     INTC_MODE_ENABLE_REG,
107     INTC_MODE_MASK_REG,
108 } SHIntCMode;
109 #define INTC_MODE_IS_PRIO 0x80
110 
111 static SHIntCMode sh_intc_mode(unsigned long address, unsigned long set_reg,
112                                unsigned long clr_reg)
113 {
114     if (address != A7ADDR(set_reg) && address != A7ADDR(clr_reg)) {
115         return INTC_MODE_NONE;
116     }
117     if (set_reg && clr_reg) {
118         return address == A7ADDR(set_reg) ?
119                INTC_MODE_DUAL_SET : INTC_MODE_DUAL_CLR;
120     }
121     return set_reg ? INTC_MODE_ENABLE_REG : INTC_MODE_MASK_REG;
122 }
123 
124 static void sh_intc_locate(struct intc_desc *desc,
125                            unsigned long address,
126                            unsigned long **datap,
127                            intc_enum **enums,
128                            unsigned int *first,
129                            unsigned int *width,
130                            unsigned int *modep)
131 {
132     SHIntCMode mode;
133     unsigned int i;
134 
135     /* this is slow but works for now */
136 
137     if (desc->mask_regs) {
138         for (i = 0; i < desc->nr_mask_regs; i++) {
139             struct intc_mask_reg *mr = &desc->mask_regs[i];
140 
141             mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
142             if (mode != INTC_MODE_NONE) {
143                 *modep = mode;
144                 *datap = &mr->value;
145                 *enums = mr->enum_ids;
146                 *first = mr->reg_width - 1;
147                 *width = 1;
148                 return;
149             }
150         }
151     }
152 
153     if (desc->prio_regs) {
154         for (i = 0; i < desc->nr_prio_regs; i++) {
155             struct intc_prio_reg *pr = &desc->prio_regs[i];
156 
157             mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
158             if (mode != INTC_MODE_NONE) {
159                 *modep = mode | INTC_MODE_IS_PRIO;
160                 *datap = &pr->value;
161                 *enums = pr->enum_ids;
162                 *first = pr->reg_width / pr->field_width - 1;
163                 *width = pr->field_width;
164                 return;
165             }
166         }
167     }
168     g_assert_not_reached();
169 }
170 
171 static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
172                                 int enable, int is_group)
173 {
174     struct intc_source *source = &desc->sources[id];
175 
176     if (!id) {
177         return;
178     }
179     if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
180         qemu_log_mask(LOG_UNIMP,
181                       "sh_intc: reserved interrupt source %d modified\n", id);
182         return;
183     }
184 
185     if (source->vect) {
186         sh_intc_toggle_source(source, enable ? 1 : -1, 0);
187     }
188 
189     if ((is_group || !source->vect) && source->next_enum_id) {
190         sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
191     }
192 
193     if (!source->vect) {
194         trace_sh_intc_set(id, !!enable);
195     }
196 }
197 
198 static uint64_t sh_intc_read(void *opaque, hwaddr offset,
199                              unsigned size)
200 {
201     struct intc_desc *desc = opaque;
202     intc_enum *enum_ids = NULL;
203     unsigned int first = 0;
204     unsigned int width = 0;
205     unsigned int mode = 0;
206     unsigned long *valuep;
207 
208     sh_intc_locate(desc, (unsigned long)offset, &valuep,
209                    &enum_ids, &first, &width, &mode);
210     trace_sh_intc_read(size, (uint64_t)offset, *valuep);
211     return *valuep;
212 }
213 
214 static void sh_intc_write(void *opaque, hwaddr offset,
215                           uint64_t value, unsigned size)
216 {
217     struct intc_desc *desc = opaque;
218     intc_enum *enum_ids = NULL;
219     unsigned int first = 0;
220     unsigned int width = 0;
221     unsigned int mode = 0;
222     unsigned int k;
223     unsigned long *valuep;
224     unsigned long mask;
225 
226     trace_sh_intc_write(size, (uint64_t)offset, value);
227     sh_intc_locate(desc, (unsigned long)offset, &valuep,
228                    &enum_ids, &first, &width, &mode);
229     switch (mode) {
230     case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO:
231         break;
232     case INTC_MODE_DUAL_SET:
233         value |= *valuep;
234         break;
235     case INTC_MODE_DUAL_CLR:
236         value = *valuep & ~value;
237         break;
238     default:
239         g_assert_not_reached();
240     }
241 
242     for (k = 0; k <= first; k++) {
243         mask = (1 << width) - 1;
244         mask <<= (first - k) * width;
245 
246         if ((*valuep & mask) != (value & mask)) {
247             sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
248         }
249     }
250 
251     *valuep = value;
252 }
253 
254 static const MemoryRegionOps sh_intc_ops = {
255     .read = sh_intc_read,
256     .write = sh_intc_write,
257     .endianness = DEVICE_NATIVE_ENDIAN,
258 };
259 
260 static void sh_intc_register_source(struct intc_desc *desc,
261                                     intc_enum source,
262                                     struct intc_group *groups,
263                                     int nr_groups)
264 {
265     unsigned int i, k;
266     intc_enum id;
267 
268     if (desc->mask_regs) {
269         for (i = 0; i < desc->nr_mask_regs; i++) {
270             struct intc_mask_reg *mr = &desc->mask_regs[i];
271 
272             for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
273                 id = mr->enum_ids[k];
274                 if (id && id == source) {
275                     desc->sources[id].enable_max++;
276                 }
277             }
278         }
279     }
280 
281     if (desc->prio_regs) {
282         for (i = 0; i < desc->nr_prio_regs; i++) {
283             struct intc_prio_reg *pr = &desc->prio_regs[i];
284 
285             for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
286                 id = pr->enum_ids[k];
287                 if (id && id == source) {
288                     desc->sources[id].enable_max++;
289                 }
290             }
291         }
292     }
293 
294     if (groups) {
295         for (i = 0; i < nr_groups; i++) {
296             struct intc_group *gr = &groups[i];
297 
298             for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
299                 id = gr->enum_ids[k];
300                 if (id && id == source) {
301                     desc->sources[id].enable_max++;
302                 }
303             }
304         }
305     }
306 
307 }
308 
309 void sh_intc_register_sources(struct intc_desc *desc,
310                               struct intc_vect *vectors,
311                               int nr_vectors,
312                               struct intc_group *groups,
313                               int nr_groups)
314 {
315     unsigned int i, k;
316     intc_enum id;
317     struct intc_source *s;
318 
319     for (i = 0; i < nr_vectors; i++) {
320         struct intc_vect *vect = &vectors[i];
321 
322         sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
323         id = vect->enum_id;
324         if (id) {
325             s = &desc->sources[id];
326             s->vect = vect->vect;
327             trace_sh_intc_register("source", vect->enum_id, s->vect,
328                                    s->enable_count, s->enable_max);
329         }
330     }
331 
332     if (groups) {
333         for (i = 0; i < nr_groups; i++) {
334             struct intc_group *gr = &groups[i];
335 
336             id = gr->enum_id;
337             s = &desc->sources[id];
338             s->next_enum_id = gr->enum_ids[0];
339 
340             for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
341                 if (gr->enum_ids[k]) {
342                     id = gr->enum_ids[k - 1];
343                     s = &desc->sources[id];
344                     s->next_enum_id = gr->enum_ids[k];
345                 }
346             }
347             trace_sh_intc_register("group", gr->enum_id, 0xffff,
348                                    s->enable_count, s->enable_max);
349         }
350     }
351 }
352 
353 static unsigned int sh_intc_register(MemoryRegion *sysmem,
354                                      struct intc_desc *desc,
355                                      const unsigned long address,
356                                      const char *type,
357                                      const char *action,
358                                      const unsigned int index)
359 {
360     char name[60];
361     MemoryRegion *iomem, *iomem_p4, *iomem_a7;
362 
363     if (!address) {
364         return 0;
365     }
366 
367     iomem = &desc->iomem;
368     iomem_p4 = &desc->iomem_aliases[index];
369     iomem_a7 = iomem_p4 + 1;
370 
371     snprintf(name, sizeof(name), "intc-%s-%s-%s", type, action, "p4");
372     memory_region_init_alias(iomem_p4, NULL, name, iomem, A7ADDR(address), 4);
373     memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
374 
375     snprintf(name, sizeof(name), "intc-%s-%s-%s", type, action, "a7");
376     memory_region_init_alias(iomem_a7, NULL, name, iomem, A7ADDR(address), 4);
377     memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
378 
379     /* used to increment aliases index */
380     return 2;
381 }
382 
383 int sh_intc_init(MemoryRegion *sysmem,
384                  struct intc_desc *desc,
385                  int nr_sources,
386                  struct intc_mask_reg *mask_regs,
387                  int nr_mask_regs,
388                  struct intc_prio_reg *prio_regs,
389                  int nr_prio_regs)
390 {
391     unsigned int i, j;
392 
393     desc->pending = 0;
394     desc->nr_sources = nr_sources;
395     desc->mask_regs = mask_regs;
396     desc->nr_mask_regs = nr_mask_regs;
397     desc->prio_regs = prio_regs;
398     desc->nr_prio_regs = nr_prio_regs;
399     /* Allocate 4 MemoryRegions per register (2 actions * 2 aliases) */
400     desc->iomem_aliases = g_new0(MemoryRegion,
401                                  (nr_mask_regs + nr_prio_regs) * 4);
402 
403     j = 0;
404     i = sizeof(struct intc_source) * nr_sources;
405     desc->sources = g_malloc0(i);
406 
407     for (i = 0; i < desc->nr_sources; i++) {
408         struct intc_source *source = &desc->sources[i];
409 
410         source->parent = desc;
411     }
412 
413     desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
414     memory_region_init_io(&desc->iomem, NULL, &sh_intc_ops, desc, "intc",
415                           0x100000000ULL);
416 
417     if (desc->mask_regs) {
418         for (i = 0; i < desc->nr_mask_regs; i++) {
419             struct intc_mask_reg *mr = &desc->mask_regs[i];
420 
421             j += sh_intc_register(sysmem, desc, mr->set_reg, "mask", "set", j);
422             j += sh_intc_register(sysmem, desc, mr->clr_reg, "mask", "clr", j);
423         }
424     }
425 
426     if (desc->prio_regs) {
427         for (i = 0; i < desc->nr_prio_regs; i++) {
428             struct intc_prio_reg *pr = &desc->prio_regs[i];
429 
430             j += sh_intc_register(sysmem, desc, pr->set_reg, "prio", "set", j);
431             j += sh_intc_register(sysmem, desc, pr->clr_reg, "prio", "clr", j);
432         }
433     }
434 
435     return 0;
436 }
437 
438 /*
439  * Assert level <n> IRL interrupt.
440  * 0:deassert. 1:lowest priority,... 15:highest priority
441  */
442 void sh_intc_set_irl(void *opaque, int n, int level)
443 {
444     struct intc_source *s = opaque;
445     int i, irl = level ^ 15;
446     intc_enum id = s->next_enum_id;
447 
448     for (i = 0; id; id = s->next_enum_id, i++) {
449         s = &s->parent->sources[id];
450         if (i == irl) {
451             sh_intc_toggle_source(s, s->enable_count ? 0 : 1,
452                                   s->asserted ? 0 : 1);
453         } else if (s->asserted) {
454             sh_intc_toggle_source(s, 0, -1);
455         }
456     }
457 }
458