1 /* 2 * RISC-V APLIC (Advanced Platform Level Interrupt Controller) 3 * 4 * Copyright (c) 2021 Western Digital Corporation or its affiliates. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qapi/error.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "qemu/error-report.h" 24 #include "qemu/bswap.h" 25 #include "exec/address-spaces.h" 26 #include "hw/sysbus.h" 27 #include "hw/pci/msi.h" 28 #include "hw/boards.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/intc/riscv_aplic.h" 31 #include "hw/irq.h" 32 #include "target/riscv/cpu.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/kvm.h" 35 #include "kvm/kvm_riscv.h" 36 #include "migration/vmstate.h" 37 38 #define APLIC_MAX_IDC (1UL << 14) 39 #define APLIC_MAX_SOURCE 1024 40 #define APLIC_MIN_IPRIO_BITS 1 41 #define APLIC_MAX_IPRIO_BITS 8 42 #define APLIC_MAX_CHILDREN 1024 43 44 #define APLIC_DOMAINCFG 0x0000 45 #define APLIC_DOMAINCFG_RDONLY 0x80000000 46 #define APLIC_DOMAINCFG_IE (1 << 8) 47 #define APLIC_DOMAINCFG_DM (1 << 2) 48 #define APLIC_DOMAINCFG_BE (1 << 0) 49 50 #define APLIC_SOURCECFG_BASE 0x0004 51 #define APLIC_SOURCECFG_D (1 << 10) 52 #define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff 53 #define APLIC_SOURCECFG_SM_MASK 0x00000007 54 #define APLIC_SOURCECFG_SM_INACTIVE 0x0 55 #define APLIC_SOURCECFG_SM_DETACH 0x1 56 #define APLIC_SOURCECFG_SM_EDGE_RISE 0x4 57 #define APLIC_SOURCECFG_SM_EDGE_FALL 0x5 58 #define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 59 #define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 60 61 #define APLIC_MMSICFGADDR 0x1bc0 62 #define APLIC_MMSICFGADDRH 0x1bc4 63 #define APLIC_SMSICFGADDR 0x1bc8 64 #define APLIC_SMSICFGADDRH 0x1bcc 65 66 #define APLIC_xMSICFGADDRH_L (1UL << 31) 67 #define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f 68 #define APLIC_xMSICFGADDRH_HHXS_SHIFT 24 69 #define APLIC_xMSICFGADDRH_LHXS_MASK 0x7 70 #define APLIC_xMSICFGADDRH_LHXS_SHIFT 20 71 #define APLIC_xMSICFGADDRH_HHXW_MASK 0x7 72 #define APLIC_xMSICFGADDRH_HHXW_SHIFT 16 73 #define APLIC_xMSICFGADDRH_LHXW_MASK 0xf 74 #define APLIC_xMSICFGADDRH_LHXW_SHIFT 12 75 #define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff 76 77 #define APLIC_xMSICFGADDR_PPN_SHIFT 12 78 79 #define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \ 80 ((1UL << (__lhxs)) - 1) 81 82 #define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \ 83 ((1UL << (__lhxw)) - 1) 84 #define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \ 85 ((__lhxs)) 86 #define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \ 87 (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \ 88 APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs)) 89 90 #define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \ 91 ((1UL << (__hhxw)) - 1) 92 #define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \ 93 ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT) 94 #define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \ 95 (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \ 96 APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs)) 97 98 #define APLIC_xMSICFGADDRH_VALID_MASK \ 99 (APLIC_xMSICFGADDRH_L | \ 100 (APLIC_xMSICFGADDRH_HHXS_MASK << APLIC_xMSICFGADDRH_HHXS_SHIFT) | \ 101 (APLIC_xMSICFGADDRH_LHXS_MASK << APLIC_xMSICFGADDRH_LHXS_SHIFT) | \ 102 (APLIC_xMSICFGADDRH_HHXW_MASK << APLIC_xMSICFGADDRH_HHXW_SHIFT) | \ 103 (APLIC_xMSICFGADDRH_LHXW_MASK << APLIC_xMSICFGADDRH_LHXW_SHIFT) | \ 104 APLIC_xMSICFGADDRH_BAPPN_MASK) 105 106 #define APLIC_SETIP_BASE 0x1c00 107 #define APLIC_SETIPNUM 0x1cdc 108 109 #define APLIC_CLRIP_BASE 0x1d00 110 #define APLIC_CLRIPNUM 0x1ddc 111 112 #define APLIC_SETIE_BASE 0x1e00 113 #define APLIC_SETIENUM 0x1edc 114 115 #define APLIC_CLRIE_BASE 0x1f00 116 #define APLIC_CLRIENUM 0x1fdc 117 118 #define APLIC_SETIPNUM_LE 0x2000 119 #define APLIC_SETIPNUM_BE 0x2004 120 121 #define APLIC_ISTATE_PENDING (1U << 0) 122 #define APLIC_ISTATE_ENABLED (1U << 1) 123 #define APLIC_ISTATE_ENPEND (APLIC_ISTATE_ENABLED | \ 124 APLIC_ISTATE_PENDING) 125 #define APLIC_ISTATE_INPUT (1U << 8) 126 127 #define APLIC_GENMSI 0x3000 128 129 #define APLIC_TARGET_BASE 0x3004 130 #define APLIC_TARGET_HART_IDX_SHIFT 18 131 #define APLIC_TARGET_HART_IDX_MASK 0x3fff 132 #define APLIC_TARGET_GUEST_IDX_SHIFT 12 133 #define APLIC_TARGET_GUEST_IDX_MASK 0x3f 134 #define APLIC_TARGET_IPRIO_MASK 0xff 135 #define APLIC_TARGET_EIID_MASK 0x7ff 136 137 #define APLIC_IDC_BASE 0x4000 138 #define APLIC_IDC_SIZE 32 139 140 #define APLIC_IDC_IDELIVERY 0x00 141 142 #define APLIC_IDC_IFORCE 0x04 143 144 #define APLIC_IDC_ITHRESHOLD 0x08 145 146 #define APLIC_IDC_TOPI 0x18 147 #define APLIC_IDC_TOPI_ID_SHIFT 16 148 #define APLIC_IDC_TOPI_ID_MASK 0x3ff 149 #define APLIC_IDC_TOPI_PRIO_MASK 0xff 150 151 #define APLIC_IDC_CLAIMI 0x1c 152 153 /* 154 * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use 155 * APLIC Wired. 156 */ 157 static bool is_kvm_aia(bool msimode) 158 { 159 return kvm_irqchip_in_kernel() && msimode; 160 } 161 162 static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic, 163 uint32_t word) 164 { 165 uint32_t i, irq, ret = 0; 166 167 for (i = 0; i < 32; i++) { 168 irq = word * 32 + i; 169 if (!irq || aplic->num_irqs <= irq) { 170 continue; 171 } 172 173 ret |= ((aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0) << i; 174 } 175 176 return ret; 177 } 178 179 static uint32_t riscv_aplic_read_pending_word(RISCVAPLICState *aplic, 180 uint32_t word) 181 { 182 uint32_t i, irq, ret = 0; 183 184 for (i = 0; i < 32; i++) { 185 irq = word * 32 + i; 186 if (!irq || aplic->num_irqs <= irq) { 187 continue; 188 } 189 190 ret |= ((aplic->state[irq] & APLIC_ISTATE_PENDING) ? 1 : 0) << i; 191 } 192 193 return ret; 194 } 195 196 static void riscv_aplic_set_pending_raw(RISCVAPLICState *aplic, 197 uint32_t irq, bool pending) 198 { 199 if (pending) { 200 aplic->state[irq] |= APLIC_ISTATE_PENDING; 201 } else { 202 aplic->state[irq] &= ~APLIC_ISTATE_PENDING; 203 } 204 } 205 206 static void riscv_aplic_set_pending(RISCVAPLICState *aplic, 207 uint32_t irq, bool pending) 208 { 209 uint32_t sourcecfg, sm; 210 211 if ((irq <= 0) || (aplic->num_irqs <= irq)) { 212 return; 213 } 214 215 sourcecfg = aplic->sourcecfg[irq]; 216 if (sourcecfg & APLIC_SOURCECFG_D) { 217 return; 218 } 219 220 sm = sourcecfg & APLIC_SOURCECFG_SM_MASK; 221 if (sm == APLIC_SOURCECFG_SM_INACTIVE) { 222 return; 223 } 224 225 if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) || 226 (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) { 227 if (!aplic->msimode || (aplic->msimode && !pending)) { 228 return; 229 } 230 if ((aplic->state[irq] & APLIC_ISTATE_INPUT) && 231 (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) { 232 return; 233 } 234 if (!(aplic->state[irq] & APLIC_ISTATE_INPUT) && 235 (sm == APLIC_SOURCECFG_SM_LEVEL_HIGH)) { 236 return; 237 } 238 } 239 240 riscv_aplic_set_pending_raw(aplic, irq, pending); 241 } 242 243 static void riscv_aplic_set_pending_word(RISCVAPLICState *aplic, 244 uint32_t word, uint32_t value, 245 bool pending) 246 { 247 uint32_t i, irq; 248 249 for (i = 0; i < 32; i++) { 250 irq = word * 32 + i; 251 if (!irq || aplic->num_irqs <= irq) { 252 continue; 253 } 254 255 if (value & (1U << i)) { 256 riscv_aplic_set_pending(aplic, irq, pending); 257 } 258 } 259 } 260 261 static uint32_t riscv_aplic_read_enabled_word(RISCVAPLICState *aplic, 262 int word) 263 { 264 uint32_t i, irq, ret = 0; 265 266 for (i = 0; i < 32; i++) { 267 irq = word * 32 + i; 268 if (!irq || aplic->num_irqs <= irq) { 269 continue; 270 } 271 272 ret |= ((aplic->state[irq] & APLIC_ISTATE_ENABLED) ? 1 : 0) << i; 273 } 274 275 return ret; 276 } 277 278 static void riscv_aplic_set_enabled_raw(RISCVAPLICState *aplic, 279 uint32_t irq, bool enabled) 280 { 281 if (enabled) { 282 aplic->state[irq] |= APLIC_ISTATE_ENABLED; 283 } else { 284 aplic->state[irq] &= ~APLIC_ISTATE_ENABLED; 285 } 286 } 287 288 static void riscv_aplic_set_enabled(RISCVAPLICState *aplic, 289 uint32_t irq, bool enabled) 290 { 291 uint32_t sourcecfg, sm; 292 293 if ((irq <= 0) || (aplic->num_irqs <= irq)) { 294 return; 295 } 296 297 sourcecfg = aplic->sourcecfg[irq]; 298 if (sourcecfg & APLIC_SOURCECFG_D) { 299 return; 300 } 301 302 sm = sourcecfg & APLIC_SOURCECFG_SM_MASK; 303 if (sm == APLIC_SOURCECFG_SM_INACTIVE) { 304 return; 305 } 306 307 riscv_aplic_set_enabled_raw(aplic, irq, enabled); 308 } 309 310 static void riscv_aplic_set_enabled_word(RISCVAPLICState *aplic, 311 uint32_t word, uint32_t value, 312 bool enabled) 313 { 314 uint32_t i, irq; 315 316 for (i = 0; i < 32; i++) { 317 irq = word * 32 + i; 318 if (!irq || aplic->num_irqs <= irq) { 319 continue; 320 } 321 322 if (value & (1U << i)) { 323 riscv_aplic_set_enabled(aplic, irq, enabled); 324 } 325 } 326 } 327 328 static void riscv_aplic_msi_send(RISCVAPLICState *aplic, 329 uint32_t hart_idx, uint32_t guest_idx, 330 uint32_t eiid) 331 { 332 uint64_t addr; 333 MemTxResult result; 334 RISCVAPLICState *aplic_m; 335 uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH; 336 337 aplic_m = aplic; 338 while (aplic_m && !aplic_m->mmode) { 339 aplic_m = aplic_m->parent; 340 } 341 if (!aplic_m) { 342 qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n", 343 __func__); 344 return; 345 } 346 347 if (aplic->mmode) { 348 msicfgaddr = aplic_m->mmsicfgaddr; 349 msicfgaddrH = aplic_m->mmsicfgaddrH; 350 } else { 351 msicfgaddr = aplic_m->smsicfgaddr; 352 msicfgaddrH = aplic_m->smsicfgaddrH; 353 } 354 355 lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) & 356 APLIC_xMSICFGADDRH_LHXS_MASK; 357 lhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXW_SHIFT) & 358 APLIC_xMSICFGADDRH_LHXW_MASK; 359 hhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXS_SHIFT) & 360 APLIC_xMSICFGADDRH_HHXS_MASK; 361 hhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXW_SHIFT) & 362 APLIC_xMSICFGADDRH_HHXW_MASK; 363 364 group_idx = hart_idx >> lhxw; 365 hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw); 366 367 addr = msicfgaddr; 368 addr |= ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) << 32; 369 addr |= ((uint64_t)(group_idx & APLIC_xMSICFGADDR_PPN_HHX_MASK(hhxw))) << 370 APLIC_xMSICFGADDR_PPN_HHX_SHIFT(hhxs); 371 addr |= ((uint64_t)(hart_idx & APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw))) << 372 APLIC_xMSICFGADDR_PPN_LHX_SHIFT(lhxs); 373 addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs)); 374 addr <<= APLIC_xMSICFGADDR_PPN_SHIFT; 375 376 address_space_stl_le(&address_space_memory, addr, 377 eiid, MEMTXATTRS_UNSPECIFIED, &result); 378 if (result != MEMTX_OK) { 379 qemu_log_mask(LOG_GUEST_ERROR, "%s: MSI write failed for " 380 "hart_index=%d guest_index=%d eiid=%d\n", 381 __func__, hart_idx, guest_idx, eiid); 382 } 383 } 384 385 static void riscv_aplic_msi_irq_update(RISCVAPLICState *aplic, uint32_t irq) 386 { 387 uint32_t hart_idx, guest_idx, eiid; 388 389 if (!aplic->msimode || (aplic->num_irqs <= irq) || 390 !(aplic->domaincfg & APLIC_DOMAINCFG_IE)) { 391 return; 392 } 393 394 if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) != APLIC_ISTATE_ENPEND) { 395 return; 396 } 397 398 riscv_aplic_set_pending_raw(aplic, irq, false); 399 400 hart_idx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT; 401 hart_idx &= APLIC_TARGET_HART_IDX_MASK; 402 if (aplic->mmode) { 403 /* M-level APLIC ignores guest_index */ 404 guest_idx = 0; 405 } else { 406 guest_idx = aplic->target[irq] >> APLIC_TARGET_GUEST_IDX_SHIFT; 407 guest_idx &= APLIC_TARGET_GUEST_IDX_MASK; 408 } 409 eiid = aplic->target[irq] & APLIC_TARGET_EIID_MASK; 410 riscv_aplic_msi_send(aplic, hart_idx, guest_idx, eiid); 411 } 412 413 static uint32_t riscv_aplic_idc_topi(RISCVAPLICState *aplic, uint32_t idc) 414 { 415 uint32_t best_irq, best_iprio; 416 uint32_t irq, iprio, ihartidx, ithres; 417 418 if (aplic->num_harts <= idc) { 419 return 0; 420 } 421 422 ithres = aplic->ithreshold[idc]; 423 best_irq = best_iprio = UINT32_MAX; 424 for (irq = 1; irq < aplic->num_irqs; irq++) { 425 if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) != 426 APLIC_ISTATE_ENPEND) { 427 continue; 428 } 429 430 ihartidx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT; 431 ihartidx &= APLIC_TARGET_HART_IDX_MASK; 432 if (ihartidx != idc) { 433 continue; 434 } 435 436 iprio = aplic->target[irq] & aplic->iprio_mask; 437 if (ithres && iprio >= ithres) { 438 continue; 439 } 440 441 if (iprio < best_iprio) { 442 best_irq = irq; 443 best_iprio = iprio; 444 } 445 } 446 447 if (best_irq < aplic->num_irqs && best_iprio <= aplic->iprio_mask) { 448 return (best_irq << APLIC_IDC_TOPI_ID_SHIFT) | best_iprio; 449 } 450 451 return 0; 452 } 453 454 static void riscv_aplic_idc_update(RISCVAPLICState *aplic, uint32_t idc) 455 { 456 uint32_t topi; 457 458 if (aplic->msimode || aplic->num_harts <= idc) { 459 return; 460 } 461 462 topi = riscv_aplic_idc_topi(aplic, idc); 463 if ((aplic->domaincfg & APLIC_DOMAINCFG_IE) && 464 aplic->idelivery[idc] && 465 (aplic->iforce[idc] || topi)) { 466 qemu_irq_raise(aplic->external_irqs[idc]); 467 } else { 468 qemu_irq_lower(aplic->external_irqs[idc]); 469 } 470 } 471 472 static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc) 473 { 474 uint32_t irq, state, sm, topi = riscv_aplic_idc_topi(aplic, idc); 475 476 if (!topi) { 477 aplic->iforce[idc] = 0; 478 return 0; 479 } 480 481 irq = (topi >> APLIC_IDC_TOPI_ID_SHIFT) & APLIC_IDC_TOPI_ID_MASK; 482 sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK; 483 state = aplic->state[irq]; 484 riscv_aplic_set_pending_raw(aplic, irq, false); 485 if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) && 486 (state & APLIC_ISTATE_INPUT)) { 487 riscv_aplic_set_pending_raw(aplic, irq, true); 488 } else if ((sm == APLIC_SOURCECFG_SM_LEVEL_LOW) && 489 !(state & APLIC_ISTATE_INPUT)) { 490 riscv_aplic_set_pending_raw(aplic, irq, true); 491 } 492 riscv_aplic_idc_update(aplic, idc); 493 494 return topi; 495 } 496 497 static void riscv_aplic_request(void *opaque, int irq, int level) 498 { 499 bool update = false; 500 RISCVAPLICState *aplic = opaque; 501 uint32_t sourcecfg, childidx, state, idc; 502 503 assert((0 < irq) && (irq < aplic->num_irqs)); 504 505 sourcecfg = aplic->sourcecfg[irq]; 506 if (sourcecfg & APLIC_SOURCECFG_D) { 507 childidx = sourcecfg & APLIC_SOURCECFG_CHILDIDX_MASK; 508 if (childidx < aplic->num_children) { 509 riscv_aplic_request(aplic->children[childidx], irq, level); 510 } 511 return; 512 } 513 514 state = aplic->state[irq]; 515 switch (sourcecfg & APLIC_SOURCECFG_SM_MASK) { 516 case APLIC_SOURCECFG_SM_EDGE_RISE: 517 if ((level > 0) && !(state & APLIC_ISTATE_INPUT) && 518 !(state & APLIC_ISTATE_PENDING)) { 519 riscv_aplic_set_pending_raw(aplic, irq, true); 520 update = true; 521 } 522 break; 523 case APLIC_SOURCECFG_SM_EDGE_FALL: 524 if ((level <= 0) && (state & APLIC_ISTATE_INPUT) && 525 !(state & APLIC_ISTATE_PENDING)) { 526 riscv_aplic_set_pending_raw(aplic, irq, true); 527 update = true; 528 } 529 break; 530 case APLIC_SOURCECFG_SM_LEVEL_HIGH: 531 if ((level > 0) && !(state & APLIC_ISTATE_PENDING)) { 532 riscv_aplic_set_pending_raw(aplic, irq, true); 533 update = true; 534 } 535 break; 536 case APLIC_SOURCECFG_SM_LEVEL_LOW: 537 if ((level <= 0) && !(state & APLIC_ISTATE_PENDING)) { 538 riscv_aplic_set_pending_raw(aplic, irq, true); 539 update = true; 540 } 541 break; 542 default: 543 break; 544 } 545 546 if (level <= 0) { 547 aplic->state[irq] &= ~APLIC_ISTATE_INPUT; 548 } else { 549 aplic->state[irq] |= APLIC_ISTATE_INPUT; 550 } 551 552 if (update) { 553 if (aplic->msimode) { 554 riscv_aplic_msi_irq_update(aplic, irq); 555 } else { 556 idc = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT; 557 idc &= APLIC_TARGET_HART_IDX_MASK; 558 riscv_aplic_idc_update(aplic, idc); 559 } 560 } 561 } 562 563 static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size) 564 { 565 uint32_t irq, word, idc; 566 RISCVAPLICState *aplic = opaque; 567 568 /* Reads must be 4 byte words */ 569 if ((addr & 0x3) != 0) { 570 goto err; 571 } 572 573 if (addr == APLIC_DOMAINCFG) { 574 return APLIC_DOMAINCFG_RDONLY | aplic->domaincfg | 575 (aplic->msimode ? APLIC_DOMAINCFG_DM : 0); 576 } else if ((APLIC_SOURCECFG_BASE <= addr) && 577 (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) { 578 irq = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1; 579 return aplic->sourcecfg[irq]; 580 } else if (aplic->mmode && aplic->msimode && 581 (addr == APLIC_MMSICFGADDR)) { 582 return aplic->mmsicfgaddr; 583 } else if (aplic->mmode && aplic->msimode && 584 (addr == APLIC_MMSICFGADDRH)) { 585 return aplic->mmsicfgaddrH; 586 } else if (aplic->mmode && aplic->msimode && 587 (addr == APLIC_SMSICFGADDR)) { 588 /* 589 * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if: 590 * (a) the interrupt domain is at machine level 591 * (b) the domain's harts implement supervisor mode 592 * (c) the domain has one or more child supervisor-level domains 593 * that support MSI delivery mode (domaincfg.DM is not read- 594 * only zero in at least one of the supervisor-level child 595 * domains). 596 */ 597 return (aplic->num_children) ? aplic->smsicfgaddr : 0; 598 } else if (aplic->mmode && aplic->msimode && 599 (addr == APLIC_SMSICFGADDRH)) { 600 return (aplic->num_children) ? aplic->smsicfgaddrH : 0; 601 } else if ((APLIC_SETIP_BASE <= addr) && 602 (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) { 603 word = (addr - APLIC_SETIP_BASE) >> 2; 604 return riscv_aplic_read_pending_word(aplic, word); 605 } else if (addr == APLIC_SETIPNUM) { 606 return 0; 607 } else if ((APLIC_CLRIP_BASE <= addr) && 608 (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) { 609 word = (addr - APLIC_CLRIP_BASE) >> 2; 610 return riscv_aplic_read_input_word(aplic, word); 611 } else if (addr == APLIC_CLRIPNUM) { 612 return 0; 613 } else if ((APLIC_SETIE_BASE <= addr) && 614 (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) { 615 word = (addr - APLIC_SETIE_BASE) >> 2; 616 return riscv_aplic_read_enabled_word(aplic, word); 617 } else if (addr == APLIC_SETIENUM) { 618 return 0; 619 } else if ((APLIC_CLRIE_BASE <= addr) && 620 (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) { 621 return 0; 622 } else if (addr == APLIC_CLRIENUM) { 623 return 0; 624 } else if (addr == APLIC_SETIPNUM_LE) { 625 return 0; 626 } else if (addr == APLIC_SETIPNUM_BE) { 627 return 0; 628 } else if (addr == APLIC_GENMSI) { 629 return (aplic->msimode) ? aplic->genmsi : 0; 630 } else if ((APLIC_TARGET_BASE <= addr) && 631 (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { 632 irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1; 633 return aplic->target[irq]; 634 } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) && 635 (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) { 636 idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE; 637 switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) { 638 case APLIC_IDC_IDELIVERY: 639 return aplic->idelivery[idc]; 640 case APLIC_IDC_IFORCE: 641 return aplic->iforce[idc]; 642 case APLIC_IDC_ITHRESHOLD: 643 return aplic->ithreshold[idc]; 644 case APLIC_IDC_TOPI: 645 return riscv_aplic_idc_topi(aplic, idc); 646 case APLIC_IDC_CLAIMI: 647 return riscv_aplic_idc_claimi(aplic, idc); 648 default: 649 goto err; 650 }; 651 } 652 653 err: 654 qemu_log_mask(LOG_GUEST_ERROR, 655 "%s: Invalid register read 0x%" HWADDR_PRIx "\n", 656 __func__, addr); 657 return 0; 658 } 659 660 static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value, 661 unsigned size) 662 { 663 RISCVAPLICState *aplic = opaque; 664 uint32_t irq, word, idc = UINT32_MAX; 665 666 /* Writes must be 4 byte words */ 667 if ((addr & 0x3) != 0) { 668 goto err; 669 } 670 671 if (addr == APLIC_DOMAINCFG) { 672 /* Only IE bit writable at the moment */ 673 value &= APLIC_DOMAINCFG_IE; 674 aplic->domaincfg = value; 675 } else if ((APLIC_SOURCECFG_BASE <= addr) && 676 (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) { 677 irq = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1; 678 if (!aplic->num_children && (value & APLIC_SOURCECFG_D)) { 679 value = 0; 680 } 681 if (value & APLIC_SOURCECFG_D) { 682 value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_CHILDIDX_MASK); 683 } else { 684 value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_SM_MASK); 685 } 686 aplic->sourcecfg[irq] = value; 687 if ((aplic->sourcecfg[irq] & APLIC_SOURCECFG_D) || 688 (aplic->sourcecfg[irq] == 0)) { 689 riscv_aplic_set_pending_raw(aplic, irq, false); 690 riscv_aplic_set_enabled_raw(aplic, irq, false); 691 } 692 } else if (aplic->mmode && aplic->msimode && 693 (addr == APLIC_MMSICFGADDR)) { 694 if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { 695 aplic->mmsicfgaddr = value; 696 } 697 } else if (aplic->mmode && aplic->msimode && 698 (addr == APLIC_MMSICFGADDRH)) { 699 if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { 700 aplic->mmsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK; 701 } 702 } else if (aplic->mmode && aplic->msimode && 703 (addr == APLIC_SMSICFGADDR)) { 704 /* 705 * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if: 706 * (a) the interrupt domain is at machine level 707 * (b) the domain's harts implement supervisor mode 708 * (c) the domain has one or more child supervisor-level domains 709 * that support MSI delivery mode (domaincfg.DM is not read- 710 * only zero in at least one of the supervisor-level child 711 * domains). 712 */ 713 if (aplic->num_children && 714 !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { 715 aplic->smsicfgaddr = value; 716 } 717 } else if (aplic->mmode && aplic->msimode && 718 (addr == APLIC_SMSICFGADDRH)) { 719 if (aplic->num_children && 720 !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { 721 aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK; 722 } 723 } else if ((APLIC_SETIP_BASE <= addr) && 724 (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) { 725 word = (addr - APLIC_SETIP_BASE) >> 2; 726 riscv_aplic_set_pending_word(aplic, word, value, true); 727 } else if (addr == APLIC_SETIPNUM) { 728 riscv_aplic_set_pending(aplic, value, true); 729 } else if ((APLIC_CLRIP_BASE <= addr) && 730 (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) { 731 word = (addr - APLIC_CLRIP_BASE) >> 2; 732 riscv_aplic_set_pending_word(aplic, word, value, false); 733 } else if (addr == APLIC_CLRIPNUM) { 734 riscv_aplic_set_pending(aplic, value, false); 735 } else if ((APLIC_SETIE_BASE <= addr) && 736 (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) { 737 word = (addr - APLIC_SETIE_BASE) >> 2; 738 riscv_aplic_set_enabled_word(aplic, word, value, true); 739 } else if (addr == APLIC_SETIENUM) { 740 riscv_aplic_set_enabled(aplic, value, true); 741 } else if ((APLIC_CLRIE_BASE <= addr) && 742 (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) { 743 word = (addr - APLIC_CLRIE_BASE) >> 2; 744 riscv_aplic_set_enabled_word(aplic, word, value, false); 745 } else if (addr == APLIC_CLRIENUM) { 746 riscv_aplic_set_enabled(aplic, value, false); 747 } else if (addr == APLIC_SETIPNUM_LE) { 748 riscv_aplic_set_pending(aplic, value, true); 749 } else if (addr == APLIC_SETIPNUM_BE) { 750 riscv_aplic_set_pending(aplic, bswap32(value), true); 751 } else if (addr == APLIC_GENMSI) { 752 if (aplic->msimode) { 753 aplic->genmsi = value & ~(APLIC_TARGET_GUEST_IDX_MASK << 754 APLIC_TARGET_GUEST_IDX_SHIFT); 755 riscv_aplic_msi_send(aplic, 756 value >> APLIC_TARGET_HART_IDX_SHIFT, 757 0, 758 value & APLIC_TARGET_EIID_MASK); 759 } 760 } else if ((APLIC_TARGET_BASE <= addr) && 761 (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { 762 irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1; 763 if (aplic->msimode) { 764 aplic->target[irq] = value; 765 } else { 766 aplic->target[irq] = (value & ~APLIC_TARGET_IPRIO_MASK) | 767 ((value & aplic->iprio_mask) ? 768 (value & aplic->iprio_mask) : 1); 769 } 770 } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) && 771 (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) { 772 idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE; 773 switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) { 774 case APLIC_IDC_IDELIVERY: 775 aplic->idelivery[idc] = value & 0x1; 776 break; 777 case APLIC_IDC_IFORCE: 778 aplic->iforce[idc] = value & 0x1; 779 break; 780 case APLIC_IDC_ITHRESHOLD: 781 aplic->ithreshold[idc] = value & aplic->iprio_mask; 782 break; 783 default: 784 goto err; 785 }; 786 } else { 787 goto err; 788 } 789 790 if (aplic->msimode) { 791 for (irq = 1; irq < aplic->num_irqs; irq++) { 792 riscv_aplic_msi_irq_update(aplic, irq); 793 } 794 } else { 795 if (idc == UINT32_MAX) { 796 for (idc = 0; idc < aplic->num_harts; idc++) { 797 riscv_aplic_idc_update(aplic, idc); 798 } 799 } else { 800 riscv_aplic_idc_update(aplic, idc); 801 } 802 } 803 804 return; 805 806 err: 807 qemu_log_mask(LOG_GUEST_ERROR, 808 "%s: Invalid register write 0x%" HWADDR_PRIx "\n", 809 __func__, addr); 810 } 811 812 static const MemoryRegionOps riscv_aplic_ops = { 813 .read = riscv_aplic_read, 814 .write = riscv_aplic_write, 815 .endianness = DEVICE_LITTLE_ENDIAN, 816 .valid = { 817 .min_access_size = 4, 818 .max_access_size = 4 819 } 820 }; 821 822 static void riscv_aplic_realize(DeviceState *dev, Error **errp) 823 { 824 uint32_t i; 825 RISCVAPLICState *aplic = RISCV_APLIC(dev); 826 827 if (!is_kvm_aia(aplic->msimode)) { 828 aplic->bitfield_words = (aplic->num_irqs + 31) >> 5; 829 aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs); 830 aplic->state = g_new0(uint32_t, aplic->num_irqs); 831 aplic->target = g_new0(uint32_t, aplic->num_irqs); 832 if (!aplic->msimode) { 833 for (i = 0; i < aplic->num_irqs; i++) { 834 aplic->target[i] = 1; 835 } 836 } 837 aplic->idelivery = g_new0(uint32_t, aplic->num_harts); 838 aplic->iforce = g_new0(uint32_t, aplic->num_harts); 839 aplic->ithreshold = g_new0(uint32_t, aplic->num_harts); 840 841 memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, 842 aplic, TYPE_RISCV_APLIC, aplic->aperture_size); 843 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); 844 } 845 846 /* 847 * Only root APLICs have hardware IRQ lines. All non-root APLICs 848 * have IRQ lines delegated by their parent APLIC. 849 */ 850 if (!aplic->parent) { 851 if (kvm_enabled() && is_kvm_aia(aplic->msimode)) { 852 qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs); 853 } else { 854 qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); 855 } 856 } 857 858 /* Create output IRQ lines for non-MSI mode */ 859 if (!aplic->msimode) { 860 aplic->external_irqs = g_malloc(sizeof(qemu_irq) * aplic->num_harts); 861 qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts); 862 863 /* Claim the CPU interrupt to be triggered by this APLIC */ 864 for (i = 0; i < aplic->num_harts; i++) { 865 RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i)); 866 if (riscv_cpu_claim_interrupts(cpu, 867 (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { 868 error_report("%s already claimed", 869 (aplic->mmode) ? "MEIP" : "SEIP"); 870 exit(1); 871 } 872 } 873 } 874 875 msi_nonbroken = true; 876 } 877 878 static Property riscv_aplic_properties[] = { 879 DEFINE_PROP_UINT32("aperture-size", RISCVAPLICState, aperture_size, 0), 880 DEFINE_PROP_UINT32("hartid-base", RISCVAPLICState, hartid_base, 0), 881 DEFINE_PROP_UINT32("num-harts", RISCVAPLICState, num_harts, 0), 882 DEFINE_PROP_UINT32("iprio-mask", RISCVAPLICState, iprio_mask, 0), 883 DEFINE_PROP_UINT32("num-irqs", RISCVAPLICState, num_irqs, 0), 884 DEFINE_PROP_BOOL("msimode", RISCVAPLICState, msimode, 0), 885 DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0), 886 DEFINE_PROP_END_OF_LIST(), 887 }; 888 889 static const VMStateDescription vmstate_riscv_aplic = { 890 .name = "riscv_aplic", 891 .version_id = 1, 892 .minimum_version_id = 1, 893 .fields = (const VMStateField[]) { 894 VMSTATE_UINT32(domaincfg, RISCVAPLICState), 895 VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState), 896 VMSTATE_UINT32(mmsicfgaddrH, RISCVAPLICState), 897 VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState), 898 VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState), 899 VMSTATE_UINT32(genmsi, RISCVAPLICState), 900 VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState, 901 num_irqs, 0, 902 vmstate_info_uint32, uint32_t), 903 VMSTATE_VARRAY_UINT32(state, RISCVAPLICState, 904 num_irqs, 0, 905 vmstate_info_uint32, uint32_t), 906 VMSTATE_VARRAY_UINT32(target, RISCVAPLICState, 907 num_irqs, 0, 908 vmstate_info_uint32, uint32_t), 909 VMSTATE_VARRAY_UINT32(idelivery, RISCVAPLICState, 910 num_harts, 0, 911 vmstate_info_uint32, uint32_t), 912 VMSTATE_VARRAY_UINT32(iforce, RISCVAPLICState, 913 num_harts, 0, 914 vmstate_info_uint32, uint32_t), 915 VMSTATE_VARRAY_UINT32(ithreshold, RISCVAPLICState, 916 num_harts, 0, 917 vmstate_info_uint32, uint32_t), 918 VMSTATE_END_OF_LIST() 919 } 920 }; 921 922 static void riscv_aplic_class_init(ObjectClass *klass, void *data) 923 { 924 DeviceClass *dc = DEVICE_CLASS(klass); 925 926 device_class_set_props(dc, riscv_aplic_properties); 927 dc->realize = riscv_aplic_realize; 928 dc->vmsd = &vmstate_riscv_aplic; 929 } 930 931 static const TypeInfo riscv_aplic_info = { 932 .name = TYPE_RISCV_APLIC, 933 .parent = TYPE_SYS_BUS_DEVICE, 934 .instance_size = sizeof(RISCVAPLICState), 935 .class_init = riscv_aplic_class_init, 936 }; 937 938 static void riscv_aplic_register_types(void) 939 { 940 type_register_static(&riscv_aplic_info); 941 } 942 943 type_init(riscv_aplic_register_types) 944 945 /* 946 * Add a APLIC device to another APLIC device as child for 947 * interrupt delegation. 948 */ 949 void riscv_aplic_add_child(DeviceState *parent, DeviceState *child) 950 { 951 RISCVAPLICState *caplic, *paplic; 952 953 assert(parent && child); 954 caplic = RISCV_APLIC(child); 955 paplic = RISCV_APLIC(parent); 956 957 assert(paplic->num_irqs == caplic->num_irqs); 958 assert(paplic->num_children <= QEMU_APLIC_MAX_CHILDREN); 959 960 caplic->parent = paplic; 961 paplic->children[paplic->num_children] = caplic; 962 paplic->num_children++; 963 } 964 965 /* 966 * Create APLIC device. 967 */ 968 DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, 969 uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, 970 uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent) 971 { 972 DeviceState *dev = qdev_new(TYPE_RISCV_APLIC); 973 uint32_t i; 974 975 assert(num_harts < APLIC_MAX_IDC); 976 assert((APLIC_IDC_BASE + (num_harts * APLIC_IDC_SIZE)) <= size); 977 assert(num_sources < APLIC_MAX_SOURCE); 978 assert(APLIC_MIN_IPRIO_BITS <= iprio_bits); 979 assert(iprio_bits <= APLIC_MAX_IPRIO_BITS); 980 981 qdev_prop_set_uint32(dev, "aperture-size", size); 982 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); 983 qdev_prop_set_uint32(dev, "num-harts", num_harts); 984 qdev_prop_set_uint32(dev, "iprio-mask", ((1U << iprio_bits) - 1)); 985 qdev_prop_set_uint32(dev, "num-irqs", num_sources + 1); 986 qdev_prop_set_bit(dev, "msimode", msimode); 987 qdev_prop_set_bit(dev, "mmode", mmode); 988 989 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 990 991 if (!is_kvm_aia(msimode)) { 992 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 993 } 994 995 if (parent) { 996 riscv_aplic_add_child(parent, dev); 997 } 998 999 if (!msimode) { 1000 for (i = 0; i < num_harts; i++) { 1001 CPUState *cpu = cpu_by_arch_id(hartid_base + i); 1002 1003 qdev_connect_gpio_out_named(dev, NULL, i, 1004 qdev_get_gpio_in(DEVICE(cpu), 1005 (mmode) ? IRQ_M_EXT : IRQ_S_EXT)); 1006 } 1007 } 1008 1009 return dev; 1010 } 1011