1 /* 2 * RISC-V APLIC (Advanced Platform Level Interrupt Controller) 3 * 4 * Copyright (c) 2021 Western Digital Corporation or its affiliates. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qapi/error.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "qemu/error-report.h" 24 #include "qemu/bswap.h" 25 #include "exec/address-spaces.h" 26 #include "hw/sysbus.h" 27 #include "hw/pci/msi.h" 28 #include "hw/boards.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/intc/riscv_aplic.h" 31 #include "hw/irq.h" 32 #include "target/riscv/cpu.h" 33 #include "sysemu/sysemu.h" 34 #include "sysemu/kvm.h" 35 #include "kvm/kvm_riscv.h" 36 #include "migration/vmstate.h" 37 38 #define APLIC_MAX_IDC (1UL << 14) 39 #define APLIC_MAX_SOURCE 1024 40 #define APLIC_MIN_IPRIO_BITS 1 41 #define APLIC_MAX_IPRIO_BITS 8 42 #define APLIC_MAX_CHILDREN 1024 43 44 #define APLIC_DOMAINCFG 0x0000 45 #define APLIC_DOMAINCFG_RDONLY 0x80000000 46 #define APLIC_DOMAINCFG_IE (1 << 8) 47 #define APLIC_DOMAINCFG_DM (1 << 2) 48 #define APLIC_DOMAINCFG_BE (1 << 0) 49 50 #define APLIC_SOURCECFG_BASE 0x0004 51 #define APLIC_SOURCECFG_D (1 << 10) 52 #define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff 53 #define APLIC_SOURCECFG_SM_MASK 0x00000007 54 #define APLIC_SOURCECFG_SM_INACTIVE 0x0 55 #define APLIC_SOURCECFG_SM_DETACH 0x1 56 #define APLIC_SOURCECFG_SM_EDGE_RISE 0x4 57 #define APLIC_SOURCECFG_SM_EDGE_FALL 0x5 58 #define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 59 #define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 60 61 #define APLIC_MMSICFGADDR 0x1bc0 62 #define APLIC_MMSICFGADDRH 0x1bc4 63 #define APLIC_SMSICFGADDR 0x1bc8 64 #define APLIC_SMSICFGADDRH 0x1bcc 65 66 #define APLIC_xMSICFGADDRH_L (1UL << 31) 67 #define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f 68 #define APLIC_xMSICFGADDRH_HHXS_SHIFT 24 69 #define APLIC_xMSICFGADDRH_LHXS_MASK 0x7 70 #define APLIC_xMSICFGADDRH_LHXS_SHIFT 20 71 #define APLIC_xMSICFGADDRH_HHXW_MASK 0x7 72 #define APLIC_xMSICFGADDRH_HHXW_SHIFT 16 73 #define APLIC_xMSICFGADDRH_LHXW_MASK 0xf 74 #define APLIC_xMSICFGADDRH_LHXW_SHIFT 12 75 #define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff 76 77 #define APLIC_xMSICFGADDR_PPN_SHIFT 12 78 79 #define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \ 80 ((1UL << (__lhxs)) - 1) 81 82 #define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \ 83 ((1UL << (__lhxw)) - 1) 84 #define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \ 85 ((__lhxs)) 86 #define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \ 87 (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \ 88 APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs)) 89 90 #define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \ 91 ((1UL << (__hhxw)) - 1) 92 #define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \ 93 ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT) 94 #define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \ 95 (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \ 96 APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs)) 97 98 #define APLIC_xMSICFGADDRH_VALID_MASK \ 99 (APLIC_xMSICFGADDRH_L | \ 100 (APLIC_xMSICFGADDRH_HHXS_MASK << APLIC_xMSICFGADDRH_HHXS_SHIFT) | \ 101 (APLIC_xMSICFGADDRH_LHXS_MASK << APLIC_xMSICFGADDRH_LHXS_SHIFT) | \ 102 (APLIC_xMSICFGADDRH_HHXW_MASK << APLIC_xMSICFGADDRH_HHXW_SHIFT) | \ 103 (APLIC_xMSICFGADDRH_LHXW_MASK << APLIC_xMSICFGADDRH_LHXW_SHIFT) | \ 104 APLIC_xMSICFGADDRH_BAPPN_MASK) 105 106 #define APLIC_SETIP_BASE 0x1c00 107 #define APLIC_SETIPNUM 0x1cdc 108 109 #define APLIC_CLRIP_BASE 0x1d00 110 #define APLIC_CLRIPNUM 0x1ddc 111 112 #define APLIC_SETIE_BASE 0x1e00 113 #define APLIC_SETIENUM 0x1edc 114 115 #define APLIC_CLRIE_BASE 0x1f00 116 #define APLIC_CLRIENUM 0x1fdc 117 118 #define APLIC_SETIPNUM_LE 0x2000 119 #define APLIC_SETIPNUM_BE 0x2004 120 121 #define APLIC_ISTATE_PENDING (1U << 0) 122 #define APLIC_ISTATE_ENABLED (1U << 1) 123 #define APLIC_ISTATE_ENPEND (APLIC_ISTATE_ENABLED | \ 124 APLIC_ISTATE_PENDING) 125 #define APLIC_ISTATE_INPUT (1U << 8) 126 127 #define APLIC_GENMSI 0x3000 128 129 #define APLIC_TARGET_BASE 0x3004 130 #define APLIC_TARGET_HART_IDX_SHIFT 18 131 #define APLIC_TARGET_HART_IDX_MASK 0x3fff 132 #define APLIC_TARGET_GUEST_IDX_SHIFT 12 133 #define APLIC_TARGET_GUEST_IDX_MASK 0x3f 134 #define APLIC_TARGET_IPRIO_MASK 0xff 135 #define APLIC_TARGET_EIID_MASK 0x7ff 136 137 #define APLIC_IDC_BASE 0x4000 138 #define APLIC_IDC_SIZE 32 139 140 #define APLIC_IDC_IDELIVERY 0x00 141 142 #define APLIC_IDC_IFORCE 0x04 143 144 #define APLIC_IDC_ITHRESHOLD 0x08 145 146 #define APLIC_IDC_TOPI 0x18 147 #define APLIC_IDC_TOPI_ID_SHIFT 16 148 #define APLIC_IDC_TOPI_ID_MASK 0x3ff 149 #define APLIC_IDC_TOPI_PRIO_MASK 0xff 150 151 #define APLIC_IDC_CLAIMI 0x1c 152 153 /* 154 * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use 155 * APLIC Wired. 156 */ 157 static bool is_kvm_aia(bool msimode) 158 { 159 return kvm_irqchip_in_kernel() && msimode; 160 } 161 162 static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic, 163 uint32_t word) 164 { 165 uint32_t i, irq, sourcecfg, sm, raw_input, irq_inverted, ret = 0; 166 167 for (i = 0; i < 32; i++) { 168 irq = word * 32 + i; 169 if (!irq || aplic->num_irqs <= irq) { 170 continue; 171 } 172 173 sourcecfg = aplic->sourcecfg[irq]; 174 if (sourcecfg & APLIC_SOURCECFG_D) { 175 continue; 176 } 177 178 sm = sourcecfg & APLIC_SOURCECFG_SM_MASK; 179 if (sm == APLIC_SOURCECFG_SM_INACTIVE) { 180 continue; 181 } 182 183 raw_input = (aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0; 184 irq_inverted = (sm == APLIC_SOURCECFG_SM_LEVEL_LOW || 185 sm == APLIC_SOURCECFG_SM_EDGE_FALL) ? 1 : 0; 186 ret |= (raw_input ^ irq_inverted) << i; 187 } 188 189 return ret; 190 } 191 192 static uint32_t riscv_aplic_read_pending_word(RISCVAPLICState *aplic, 193 uint32_t word) 194 { 195 uint32_t i, irq, ret = 0; 196 197 for (i = 0; i < 32; i++) { 198 irq = word * 32 + i; 199 if (!irq || aplic->num_irqs <= irq) { 200 continue; 201 } 202 203 ret |= ((aplic->state[irq] & APLIC_ISTATE_PENDING) ? 1 : 0) << i; 204 } 205 206 return ret; 207 } 208 209 static void riscv_aplic_set_pending_raw(RISCVAPLICState *aplic, 210 uint32_t irq, bool pending) 211 { 212 if (pending) { 213 aplic->state[irq] |= APLIC_ISTATE_PENDING; 214 } else { 215 aplic->state[irq] &= ~APLIC_ISTATE_PENDING; 216 } 217 } 218 219 static void riscv_aplic_set_pending(RISCVAPLICState *aplic, 220 uint32_t irq, bool pending) 221 { 222 uint32_t sourcecfg, sm; 223 224 if ((irq <= 0) || (aplic->num_irqs <= irq)) { 225 return; 226 } 227 228 sourcecfg = aplic->sourcecfg[irq]; 229 if (sourcecfg & APLIC_SOURCECFG_D) { 230 return; 231 } 232 233 sm = sourcecfg & APLIC_SOURCECFG_SM_MASK; 234 if (sm == APLIC_SOURCECFG_SM_INACTIVE) { 235 return; 236 } 237 238 if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) || 239 (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) { 240 if (!aplic->msimode || (aplic->msimode && !pending)) { 241 return; 242 } 243 if ((aplic->state[irq] & APLIC_ISTATE_INPUT) && 244 (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) { 245 return; 246 } 247 if (!(aplic->state[irq] & APLIC_ISTATE_INPUT) && 248 (sm == APLIC_SOURCECFG_SM_LEVEL_HIGH)) { 249 return; 250 } 251 } 252 253 riscv_aplic_set_pending_raw(aplic, irq, pending); 254 } 255 256 static void riscv_aplic_set_pending_word(RISCVAPLICState *aplic, 257 uint32_t word, uint32_t value, 258 bool pending) 259 { 260 uint32_t i, irq; 261 262 for (i = 0; i < 32; i++) { 263 irq = word * 32 + i; 264 if (!irq || aplic->num_irqs <= irq) { 265 continue; 266 } 267 268 if (value & (1U << i)) { 269 riscv_aplic_set_pending(aplic, irq, pending); 270 } 271 } 272 } 273 274 static uint32_t riscv_aplic_read_enabled_word(RISCVAPLICState *aplic, 275 int word) 276 { 277 uint32_t i, irq, ret = 0; 278 279 for (i = 0; i < 32; i++) { 280 irq = word * 32 + i; 281 if (!irq || aplic->num_irqs <= irq) { 282 continue; 283 } 284 285 ret |= ((aplic->state[irq] & APLIC_ISTATE_ENABLED) ? 1 : 0) << i; 286 } 287 288 return ret; 289 } 290 291 static void riscv_aplic_set_enabled_raw(RISCVAPLICState *aplic, 292 uint32_t irq, bool enabled) 293 { 294 if (enabled) { 295 aplic->state[irq] |= APLIC_ISTATE_ENABLED; 296 } else { 297 aplic->state[irq] &= ~APLIC_ISTATE_ENABLED; 298 } 299 } 300 301 static void riscv_aplic_set_enabled(RISCVAPLICState *aplic, 302 uint32_t irq, bool enabled) 303 { 304 uint32_t sourcecfg, sm; 305 306 if ((irq <= 0) || (aplic->num_irqs <= irq)) { 307 return; 308 } 309 310 sourcecfg = aplic->sourcecfg[irq]; 311 if (sourcecfg & APLIC_SOURCECFG_D) { 312 return; 313 } 314 315 sm = sourcecfg & APLIC_SOURCECFG_SM_MASK; 316 if (sm == APLIC_SOURCECFG_SM_INACTIVE) { 317 return; 318 } 319 320 riscv_aplic_set_enabled_raw(aplic, irq, enabled); 321 } 322 323 static void riscv_aplic_set_enabled_word(RISCVAPLICState *aplic, 324 uint32_t word, uint32_t value, 325 bool enabled) 326 { 327 uint32_t i, irq; 328 329 for (i = 0; i < 32; i++) { 330 irq = word * 32 + i; 331 if (!irq || aplic->num_irqs <= irq) { 332 continue; 333 } 334 335 if (value & (1U << i)) { 336 riscv_aplic_set_enabled(aplic, irq, enabled); 337 } 338 } 339 } 340 341 static void riscv_aplic_msi_send(RISCVAPLICState *aplic, 342 uint32_t hart_idx, uint32_t guest_idx, 343 uint32_t eiid) 344 { 345 uint64_t addr; 346 MemTxResult result; 347 RISCVAPLICState *aplic_m; 348 uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH; 349 350 aplic_m = aplic; 351 while (aplic_m && !aplic_m->mmode) { 352 aplic_m = aplic_m->parent; 353 } 354 if (!aplic_m) { 355 qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n", 356 __func__); 357 return; 358 } 359 360 if (aplic->mmode) { 361 msicfgaddr = aplic_m->mmsicfgaddr; 362 msicfgaddrH = aplic_m->mmsicfgaddrH; 363 } else { 364 msicfgaddr = aplic_m->smsicfgaddr; 365 msicfgaddrH = aplic_m->smsicfgaddrH; 366 } 367 368 lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) & 369 APLIC_xMSICFGADDRH_LHXS_MASK; 370 lhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXW_SHIFT) & 371 APLIC_xMSICFGADDRH_LHXW_MASK; 372 hhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXS_SHIFT) & 373 APLIC_xMSICFGADDRH_HHXS_MASK; 374 hhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXW_SHIFT) & 375 APLIC_xMSICFGADDRH_HHXW_MASK; 376 377 group_idx = hart_idx >> lhxw; 378 hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw); 379 380 addr = msicfgaddr; 381 addr |= ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) << 32; 382 addr |= ((uint64_t)(group_idx & APLIC_xMSICFGADDR_PPN_HHX_MASK(hhxw))) << 383 APLIC_xMSICFGADDR_PPN_HHX_SHIFT(hhxs); 384 addr |= ((uint64_t)(hart_idx & APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw))) << 385 APLIC_xMSICFGADDR_PPN_LHX_SHIFT(lhxs); 386 addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs)); 387 addr <<= APLIC_xMSICFGADDR_PPN_SHIFT; 388 389 address_space_stl_le(&address_space_memory, addr, 390 eiid, MEMTXATTRS_UNSPECIFIED, &result); 391 if (result != MEMTX_OK) { 392 qemu_log_mask(LOG_GUEST_ERROR, "%s: MSI write failed for " 393 "hart_index=%d guest_index=%d eiid=%d\n", 394 __func__, hart_idx, guest_idx, eiid); 395 } 396 } 397 398 static void riscv_aplic_msi_irq_update(RISCVAPLICState *aplic, uint32_t irq) 399 { 400 uint32_t hart_idx, guest_idx, eiid; 401 402 if (!aplic->msimode || (aplic->num_irqs <= irq) || 403 !(aplic->domaincfg & APLIC_DOMAINCFG_IE)) { 404 return; 405 } 406 407 if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) != APLIC_ISTATE_ENPEND) { 408 return; 409 } 410 411 riscv_aplic_set_pending_raw(aplic, irq, false); 412 413 hart_idx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT; 414 hart_idx &= APLIC_TARGET_HART_IDX_MASK; 415 if (aplic->mmode) { 416 /* M-level APLIC ignores guest_index */ 417 guest_idx = 0; 418 } else { 419 guest_idx = aplic->target[irq] >> APLIC_TARGET_GUEST_IDX_SHIFT; 420 guest_idx &= APLIC_TARGET_GUEST_IDX_MASK; 421 } 422 eiid = aplic->target[irq] & APLIC_TARGET_EIID_MASK; 423 riscv_aplic_msi_send(aplic, hart_idx, guest_idx, eiid); 424 } 425 426 static uint32_t riscv_aplic_idc_topi(RISCVAPLICState *aplic, uint32_t idc) 427 { 428 uint32_t best_irq, best_iprio; 429 uint32_t irq, iprio, ihartidx, ithres; 430 431 if (aplic->num_harts <= idc) { 432 return 0; 433 } 434 435 ithres = aplic->ithreshold[idc]; 436 best_irq = best_iprio = UINT32_MAX; 437 for (irq = 1; irq < aplic->num_irqs; irq++) { 438 if ((aplic->state[irq] & APLIC_ISTATE_ENPEND) != 439 APLIC_ISTATE_ENPEND) { 440 continue; 441 } 442 443 ihartidx = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT; 444 ihartidx &= APLIC_TARGET_HART_IDX_MASK; 445 if (ihartidx != idc) { 446 continue; 447 } 448 449 iprio = aplic->target[irq] & aplic->iprio_mask; 450 if (ithres && iprio >= ithres) { 451 continue; 452 } 453 454 if (iprio < best_iprio) { 455 best_irq = irq; 456 best_iprio = iprio; 457 } 458 } 459 460 if (best_irq < aplic->num_irqs && best_iprio <= aplic->iprio_mask) { 461 return (best_irq << APLIC_IDC_TOPI_ID_SHIFT) | best_iprio; 462 } 463 464 return 0; 465 } 466 467 static void riscv_aplic_idc_update(RISCVAPLICState *aplic, uint32_t idc) 468 { 469 uint32_t topi; 470 471 if (aplic->msimode || aplic->num_harts <= idc) { 472 return; 473 } 474 475 topi = riscv_aplic_idc_topi(aplic, idc); 476 if ((aplic->domaincfg & APLIC_DOMAINCFG_IE) && 477 aplic->idelivery[idc] && 478 (aplic->iforce[idc] || topi)) { 479 qemu_irq_raise(aplic->external_irqs[idc]); 480 } else { 481 qemu_irq_lower(aplic->external_irqs[idc]); 482 } 483 } 484 485 static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc) 486 { 487 uint32_t irq, state, sm, topi = riscv_aplic_idc_topi(aplic, idc); 488 489 if (!topi) { 490 aplic->iforce[idc] = 0; 491 return 0; 492 } 493 494 irq = (topi >> APLIC_IDC_TOPI_ID_SHIFT) & APLIC_IDC_TOPI_ID_MASK; 495 sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK; 496 state = aplic->state[irq]; 497 riscv_aplic_set_pending_raw(aplic, irq, false); 498 if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) && 499 (state & APLIC_ISTATE_INPUT)) { 500 riscv_aplic_set_pending_raw(aplic, irq, true); 501 } else if ((sm == APLIC_SOURCECFG_SM_LEVEL_LOW) && 502 !(state & APLIC_ISTATE_INPUT)) { 503 riscv_aplic_set_pending_raw(aplic, irq, true); 504 } 505 riscv_aplic_idc_update(aplic, idc); 506 507 return topi; 508 } 509 510 static void riscv_aplic_request(void *opaque, int irq, int level) 511 { 512 bool update = false; 513 RISCVAPLICState *aplic = opaque; 514 uint32_t sourcecfg, childidx, state, idc; 515 516 assert((0 < irq) && (irq < aplic->num_irqs)); 517 518 sourcecfg = aplic->sourcecfg[irq]; 519 if (sourcecfg & APLIC_SOURCECFG_D) { 520 childidx = sourcecfg & APLIC_SOURCECFG_CHILDIDX_MASK; 521 if (childidx < aplic->num_children) { 522 riscv_aplic_request(aplic->children[childidx], irq, level); 523 } 524 return; 525 } 526 527 state = aplic->state[irq]; 528 switch (sourcecfg & APLIC_SOURCECFG_SM_MASK) { 529 case APLIC_SOURCECFG_SM_EDGE_RISE: 530 if ((level > 0) && !(state & APLIC_ISTATE_INPUT) && 531 !(state & APLIC_ISTATE_PENDING)) { 532 riscv_aplic_set_pending_raw(aplic, irq, true); 533 update = true; 534 } 535 break; 536 case APLIC_SOURCECFG_SM_EDGE_FALL: 537 if ((level <= 0) && (state & APLIC_ISTATE_INPUT) && 538 !(state & APLIC_ISTATE_PENDING)) { 539 riscv_aplic_set_pending_raw(aplic, irq, true); 540 update = true; 541 } 542 break; 543 case APLIC_SOURCECFG_SM_LEVEL_HIGH: 544 if ((level > 0) && !(state & APLIC_ISTATE_PENDING)) { 545 riscv_aplic_set_pending_raw(aplic, irq, true); 546 update = true; 547 } 548 break; 549 case APLIC_SOURCECFG_SM_LEVEL_LOW: 550 if ((level <= 0) && !(state & APLIC_ISTATE_PENDING)) { 551 riscv_aplic_set_pending_raw(aplic, irq, true); 552 update = true; 553 } 554 break; 555 default: 556 break; 557 } 558 559 if (level <= 0) { 560 aplic->state[irq] &= ~APLIC_ISTATE_INPUT; 561 } else { 562 aplic->state[irq] |= APLIC_ISTATE_INPUT; 563 } 564 565 if (update) { 566 if (aplic->msimode) { 567 riscv_aplic_msi_irq_update(aplic, irq); 568 } else { 569 idc = aplic->target[irq] >> APLIC_TARGET_HART_IDX_SHIFT; 570 idc &= APLIC_TARGET_HART_IDX_MASK; 571 riscv_aplic_idc_update(aplic, idc); 572 } 573 } 574 } 575 576 static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size) 577 { 578 uint32_t irq, word, idc; 579 RISCVAPLICState *aplic = opaque; 580 581 /* Reads must be 4 byte words */ 582 if ((addr & 0x3) != 0) { 583 goto err; 584 } 585 586 if (addr == APLIC_DOMAINCFG) { 587 return APLIC_DOMAINCFG_RDONLY | aplic->domaincfg | 588 (aplic->msimode ? APLIC_DOMAINCFG_DM : 0); 589 } else if ((APLIC_SOURCECFG_BASE <= addr) && 590 (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) { 591 irq = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1; 592 return aplic->sourcecfg[irq]; 593 } else if (aplic->mmode && aplic->msimode && 594 (addr == APLIC_MMSICFGADDR)) { 595 return aplic->mmsicfgaddr; 596 } else if (aplic->mmode && aplic->msimode && 597 (addr == APLIC_MMSICFGADDRH)) { 598 return aplic->mmsicfgaddrH; 599 } else if (aplic->mmode && aplic->msimode && 600 (addr == APLIC_SMSICFGADDR)) { 601 /* 602 * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if: 603 * (a) the interrupt domain is at machine level 604 * (b) the domain's harts implement supervisor mode 605 * (c) the domain has one or more child supervisor-level domains 606 * that support MSI delivery mode (domaincfg.DM is not read- 607 * only zero in at least one of the supervisor-level child 608 * domains). 609 */ 610 return (aplic->num_children) ? aplic->smsicfgaddr : 0; 611 } else if (aplic->mmode && aplic->msimode && 612 (addr == APLIC_SMSICFGADDRH)) { 613 return (aplic->num_children) ? aplic->smsicfgaddrH : 0; 614 } else if ((APLIC_SETIP_BASE <= addr) && 615 (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) { 616 word = (addr - APLIC_SETIP_BASE) >> 2; 617 return riscv_aplic_read_pending_word(aplic, word); 618 } else if (addr == APLIC_SETIPNUM) { 619 return 0; 620 } else if ((APLIC_CLRIP_BASE <= addr) && 621 (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) { 622 word = (addr - APLIC_CLRIP_BASE) >> 2; 623 return riscv_aplic_read_input_word(aplic, word); 624 } else if (addr == APLIC_CLRIPNUM) { 625 return 0; 626 } else if ((APLIC_SETIE_BASE <= addr) && 627 (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) { 628 word = (addr - APLIC_SETIE_BASE) >> 2; 629 return riscv_aplic_read_enabled_word(aplic, word); 630 } else if (addr == APLIC_SETIENUM) { 631 return 0; 632 } else if ((APLIC_CLRIE_BASE <= addr) && 633 (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) { 634 return 0; 635 } else if (addr == APLIC_CLRIENUM) { 636 return 0; 637 } else if (addr == APLIC_SETIPNUM_LE) { 638 return 0; 639 } else if (addr == APLIC_SETIPNUM_BE) { 640 return 0; 641 } else if (addr == APLIC_GENMSI) { 642 return (aplic->msimode) ? aplic->genmsi : 0; 643 } else if ((APLIC_TARGET_BASE <= addr) && 644 (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { 645 irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1; 646 return aplic->target[irq]; 647 } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) && 648 (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) { 649 idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE; 650 switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) { 651 case APLIC_IDC_IDELIVERY: 652 return aplic->idelivery[idc]; 653 case APLIC_IDC_IFORCE: 654 return aplic->iforce[idc]; 655 case APLIC_IDC_ITHRESHOLD: 656 return aplic->ithreshold[idc]; 657 case APLIC_IDC_TOPI: 658 return riscv_aplic_idc_topi(aplic, idc); 659 case APLIC_IDC_CLAIMI: 660 return riscv_aplic_idc_claimi(aplic, idc); 661 default: 662 goto err; 663 }; 664 } 665 666 err: 667 qemu_log_mask(LOG_GUEST_ERROR, 668 "%s: Invalid register read 0x%" HWADDR_PRIx "\n", 669 __func__, addr); 670 return 0; 671 } 672 673 static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value, 674 unsigned size) 675 { 676 RISCVAPLICState *aplic = opaque; 677 uint32_t irq, word, idc = UINT32_MAX; 678 679 /* Writes must be 4 byte words */ 680 if ((addr & 0x3) != 0) { 681 goto err; 682 } 683 684 if (addr == APLIC_DOMAINCFG) { 685 /* Only IE bit writable at the moment */ 686 value &= APLIC_DOMAINCFG_IE; 687 aplic->domaincfg = value; 688 } else if ((APLIC_SOURCECFG_BASE <= addr) && 689 (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) { 690 irq = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1; 691 if (!aplic->num_children && (value & APLIC_SOURCECFG_D)) { 692 value = 0; 693 } 694 if (value & APLIC_SOURCECFG_D) { 695 value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_CHILDIDX_MASK); 696 } else { 697 value &= (APLIC_SOURCECFG_D | APLIC_SOURCECFG_SM_MASK); 698 } 699 aplic->sourcecfg[irq] = value; 700 if ((aplic->sourcecfg[irq] & APLIC_SOURCECFG_D) || 701 (aplic->sourcecfg[irq] == 0)) { 702 riscv_aplic_set_pending_raw(aplic, irq, false); 703 riscv_aplic_set_enabled_raw(aplic, irq, false); 704 } 705 } else if (aplic->mmode && aplic->msimode && 706 (addr == APLIC_MMSICFGADDR)) { 707 if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { 708 aplic->mmsicfgaddr = value; 709 } 710 } else if (aplic->mmode && aplic->msimode && 711 (addr == APLIC_MMSICFGADDRH)) { 712 if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { 713 aplic->mmsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK; 714 } 715 } else if (aplic->mmode && aplic->msimode && 716 (addr == APLIC_SMSICFGADDR)) { 717 /* 718 * Registers SMSICFGADDR and SMSICFGADDRH are implemented only if: 719 * (a) the interrupt domain is at machine level 720 * (b) the domain's harts implement supervisor mode 721 * (c) the domain has one or more child supervisor-level domains 722 * that support MSI delivery mode (domaincfg.DM is not read- 723 * only zero in at least one of the supervisor-level child 724 * domains). 725 */ 726 if (aplic->num_children && 727 !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { 728 aplic->smsicfgaddr = value; 729 } 730 } else if (aplic->mmode && aplic->msimode && 731 (addr == APLIC_SMSICFGADDRH)) { 732 if (aplic->num_children && 733 !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { 734 aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK; 735 } 736 } else if ((APLIC_SETIP_BASE <= addr) && 737 (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) { 738 word = (addr - APLIC_SETIP_BASE) >> 2; 739 riscv_aplic_set_pending_word(aplic, word, value, true); 740 } else if (addr == APLIC_SETIPNUM) { 741 riscv_aplic_set_pending(aplic, value, true); 742 } else if ((APLIC_CLRIP_BASE <= addr) && 743 (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) { 744 word = (addr - APLIC_CLRIP_BASE) >> 2; 745 riscv_aplic_set_pending_word(aplic, word, value, false); 746 } else if (addr == APLIC_CLRIPNUM) { 747 riscv_aplic_set_pending(aplic, value, false); 748 } else if ((APLIC_SETIE_BASE <= addr) && 749 (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) { 750 word = (addr - APLIC_SETIE_BASE) >> 2; 751 riscv_aplic_set_enabled_word(aplic, word, value, true); 752 } else if (addr == APLIC_SETIENUM) { 753 riscv_aplic_set_enabled(aplic, value, true); 754 } else if ((APLIC_CLRIE_BASE <= addr) && 755 (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) { 756 word = (addr - APLIC_CLRIE_BASE) >> 2; 757 riscv_aplic_set_enabled_word(aplic, word, value, false); 758 } else if (addr == APLIC_CLRIENUM) { 759 riscv_aplic_set_enabled(aplic, value, false); 760 } else if (addr == APLIC_SETIPNUM_LE) { 761 riscv_aplic_set_pending(aplic, value, true); 762 } else if (addr == APLIC_SETIPNUM_BE) { 763 riscv_aplic_set_pending(aplic, bswap32(value), true); 764 } else if (addr == APLIC_GENMSI) { 765 if (aplic->msimode) { 766 aplic->genmsi = value & ~(APLIC_TARGET_GUEST_IDX_MASK << 767 APLIC_TARGET_GUEST_IDX_SHIFT); 768 riscv_aplic_msi_send(aplic, 769 value >> APLIC_TARGET_HART_IDX_SHIFT, 770 0, 771 value & APLIC_TARGET_EIID_MASK); 772 } 773 } else if ((APLIC_TARGET_BASE <= addr) && 774 (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { 775 irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1; 776 if (aplic->msimode) { 777 aplic->target[irq] = value; 778 } else { 779 aplic->target[irq] = (value & ~APLIC_TARGET_IPRIO_MASK) | 780 ((value & aplic->iprio_mask) ? 781 (value & aplic->iprio_mask) : 1); 782 } 783 } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) && 784 (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) { 785 idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE; 786 switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) { 787 case APLIC_IDC_IDELIVERY: 788 aplic->idelivery[idc] = value & 0x1; 789 break; 790 case APLIC_IDC_IFORCE: 791 aplic->iforce[idc] = value & 0x1; 792 break; 793 case APLIC_IDC_ITHRESHOLD: 794 aplic->ithreshold[idc] = value & aplic->iprio_mask; 795 break; 796 default: 797 goto err; 798 }; 799 } else { 800 goto err; 801 } 802 803 if (aplic->msimode) { 804 for (irq = 1; irq < aplic->num_irqs; irq++) { 805 riscv_aplic_msi_irq_update(aplic, irq); 806 } 807 } else { 808 if (idc == UINT32_MAX) { 809 for (idc = 0; idc < aplic->num_harts; idc++) { 810 riscv_aplic_idc_update(aplic, idc); 811 } 812 } else { 813 riscv_aplic_idc_update(aplic, idc); 814 } 815 } 816 817 return; 818 819 err: 820 qemu_log_mask(LOG_GUEST_ERROR, 821 "%s: Invalid register write 0x%" HWADDR_PRIx "\n", 822 __func__, addr); 823 } 824 825 static const MemoryRegionOps riscv_aplic_ops = { 826 .read = riscv_aplic_read, 827 .write = riscv_aplic_write, 828 .endianness = DEVICE_LITTLE_ENDIAN, 829 .valid = { 830 .min_access_size = 4, 831 .max_access_size = 4 832 } 833 }; 834 835 static void riscv_aplic_realize(DeviceState *dev, Error **errp) 836 { 837 uint32_t i; 838 RISCVAPLICState *aplic = RISCV_APLIC(dev); 839 840 if (!is_kvm_aia(aplic->msimode)) { 841 aplic->bitfield_words = (aplic->num_irqs + 31) >> 5; 842 aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs); 843 aplic->state = g_new0(uint32_t, aplic->num_irqs); 844 aplic->target = g_new0(uint32_t, aplic->num_irqs); 845 if (!aplic->msimode) { 846 for (i = 0; i < aplic->num_irqs; i++) { 847 aplic->target[i] = 1; 848 } 849 } 850 aplic->idelivery = g_new0(uint32_t, aplic->num_harts); 851 aplic->iforce = g_new0(uint32_t, aplic->num_harts); 852 aplic->ithreshold = g_new0(uint32_t, aplic->num_harts); 853 854 memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, 855 aplic, TYPE_RISCV_APLIC, aplic->aperture_size); 856 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); 857 } 858 859 /* 860 * Only root APLICs have hardware IRQ lines. All non-root APLICs 861 * have IRQ lines delegated by their parent APLIC. 862 */ 863 if (!aplic->parent) { 864 if (kvm_enabled() && is_kvm_aia(aplic->msimode)) { 865 qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs); 866 } else { 867 qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); 868 } 869 } 870 871 /* Create output IRQ lines for non-MSI mode */ 872 if (!aplic->msimode) { 873 aplic->external_irqs = g_malloc(sizeof(qemu_irq) * aplic->num_harts); 874 qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts); 875 876 /* Claim the CPU interrupt to be triggered by this APLIC */ 877 for (i = 0; i < aplic->num_harts; i++) { 878 RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i)); 879 if (riscv_cpu_claim_interrupts(cpu, 880 (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { 881 error_report("%s already claimed", 882 (aplic->mmode) ? "MEIP" : "SEIP"); 883 exit(1); 884 } 885 } 886 } 887 888 msi_nonbroken = true; 889 } 890 891 static Property riscv_aplic_properties[] = { 892 DEFINE_PROP_UINT32("aperture-size", RISCVAPLICState, aperture_size, 0), 893 DEFINE_PROP_UINT32("hartid-base", RISCVAPLICState, hartid_base, 0), 894 DEFINE_PROP_UINT32("num-harts", RISCVAPLICState, num_harts, 0), 895 DEFINE_PROP_UINT32("iprio-mask", RISCVAPLICState, iprio_mask, 0), 896 DEFINE_PROP_UINT32("num-irqs", RISCVAPLICState, num_irqs, 0), 897 DEFINE_PROP_BOOL("msimode", RISCVAPLICState, msimode, 0), 898 DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0), 899 DEFINE_PROP_END_OF_LIST(), 900 }; 901 902 static const VMStateDescription vmstate_riscv_aplic = { 903 .name = "riscv_aplic", 904 .version_id = 1, 905 .minimum_version_id = 1, 906 .fields = (const VMStateField[]) { 907 VMSTATE_UINT32(domaincfg, RISCVAPLICState), 908 VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState), 909 VMSTATE_UINT32(mmsicfgaddrH, RISCVAPLICState), 910 VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState), 911 VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState), 912 VMSTATE_UINT32(genmsi, RISCVAPLICState), 913 VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState, 914 num_irqs, 0, 915 vmstate_info_uint32, uint32_t), 916 VMSTATE_VARRAY_UINT32(state, RISCVAPLICState, 917 num_irqs, 0, 918 vmstate_info_uint32, uint32_t), 919 VMSTATE_VARRAY_UINT32(target, RISCVAPLICState, 920 num_irqs, 0, 921 vmstate_info_uint32, uint32_t), 922 VMSTATE_VARRAY_UINT32(idelivery, RISCVAPLICState, 923 num_harts, 0, 924 vmstate_info_uint32, uint32_t), 925 VMSTATE_VARRAY_UINT32(iforce, RISCVAPLICState, 926 num_harts, 0, 927 vmstate_info_uint32, uint32_t), 928 VMSTATE_VARRAY_UINT32(ithreshold, RISCVAPLICState, 929 num_harts, 0, 930 vmstate_info_uint32, uint32_t), 931 VMSTATE_END_OF_LIST() 932 } 933 }; 934 935 static void riscv_aplic_class_init(ObjectClass *klass, void *data) 936 { 937 DeviceClass *dc = DEVICE_CLASS(klass); 938 939 device_class_set_props(dc, riscv_aplic_properties); 940 dc->realize = riscv_aplic_realize; 941 dc->vmsd = &vmstate_riscv_aplic; 942 } 943 944 static const TypeInfo riscv_aplic_info = { 945 .name = TYPE_RISCV_APLIC, 946 .parent = TYPE_SYS_BUS_DEVICE, 947 .instance_size = sizeof(RISCVAPLICState), 948 .class_init = riscv_aplic_class_init, 949 }; 950 951 static void riscv_aplic_register_types(void) 952 { 953 type_register_static(&riscv_aplic_info); 954 } 955 956 type_init(riscv_aplic_register_types) 957 958 /* 959 * Add a APLIC device to another APLIC device as child for 960 * interrupt delegation. 961 */ 962 void riscv_aplic_add_child(DeviceState *parent, DeviceState *child) 963 { 964 RISCVAPLICState *caplic, *paplic; 965 966 assert(parent && child); 967 caplic = RISCV_APLIC(child); 968 paplic = RISCV_APLIC(parent); 969 970 assert(paplic->num_irqs == caplic->num_irqs); 971 assert(paplic->num_children <= QEMU_APLIC_MAX_CHILDREN); 972 973 caplic->parent = paplic; 974 paplic->children[paplic->num_children] = caplic; 975 paplic->num_children++; 976 } 977 978 /* 979 * Create APLIC device. 980 */ 981 DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, 982 uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, 983 uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent) 984 { 985 DeviceState *dev = qdev_new(TYPE_RISCV_APLIC); 986 uint32_t i; 987 988 assert(num_harts < APLIC_MAX_IDC); 989 assert((APLIC_IDC_BASE + (num_harts * APLIC_IDC_SIZE)) <= size); 990 assert(num_sources < APLIC_MAX_SOURCE); 991 assert(APLIC_MIN_IPRIO_BITS <= iprio_bits); 992 assert(iprio_bits <= APLIC_MAX_IPRIO_BITS); 993 994 qdev_prop_set_uint32(dev, "aperture-size", size); 995 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); 996 qdev_prop_set_uint32(dev, "num-harts", num_harts); 997 qdev_prop_set_uint32(dev, "iprio-mask", ((1U << iprio_bits) - 1)); 998 qdev_prop_set_uint32(dev, "num-irqs", num_sources + 1); 999 qdev_prop_set_bit(dev, "msimode", msimode); 1000 qdev_prop_set_bit(dev, "mmode", mmode); 1001 1002 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1003 1004 if (!is_kvm_aia(msimode)) { 1005 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 1006 } 1007 1008 if (parent) { 1009 riscv_aplic_add_child(parent, dev); 1010 } 1011 1012 if (!msimode) { 1013 for (i = 0; i < num_harts; i++) { 1014 CPUState *cpu = cpu_by_arch_id(hartid_base + i); 1015 1016 qdev_connect_gpio_out_named(dev, NULL, i, 1017 qdev_get_gpio_in(DEVICE(cpu), 1018 (mmode) ? IRQ_M_EXT : IRQ_S_EXT)); 1019 } 1020 } 1021 1022 return dev; 1023 } 1024