12dfa91a2SCédric Le Goater /* 22dfa91a2SCédric Le Goater * QEMU PowerPC XIVE interrupt controller model 32dfa91a2SCédric Le Goater * 42dfa91a2SCédric Le Goater * Copyright (c) 2017-2018, IBM Corporation. 52dfa91a2SCédric Le Goater * 62dfa91a2SCédric Le Goater * This code is licensed under the GPL version 2 or later. See the 72dfa91a2SCédric Le Goater * COPYING file in the top-level directory. 82dfa91a2SCédric Le Goater */ 92dfa91a2SCédric Le Goater 102dfa91a2SCédric Le Goater #ifndef PPC_PNV_XIVE_REGS_H 112dfa91a2SCédric Le Goater #define PPC_PNV_XIVE_REGS_H 122dfa91a2SCédric Le Goater 132dfa91a2SCédric Le Goater /* IC register offsets 0x0 - 0x400 */ 142dfa91a2SCédric Le Goater #define CQ_SWI_CMD_HIST 0x020 152dfa91a2SCédric Le Goater #define CQ_SWI_CMD_POLL 0x028 162dfa91a2SCédric Le Goater #define CQ_SWI_CMD_BCAST 0x030 172dfa91a2SCédric Le Goater #define CQ_SWI_CMD_ASSIGN 0x038 182dfa91a2SCédric Le Goater #define CQ_SWI_CMD_BLK_UPD 0x040 192dfa91a2SCédric Le Goater #define CQ_SWI_RSP 0x048 202dfa91a2SCédric Le Goater #define CQ_CFG_PB_GEN 0x050 212dfa91a2SCédric Le Goater #define CQ_INT_ADDR_OPT PPC_BITMASK(14, 15) 222dfa91a2SCédric Le Goater #define CQ_MSGSND 0x058 232dfa91a2SCédric Le Goater #define CQ_CNPM_SEL 0x078 242dfa91a2SCédric Le Goater #define CQ_IC_BAR 0x080 252dfa91a2SCédric Le Goater #define CQ_IC_BAR_VALID PPC_BIT(0) 262dfa91a2SCédric Le Goater #define CQ_IC_BAR_64K PPC_BIT(1) 272dfa91a2SCédric Le Goater #define CQ_TM1_BAR 0x90 282dfa91a2SCédric Le Goater #define CQ_TM2_BAR 0x0a0 292dfa91a2SCédric Le Goater #define CQ_TM_BAR_VALID PPC_BIT(0) 302dfa91a2SCédric Le Goater #define CQ_TM_BAR_64K PPC_BIT(1) 312dfa91a2SCédric Le Goater #define CQ_PC_BAR 0x0b0 322dfa91a2SCédric Le Goater #define CQ_PC_BAR_VALID PPC_BIT(0) 332dfa91a2SCédric Le Goater #define CQ_PC_BARM 0x0b8 342dfa91a2SCédric Le Goater #define CQ_PC_BARM_MASK PPC_BITMASK(26, 38) 352dfa91a2SCédric Le Goater #define CQ_VC_BAR 0x0c0 362dfa91a2SCédric Le Goater #define CQ_VC_BAR_VALID PPC_BIT(0) 372dfa91a2SCédric Le Goater #define CQ_VC_BARM 0x0c8 382dfa91a2SCédric Le Goater #define CQ_VC_BARM_MASK PPC_BITMASK(21, 37) 392dfa91a2SCédric Le Goater #define CQ_TAR 0x0f0 402dfa91a2SCédric Le Goater #define CQ_TAR_TBL_AUTOINC PPC_BIT(0) 412dfa91a2SCédric Le Goater #define CQ_TAR_TSEL PPC_BITMASK(12, 15) 422dfa91a2SCédric Le Goater #define CQ_TAR_TSEL_BLK PPC_BIT(12) 432dfa91a2SCédric Le Goater #define CQ_TAR_TSEL_MIG PPC_BIT(13) 442dfa91a2SCédric Le Goater #define CQ_TAR_TSEL_VDT PPC_BIT(14) 452dfa91a2SCédric Le Goater #define CQ_TAR_TSEL_EDT PPC_BIT(15) 462dfa91a2SCédric Le Goater #define CQ_TAR_TSEL_INDEX PPC_BITMASK(26, 31) 472dfa91a2SCédric Le Goater #define CQ_TDR 0x0f8 482dfa91a2SCédric Le Goater #define CQ_TDR_VDT_VALID PPC_BIT(0) 492dfa91a2SCédric Le Goater #define CQ_TDR_VDT_BLK PPC_BITMASK(11, 15) 502dfa91a2SCédric Le Goater #define CQ_TDR_VDT_INDEX PPC_BITMASK(28, 31) 512dfa91a2SCédric Le Goater #define CQ_TDR_EDT_TYPE PPC_BITMASK(0, 1) 522dfa91a2SCédric Le Goater #define CQ_TDR_EDT_INVALID 0 532dfa91a2SCédric Le Goater #define CQ_TDR_EDT_IPI 1 542dfa91a2SCédric Le Goater #define CQ_TDR_EDT_EQ 2 552dfa91a2SCédric Le Goater #define CQ_TDR_EDT_BLK PPC_BITMASK(12, 15) 562dfa91a2SCédric Le Goater #define CQ_TDR_EDT_INDEX PPC_BITMASK(26, 31) 572dfa91a2SCédric Le Goater #define CQ_PBI_CTL 0x100 582dfa91a2SCédric Le Goater #define CQ_PBI_PC_64K PPC_BIT(5) 592dfa91a2SCédric Le Goater #define CQ_PBI_VC_64K PPC_BIT(6) 602dfa91a2SCédric Le Goater #define CQ_PBI_LNX_TRIG PPC_BIT(7) 612dfa91a2SCédric Le Goater #define CQ_PBI_FORCE_TM_LOCAL PPC_BIT(22) 622dfa91a2SCédric Le Goater #define CQ_PBO_CTL 0x108 632dfa91a2SCédric Le Goater #define CQ_AIB_CTL 0x110 642dfa91a2SCédric Le Goater #define CQ_RST_CTL 0x118 652dfa91a2SCédric Le Goater #define CQ_FIRMASK 0x198 662dfa91a2SCédric Le Goater #define CQ_FIRMASK_AND 0x1a0 672dfa91a2SCédric Le Goater #define CQ_FIRMASK_OR 0x1a8 682dfa91a2SCédric Le Goater 692dfa91a2SCédric Le Goater /* PC LBS1 register offsets 0x400 - 0x800 */ 702dfa91a2SCédric Le Goater #define PC_TCTXT_CFG 0x400 712dfa91a2SCédric Le Goater #define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0) 722dfa91a2SCédric Le Goater #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) 732dfa91a2SCédric Le Goater #define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) 742dfa91a2SCédric Le Goater #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) 752dfa91a2SCédric Le Goater #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) 762dfa91a2SCédric Le Goater #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) 772dfa91a2SCédric Le Goater #define PC_TCTXT_CHIPID PPC_BITMASK(12, 15) 782dfa91a2SCédric Le Goater #define PC_TCTXT_INIT_AGE PPC_BITMASK(30, 31) 792dfa91a2SCédric Le Goater #define PC_TCTXT_TRACK 0x408 802dfa91a2SCédric Le Goater #define PC_TCTXT_TRACK_EN PPC_BIT(0) 812dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR0 0x420 822dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR_VALID PPC_BIT(0) 832dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR_THRDID PPC_BITMASK(9, 15) 842dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR1 0x428 852dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR2 0x430 862dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR3 0x438 872dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG0 0x440 882dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG0_SET 0x448 892dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG0_CLR 0x450 902dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG1 0x460 912dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG1_SET 0x468 922dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG1_CLR 0x470 932dfa91a2SCédric Le Goater #define PC_GLOBAL_CONFIG 0x480 942dfa91a2SCédric Le Goater #define PC_GCONF_INDIRECT PPC_BIT(32) 952dfa91a2SCédric Le Goater #define PC_GCONF_CHIPID_OVR PPC_BIT(40) 962dfa91a2SCédric Le Goater #define PC_GCONF_CHIPID PPC_BITMASK(44, 47) 972dfa91a2SCédric Le Goater #define PC_VSD_TABLE_ADDR 0x488 982dfa91a2SCédric Le Goater #define PC_VSD_TABLE_DATA 0x490 992dfa91a2SCédric Le Goater #define PC_AT_KILL 0x4b0 1002dfa91a2SCédric Le Goater #define PC_AT_KILL_VALID PPC_BIT(0) 1012dfa91a2SCédric Le Goater #define PC_AT_KILL_BLOCK_ID PPC_BITMASK(27, 31) 1022dfa91a2SCédric Le Goater #define PC_AT_KILL_OFFSET PPC_BITMASK(48, 60) 1032dfa91a2SCédric Le Goater #define PC_AT_KILL_MASK 0x4b8 1042dfa91a2SCédric Le Goater 1052dfa91a2SCédric Le Goater /* PC LBS2 register offsets */ 1062dfa91a2SCédric Le Goater #define PC_VPC_CACHE_ENABLE 0x708 1072dfa91a2SCédric Le Goater #define PC_VPC_CACHE_EN_MASK PPC_BITMASK(0, 31) 1082dfa91a2SCédric Le Goater #define PC_VPC_SCRUB_TRIG 0x710 1092dfa91a2SCédric Le Goater #define PC_VPC_SCRUB_MASK 0x718 1102dfa91a2SCédric Le Goater #define PC_SCRUB_VALID PPC_BIT(0) 1112dfa91a2SCédric Le Goater #define PC_SCRUB_WANT_DISABLE PPC_BIT(1) 1122dfa91a2SCédric Le Goater #define PC_SCRUB_WANT_INVAL PPC_BIT(2) 1132dfa91a2SCédric Le Goater #define PC_SCRUB_BLOCK_ID PPC_BITMASK(27, 31) 1142dfa91a2SCédric Le Goater #define PC_SCRUB_OFFSET PPC_BITMASK(45, 63) 1152dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_SPEC 0x738 1162dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_CONFLICT PPC_BIT(0) 1172dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_FULL PPC_BIT(8) 1182dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_BLOCKID PPC_BITMASK(27, 31) 1192dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_OFFSET PPC_BITMASK(45, 63) 1202dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT0 0x740 1212dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT1 0x748 1222dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT2 0x750 1232dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT3 0x758 1242dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT4 0x760 1252dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT5 0x768 1262dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT6 0x770 1272dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT7 0x778 1282dfa91a2SCédric Le Goater 1292dfa91a2SCédric Le Goater /* VC0 register offsets 0x800 - 0xFFF */ 1302dfa91a2SCédric Le Goater #define VC_GLOBAL_CONFIG 0x800 1312dfa91a2SCédric Le Goater #define VC_GCONF_INDIRECT PPC_BIT(32) 1322dfa91a2SCédric Le Goater #define VC_VSD_TABLE_ADDR 0x808 1332dfa91a2SCédric Le Goater #define VC_VSD_TABLE_DATA 0x810 1342dfa91a2SCédric Le Goater #define VC_IVE_ISB_BLOCK_MODE 0x818 1352dfa91a2SCédric Le Goater #define VC_EQD_BLOCK_MODE 0x820 1362dfa91a2SCédric Le Goater #define VC_VPS_BLOCK_MODE 0x828 1372dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_IPI 0x840 1382dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_MEMB_EN PPC_BIT(45) 1392dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_MEMB_SZ PPC_BITMASK(46, 51) 1402dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_HW 0x848 1412dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_CASCADE1 0x850 1422dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_CASCADE2 0x858 1432dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_REDIST 0x860 1442dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_IPI_CASC 0x868 1452dfa91a2SCédric Le Goater #define VC_AIB_TX_ORDER_TAG2_REL_TF PPC_BIT(20) 1462dfa91a2SCédric Le Goater #define VC_AIB_TX_ORDER_TAG2 0x890 1472dfa91a2SCédric Le Goater #define VC_AT_MACRO_KILL 0x8b0 1482dfa91a2SCédric Le Goater #define VC_AT_MACRO_KILL_MASK 0x8b8 1492dfa91a2SCédric Le Goater #define VC_KILL_VALID PPC_BIT(0) 1502dfa91a2SCédric Le Goater #define VC_KILL_TYPE PPC_BITMASK(14, 15) 1512dfa91a2SCédric Le Goater #define VC_KILL_IRQ 0 1522dfa91a2SCédric Le Goater #define VC_KILL_IVC 1 1532dfa91a2SCédric Le Goater #define VC_KILL_SBC 2 1542dfa91a2SCédric Le Goater #define VC_KILL_EQD 3 1552dfa91a2SCédric Le Goater #define VC_KILL_BLOCK_ID PPC_BITMASK(27, 31) 1562dfa91a2SCédric Le Goater #define VC_KILL_OFFSET PPC_BITMASK(48, 60) 1572dfa91a2SCédric Le Goater #define VC_EQC_CACHE_ENABLE 0x908 1582dfa91a2SCédric Le Goater #define VC_EQC_CACHE_EN_MASK PPC_BITMASK(0, 15) 1592dfa91a2SCédric Le Goater #define VC_EQC_SCRUB_TRIG 0x910 1602dfa91a2SCédric Le Goater #define VC_EQC_SCRUB_MASK 0x918 1612dfa91a2SCédric Le Goater #define VC_EQC_CONFIG 0x920 1622dfa91a2SCédric Le Goater #define X_VC_EQC_CONFIG 0x214 /* XSCOM register */ 1632dfa91a2SCédric Le Goater #define VC_EQC_CONF_SYNC_IPI PPC_BIT(32) 1642dfa91a2SCédric Le Goater #define VC_EQC_CONF_SYNC_HW PPC_BIT(33) 1652dfa91a2SCédric Le Goater #define VC_EQC_CONF_SYNC_ESC1 PPC_BIT(34) 1662dfa91a2SCédric Le Goater #define VC_EQC_CONF_SYNC_ESC2 PPC_BIT(35) 1672dfa91a2SCédric Le Goater #define VC_EQC_CONF_SYNC_REDI PPC_BIT(36) 1682dfa91a2SCédric Le Goater #define VC_EQC_CONF_EQP_INTERLEAVE PPC_BIT(38) 1692dfa91a2SCédric Le Goater #define VC_EQC_CONF_ENABLE_END_s_BIT PPC_BIT(39) 1702dfa91a2SCédric Le Goater #define VC_EQC_CONF_ENABLE_END_u_BIT PPC_BIT(40) 1712dfa91a2SCédric Le Goater #define VC_EQC_CONF_ENABLE_END_c_BIT PPC_BIT(41) 1722dfa91a2SCédric Le Goater #define VC_EQC_CONF_ENABLE_MORE_QSZ PPC_BIT(42) 1732dfa91a2SCédric Le Goater #define VC_EQC_CONF_SKIP_ESCALATE PPC_BIT(43) 1742dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_SPEC 0x928 1752dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_CONFLICT PPC_BIT(0) 1762dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_FULL PPC_BIT(8) 1772dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_BLOCKID PPC_BITMASK(28, 31) 1782dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_OFFSET PPC_BITMASK(40, 63) 1792dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_DAT0 0x930 1802dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_DAT1 0x938 1812dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_DAT2 0x940 1822dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_DAT3 0x948 1832dfa91a2SCédric Le Goater #define VC_IVC_SCRUB_TRIG 0x990 1842dfa91a2SCédric Le Goater #define VC_IVC_SCRUB_MASK 0x998 1852dfa91a2SCédric Le Goater #define VC_SBC_SCRUB_TRIG 0xa10 1862dfa91a2SCédric Le Goater #define VC_SBC_SCRUB_MASK 0xa18 1872dfa91a2SCédric Le Goater #define VC_SCRUB_VALID PPC_BIT(0) 1882dfa91a2SCédric Le Goater #define VC_SCRUB_WANT_DISABLE PPC_BIT(1) 1892dfa91a2SCédric Le Goater #define VC_SCRUB_WANT_INVAL PPC_BIT(2) /* EQC and SBC only */ 1902dfa91a2SCédric Le Goater #define VC_SCRUB_BLOCK_ID PPC_BITMASK(28, 31) 1912dfa91a2SCédric Le Goater #define VC_SCRUB_OFFSET PPC_BITMASK(40, 63) 1922dfa91a2SCédric Le Goater #define VC_IVC_CACHE_ENABLE 0x988 1932dfa91a2SCédric Le Goater #define VC_IVC_CACHE_EN_MASK PPC_BITMASK(0, 15) 1942dfa91a2SCédric Le Goater #define VC_SBC_CACHE_ENABLE 0xa08 1952dfa91a2SCédric Le Goater #define VC_SBC_CACHE_EN_MASK PPC_BITMASK(0, 15) 1962dfa91a2SCédric Le Goater #define VC_IVC_CACHE_SCRUB_TRIG 0x990 1972dfa91a2SCédric Le Goater #define VC_IVC_CACHE_SCRUB_MASK 0x998 1982dfa91a2SCédric Le Goater #define VC_SBC_CACHE_ENABLE 0xa08 1992dfa91a2SCédric Le Goater #define VC_SBC_CACHE_SCRUB_TRIG 0xa10 2002dfa91a2SCédric Le Goater #define VC_SBC_CACHE_SCRUB_MASK 0xa18 2012dfa91a2SCédric Le Goater #define VC_SBC_CONFIG 0xa20 2022dfa91a2SCédric Le Goater #define VC_SBC_CONF_CPLX_CIST PPC_BIT(44) 2032dfa91a2SCédric Le Goater #define VC_SBC_CONF_CIST_BOTH PPC_BIT(45) 2042dfa91a2SCédric Le Goater #define VC_SBC_CONF_NO_UPD_PRF PPC_BIT(59) 2052dfa91a2SCédric Le Goater 2062dfa91a2SCédric Le Goater /* VC1 register offsets */ 2072dfa91a2SCédric Le Goater 2082dfa91a2SCédric Le Goater /* VSD Table address register definitions (shared) */ 2092dfa91a2SCédric Le Goater #define VST_ADDR_AUTOINC PPC_BIT(0) 2102dfa91a2SCédric Le Goater #define VST_TABLE_SELECT PPC_BITMASK(13, 15) 2112dfa91a2SCédric Le Goater #define VST_TSEL_IVT 0 2122dfa91a2SCédric Le Goater #define VST_TSEL_SBE 1 2132dfa91a2SCédric Le Goater #define VST_TSEL_EQDT 2 2142dfa91a2SCédric Le Goater #define VST_TSEL_VPDT 3 2152dfa91a2SCédric Le Goater #define VST_TSEL_IRQ 4 /* VC only */ 2162dfa91a2SCédric Le Goater #define VST_TABLE_BLOCK PPC_BITMASK(27, 31) 2172dfa91a2SCédric Le Goater 2182dfa91a2SCédric Le Goater /* Number of queue overflow pages */ 2192dfa91a2SCédric Le Goater #define VC_QUEUE_OVF_COUNT 6 2202dfa91a2SCédric Le Goater 2212dfa91a2SCédric Le Goater /* 2222dfa91a2SCédric Le Goater * Bits in a VSD entry. 2232dfa91a2SCédric Le Goater * 2242dfa91a2SCédric Le Goater * Note: the address is naturally aligned, we don't use a PPC_BITMASK, 2252dfa91a2SCédric Le Goater * but just a mask to apply to the address before OR'ing it in. 2262dfa91a2SCédric Le Goater * 2272dfa91a2SCédric Le Goater * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the 2282dfa91a2SCédric Le Goater * VSD and is only meant to be used in indirect mode ! 2292dfa91a2SCédric Le Goater */ 2302dfa91a2SCédric Le Goater #define VSD_MODE PPC_BITMASK(0, 1) 231*f2c1e591SCédric Le Goater #define VSD_MODE_INVALID 0 2322dfa91a2SCédric Le Goater #define VSD_MODE_SHARED 1 2332dfa91a2SCédric Le Goater #define VSD_MODE_EXCLUSIVE 2 2342dfa91a2SCédric Le Goater #define VSD_MODE_FORWARD 3 2352dfa91a2SCédric Le Goater #define VSD_ADDRESS_MASK 0x0ffffffffffff000ull 2362dfa91a2SCédric Le Goater #define VSD_MIGRATION_REG PPC_BITMASK(52, 55) 2372dfa91a2SCédric Le Goater #define VSD_INDIRECT PPC_BIT(56) 2382dfa91a2SCédric Le Goater #define VSD_TSIZE PPC_BITMASK(59, 63) 2392dfa91a2SCédric Le Goater #define VSD_FIRMWARE PPC_BIT(2) /* Read warning above */ 2402dfa91a2SCédric Le Goater 2412dfa91a2SCédric Le Goater #define VC_EQC_SYNC_MASK \ 2422dfa91a2SCédric Le Goater (VC_EQC_CONF_SYNC_IPI | \ 2432dfa91a2SCédric Le Goater VC_EQC_CONF_SYNC_HW | \ 2442dfa91a2SCédric Le Goater VC_EQC_CONF_SYNC_ESC1 | \ 2452dfa91a2SCédric Le Goater VC_EQC_CONF_SYNC_ESC2 | \ 2462dfa91a2SCédric Le Goater VC_EQC_CONF_SYNC_REDI) 2472dfa91a2SCédric Le Goater 2482dfa91a2SCédric Le Goater 2492dfa91a2SCédric Le Goater #endif /* PPC_PNV_XIVE_REGS_H */ 250