1*2dfa91a2SCédric Le Goater /* 2*2dfa91a2SCédric Le Goater * QEMU PowerPC XIVE interrupt controller model 3*2dfa91a2SCédric Le Goater * 4*2dfa91a2SCédric Le Goater * Copyright (c) 2017-2018, IBM Corporation. 5*2dfa91a2SCédric Le Goater * 6*2dfa91a2SCédric Le Goater * This code is licensed under the GPL version 2 or later. See the 7*2dfa91a2SCédric Le Goater * COPYING file in the top-level directory. 8*2dfa91a2SCédric Le Goater */ 9*2dfa91a2SCédric Le Goater 10*2dfa91a2SCédric Le Goater #ifndef PPC_PNV_XIVE_REGS_H 11*2dfa91a2SCédric Le Goater #define PPC_PNV_XIVE_REGS_H 12*2dfa91a2SCédric Le Goater 13*2dfa91a2SCédric Le Goater /* IC register offsets 0x0 - 0x400 */ 14*2dfa91a2SCédric Le Goater #define CQ_SWI_CMD_HIST 0x020 15*2dfa91a2SCédric Le Goater #define CQ_SWI_CMD_POLL 0x028 16*2dfa91a2SCédric Le Goater #define CQ_SWI_CMD_BCAST 0x030 17*2dfa91a2SCédric Le Goater #define CQ_SWI_CMD_ASSIGN 0x038 18*2dfa91a2SCédric Le Goater #define CQ_SWI_CMD_BLK_UPD 0x040 19*2dfa91a2SCédric Le Goater #define CQ_SWI_RSP 0x048 20*2dfa91a2SCédric Le Goater #define CQ_CFG_PB_GEN 0x050 21*2dfa91a2SCédric Le Goater #define CQ_INT_ADDR_OPT PPC_BITMASK(14, 15) 22*2dfa91a2SCédric Le Goater #define CQ_MSGSND 0x058 23*2dfa91a2SCédric Le Goater #define CQ_CNPM_SEL 0x078 24*2dfa91a2SCédric Le Goater #define CQ_IC_BAR 0x080 25*2dfa91a2SCédric Le Goater #define CQ_IC_BAR_VALID PPC_BIT(0) 26*2dfa91a2SCédric Le Goater #define CQ_IC_BAR_64K PPC_BIT(1) 27*2dfa91a2SCédric Le Goater #define CQ_TM1_BAR 0x90 28*2dfa91a2SCédric Le Goater #define CQ_TM2_BAR 0x0a0 29*2dfa91a2SCédric Le Goater #define CQ_TM_BAR_VALID PPC_BIT(0) 30*2dfa91a2SCédric Le Goater #define CQ_TM_BAR_64K PPC_BIT(1) 31*2dfa91a2SCédric Le Goater #define CQ_PC_BAR 0x0b0 32*2dfa91a2SCédric Le Goater #define CQ_PC_BAR_VALID PPC_BIT(0) 33*2dfa91a2SCédric Le Goater #define CQ_PC_BARM 0x0b8 34*2dfa91a2SCédric Le Goater #define CQ_PC_BARM_MASK PPC_BITMASK(26, 38) 35*2dfa91a2SCédric Le Goater #define CQ_VC_BAR 0x0c0 36*2dfa91a2SCédric Le Goater #define CQ_VC_BAR_VALID PPC_BIT(0) 37*2dfa91a2SCédric Le Goater #define CQ_VC_BARM 0x0c8 38*2dfa91a2SCédric Le Goater #define CQ_VC_BARM_MASK PPC_BITMASK(21, 37) 39*2dfa91a2SCédric Le Goater #define CQ_TAR 0x0f0 40*2dfa91a2SCédric Le Goater #define CQ_TAR_TBL_AUTOINC PPC_BIT(0) 41*2dfa91a2SCédric Le Goater #define CQ_TAR_TSEL PPC_BITMASK(12, 15) 42*2dfa91a2SCédric Le Goater #define CQ_TAR_TSEL_BLK PPC_BIT(12) 43*2dfa91a2SCédric Le Goater #define CQ_TAR_TSEL_MIG PPC_BIT(13) 44*2dfa91a2SCédric Le Goater #define CQ_TAR_TSEL_VDT PPC_BIT(14) 45*2dfa91a2SCédric Le Goater #define CQ_TAR_TSEL_EDT PPC_BIT(15) 46*2dfa91a2SCédric Le Goater #define CQ_TAR_TSEL_INDEX PPC_BITMASK(26, 31) 47*2dfa91a2SCédric Le Goater #define CQ_TDR 0x0f8 48*2dfa91a2SCédric Le Goater #define CQ_TDR_VDT_VALID PPC_BIT(0) 49*2dfa91a2SCédric Le Goater #define CQ_TDR_VDT_BLK PPC_BITMASK(11, 15) 50*2dfa91a2SCédric Le Goater #define CQ_TDR_VDT_INDEX PPC_BITMASK(28, 31) 51*2dfa91a2SCédric Le Goater #define CQ_TDR_EDT_TYPE PPC_BITMASK(0, 1) 52*2dfa91a2SCédric Le Goater #define CQ_TDR_EDT_INVALID 0 53*2dfa91a2SCédric Le Goater #define CQ_TDR_EDT_IPI 1 54*2dfa91a2SCédric Le Goater #define CQ_TDR_EDT_EQ 2 55*2dfa91a2SCédric Le Goater #define CQ_TDR_EDT_BLK PPC_BITMASK(12, 15) 56*2dfa91a2SCédric Le Goater #define CQ_TDR_EDT_INDEX PPC_BITMASK(26, 31) 57*2dfa91a2SCédric Le Goater #define CQ_PBI_CTL 0x100 58*2dfa91a2SCédric Le Goater #define CQ_PBI_PC_64K PPC_BIT(5) 59*2dfa91a2SCédric Le Goater #define CQ_PBI_VC_64K PPC_BIT(6) 60*2dfa91a2SCédric Le Goater #define CQ_PBI_LNX_TRIG PPC_BIT(7) 61*2dfa91a2SCédric Le Goater #define CQ_PBI_FORCE_TM_LOCAL PPC_BIT(22) 62*2dfa91a2SCédric Le Goater #define CQ_PBO_CTL 0x108 63*2dfa91a2SCédric Le Goater #define CQ_AIB_CTL 0x110 64*2dfa91a2SCédric Le Goater #define CQ_RST_CTL 0x118 65*2dfa91a2SCédric Le Goater #define CQ_FIRMASK 0x198 66*2dfa91a2SCédric Le Goater #define CQ_FIRMASK_AND 0x1a0 67*2dfa91a2SCédric Le Goater #define CQ_FIRMASK_OR 0x1a8 68*2dfa91a2SCédric Le Goater 69*2dfa91a2SCédric Le Goater /* PC LBS1 register offsets 0x400 - 0x800 */ 70*2dfa91a2SCédric Le Goater #define PC_TCTXT_CFG 0x400 71*2dfa91a2SCédric Le Goater #define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0) 72*2dfa91a2SCédric Le Goater #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) 73*2dfa91a2SCédric Le Goater #define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) 74*2dfa91a2SCédric Le Goater #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) 75*2dfa91a2SCédric Le Goater #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) 76*2dfa91a2SCédric Le Goater #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) 77*2dfa91a2SCédric Le Goater #define PC_TCTXT_CHIPID PPC_BITMASK(12, 15) 78*2dfa91a2SCédric Le Goater #define PC_TCTXT_INIT_AGE PPC_BITMASK(30, 31) 79*2dfa91a2SCédric Le Goater #define PC_TCTXT_TRACK 0x408 80*2dfa91a2SCédric Le Goater #define PC_TCTXT_TRACK_EN PPC_BIT(0) 81*2dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR0 0x420 82*2dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR_VALID PPC_BIT(0) 83*2dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR_THRDID PPC_BITMASK(9, 15) 84*2dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR1 0x428 85*2dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR2 0x430 86*2dfa91a2SCédric Le Goater #define PC_TCTXT_INDIR3 0x438 87*2dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG0 0x440 88*2dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG0_SET 0x448 89*2dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG0_CLR 0x450 90*2dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG1 0x460 91*2dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG1_SET 0x468 92*2dfa91a2SCédric Le Goater #define PC_THREAD_EN_REG1_CLR 0x470 93*2dfa91a2SCédric Le Goater #define PC_GLOBAL_CONFIG 0x480 94*2dfa91a2SCédric Le Goater #define PC_GCONF_INDIRECT PPC_BIT(32) 95*2dfa91a2SCédric Le Goater #define PC_GCONF_CHIPID_OVR PPC_BIT(40) 96*2dfa91a2SCédric Le Goater #define PC_GCONF_CHIPID PPC_BITMASK(44, 47) 97*2dfa91a2SCédric Le Goater #define PC_VSD_TABLE_ADDR 0x488 98*2dfa91a2SCédric Le Goater #define PC_VSD_TABLE_DATA 0x490 99*2dfa91a2SCédric Le Goater #define PC_AT_KILL 0x4b0 100*2dfa91a2SCédric Le Goater #define PC_AT_KILL_VALID PPC_BIT(0) 101*2dfa91a2SCédric Le Goater #define PC_AT_KILL_BLOCK_ID PPC_BITMASK(27, 31) 102*2dfa91a2SCédric Le Goater #define PC_AT_KILL_OFFSET PPC_BITMASK(48, 60) 103*2dfa91a2SCédric Le Goater #define PC_AT_KILL_MASK 0x4b8 104*2dfa91a2SCédric Le Goater 105*2dfa91a2SCédric Le Goater /* PC LBS2 register offsets */ 106*2dfa91a2SCédric Le Goater #define PC_VPC_CACHE_ENABLE 0x708 107*2dfa91a2SCédric Le Goater #define PC_VPC_CACHE_EN_MASK PPC_BITMASK(0, 31) 108*2dfa91a2SCédric Le Goater #define PC_VPC_SCRUB_TRIG 0x710 109*2dfa91a2SCédric Le Goater #define PC_VPC_SCRUB_MASK 0x718 110*2dfa91a2SCédric Le Goater #define PC_SCRUB_VALID PPC_BIT(0) 111*2dfa91a2SCédric Le Goater #define PC_SCRUB_WANT_DISABLE PPC_BIT(1) 112*2dfa91a2SCédric Le Goater #define PC_SCRUB_WANT_INVAL PPC_BIT(2) 113*2dfa91a2SCédric Le Goater #define PC_SCRUB_BLOCK_ID PPC_BITMASK(27, 31) 114*2dfa91a2SCédric Le Goater #define PC_SCRUB_OFFSET PPC_BITMASK(45, 63) 115*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_SPEC 0x738 116*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_CONFLICT PPC_BIT(0) 117*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_FULL PPC_BIT(8) 118*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_BLOCKID PPC_BITMASK(27, 31) 119*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_OFFSET PPC_BITMASK(45, 63) 120*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT0 0x740 121*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT1 0x748 122*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT2 0x750 123*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT3 0x758 124*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT4 0x760 125*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT5 0x768 126*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT6 0x770 127*2dfa91a2SCédric Le Goater #define PC_VPC_CWATCH_DAT7 0x778 128*2dfa91a2SCédric Le Goater 129*2dfa91a2SCédric Le Goater /* VC0 register offsets 0x800 - 0xFFF */ 130*2dfa91a2SCédric Le Goater #define VC_GLOBAL_CONFIG 0x800 131*2dfa91a2SCédric Le Goater #define VC_GCONF_INDIRECT PPC_BIT(32) 132*2dfa91a2SCédric Le Goater #define VC_VSD_TABLE_ADDR 0x808 133*2dfa91a2SCédric Le Goater #define VC_VSD_TABLE_DATA 0x810 134*2dfa91a2SCédric Le Goater #define VC_IVE_ISB_BLOCK_MODE 0x818 135*2dfa91a2SCédric Le Goater #define VC_EQD_BLOCK_MODE 0x820 136*2dfa91a2SCédric Le Goater #define VC_VPS_BLOCK_MODE 0x828 137*2dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_IPI 0x840 138*2dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_MEMB_EN PPC_BIT(45) 139*2dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_MEMB_SZ PPC_BITMASK(46, 51) 140*2dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_HW 0x848 141*2dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_CASCADE1 0x850 142*2dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_CASCADE2 0x858 143*2dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_REDIST 0x860 144*2dfa91a2SCédric Le Goater #define VC_IRQ_CONFIG_IPI_CASC 0x868 145*2dfa91a2SCédric Le Goater #define VC_AIB_TX_ORDER_TAG2_REL_TF PPC_BIT(20) 146*2dfa91a2SCédric Le Goater #define VC_AIB_TX_ORDER_TAG2 0x890 147*2dfa91a2SCédric Le Goater #define VC_AT_MACRO_KILL 0x8b0 148*2dfa91a2SCédric Le Goater #define VC_AT_MACRO_KILL_MASK 0x8b8 149*2dfa91a2SCédric Le Goater #define VC_KILL_VALID PPC_BIT(0) 150*2dfa91a2SCédric Le Goater #define VC_KILL_TYPE PPC_BITMASK(14, 15) 151*2dfa91a2SCédric Le Goater #define VC_KILL_IRQ 0 152*2dfa91a2SCédric Le Goater #define VC_KILL_IVC 1 153*2dfa91a2SCédric Le Goater #define VC_KILL_SBC 2 154*2dfa91a2SCédric Le Goater #define VC_KILL_EQD 3 155*2dfa91a2SCédric Le Goater #define VC_KILL_BLOCK_ID PPC_BITMASK(27, 31) 156*2dfa91a2SCédric Le Goater #define VC_KILL_OFFSET PPC_BITMASK(48, 60) 157*2dfa91a2SCédric Le Goater #define VC_EQC_CACHE_ENABLE 0x908 158*2dfa91a2SCédric Le Goater #define VC_EQC_CACHE_EN_MASK PPC_BITMASK(0, 15) 159*2dfa91a2SCédric Le Goater #define VC_EQC_SCRUB_TRIG 0x910 160*2dfa91a2SCédric Le Goater #define VC_EQC_SCRUB_MASK 0x918 161*2dfa91a2SCédric Le Goater #define VC_EQC_CONFIG 0x920 162*2dfa91a2SCédric Le Goater #define X_VC_EQC_CONFIG 0x214 /* XSCOM register */ 163*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_SYNC_IPI PPC_BIT(32) 164*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_SYNC_HW PPC_BIT(33) 165*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_SYNC_ESC1 PPC_BIT(34) 166*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_SYNC_ESC2 PPC_BIT(35) 167*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_SYNC_REDI PPC_BIT(36) 168*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_EQP_INTERLEAVE PPC_BIT(38) 169*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_ENABLE_END_s_BIT PPC_BIT(39) 170*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_ENABLE_END_u_BIT PPC_BIT(40) 171*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_ENABLE_END_c_BIT PPC_BIT(41) 172*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_ENABLE_MORE_QSZ PPC_BIT(42) 173*2dfa91a2SCédric Le Goater #define VC_EQC_CONF_SKIP_ESCALATE PPC_BIT(43) 174*2dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_SPEC 0x928 175*2dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_CONFLICT PPC_BIT(0) 176*2dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_FULL PPC_BIT(8) 177*2dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_BLOCKID PPC_BITMASK(28, 31) 178*2dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_OFFSET PPC_BITMASK(40, 63) 179*2dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_DAT0 0x930 180*2dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_DAT1 0x938 181*2dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_DAT2 0x940 182*2dfa91a2SCédric Le Goater #define VC_EQC_CWATCH_DAT3 0x948 183*2dfa91a2SCédric Le Goater #define VC_IVC_SCRUB_TRIG 0x990 184*2dfa91a2SCédric Le Goater #define VC_IVC_SCRUB_MASK 0x998 185*2dfa91a2SCédric Le Goater #define VC_SBC_SCRUB_TRIG 0xa10 186*2dfa91a2SCédric Le Goater #define VC_SBC_SCRUB_MASK 0xa18 187*2dfa91a2SCédric Le Goater #define VC_SCRUB_VALID PPC_BIT(0) 188*2dfa91a2SCédric Le Goater #define VC_SCRUB_WANT_DISABLE PPC_BIT(1) 189*2dfa91a2SCédric Le Goater #define VC_SCRUB_WANT_INVAL PPC_BIT(2) /* EQC and SBC only */ 190*2dfa91a2SCédric Le Goater #define VC_SCRUB_BLOCK_ID PPC_BITMASK(28, 31) 191*2dfa91a2SCédric Le Goater #define VC_SCRUB_OFFSET PPC_BITMASK(40, 63) 192*2dfa91a2SCédric Le Goater #define VC_IVC_CACHE_ENABLE 0x988 193*2dfa91a2SCédric Le Goater #define VC_IVC_CACHE_EN_MASK PPC_BITMASK(0, 15) 194*2dfa91a2SCédric Le Goater #define VC_SBC_CACHE_ENABLE 0xa08 195*2dfa91a2SCédric Le Goater #define VC_SBC_CACHE_EN_MASK PPC_BITMASK(0, 15) 196*2dfa91a2SCédric Le Goater #define VC_IVC_CACHE_SCRUB_TRIG 0x990 197*2dfa91a2SCédric Le Goater #define VC_IVC_CACHE_SCRUB_MASK 0x998 198*2dfa91a2SCédric Le Goater #define VC_SBC_CACHE_ENABLE 0xa08 199*2dfa91a2SCédric Le Goater #define VC_SBC_CACHE_SCRUB_TRIG 0xa10 200*2dfa91a2SCédric Le Goater #define VC_SBC_CACHE_SCRUB_MASK 0xa18 201*2dfa91a2SCédric Le Goater #define VC_SBC_CONFIG 0xa20 202*2dfa91a2SCédric Le Goater #define VC_SBC_CONF_CPLX_CIST PPC_BIT(44) 203*2dfa91a2SCédric Le Goater #define VC_SBC_CONF_CIST_BOTH PPC_BIT(45) 204*2dfa91a2SCédric Le Goater #define VC_SBC_CONF_NO_UPD_PRF PPC_BIT(59) 205*2dfa91a2SCédric Le Goater 206*2dfa91a2SCédric Le Goater /* VC1 register offsets */ 207*2dfa91a2SCédric Le Goater 208*2dfa91a2SCédric Le Goater /* VSD Table address register definitions (shared) */ 209*2dfa91a2SCédric Le Goater #define VST_ADDR_AUTOINC PPC_BIT(0) 210*2dfa91a2SCédric Le Goater #define VST_TABLE_SELECT PPC_BITMASK(13, 15) 211*2dfa91a2SCédric Le Goater #define VST_TSEL_IVT 0 212*2dfa91a2SCédric Le Goater #define VST_TSEL_SBE 1 213*2dfa91a2SCédric Le Goater #define VST_TSEL_EQDT 2 214*2dfa91a2SCédric Le Goater #define VST_TSEL_VPDT 3 215*2dfa91a2SCédric Le Goater #define VST_TSEL_IRQ 4 /* VC only */ 216*2dfa91a2SCédric Le Goater #define VST_TABLE_BLOCK PPC_BITMASK(27, 31) 217*2dfa91a2SCédric Le Goater 218*2dfa91a2SCédric Le Goater /* Number of queue overflow pages */ 219*2dfa91a2SCédric Le Goater #define VC_QUEUE_OVF_COUNT 6 220*2dfa91a2SCédric Le Goater 221*2dfa91a2SCédric Le Goater /* 222*2dfa91a2SCédric Le Goater * Bits in a VSD entry. 223*2dfa91a2SCédric Le Goater * 224*2dfa91a2SCédric Le Goater * Note: the address is naturally aligned, we don't use a PPC_BITMASK, 225*2dfa91a2SCédric Le Goater * but just a mask to apply to the address before OR'ing it in. 226*2dfa91a2SCédric Le Goater * 227*2dfa91a2SCédric Le Goater * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the 228*2dfa91a2SCédric Le Goater * VSD and is only meant to be used in indirect mode ! 229*2dfa91a2SCédric Le Goater */ 230*2dfa91a2SCédric Le Goater #define VSD_MODE PPC_BITMASK(0, 1) 231*2dfa91a2SCédric Le Goater #define VSD_MODE_SHARED 1 232*2dfa91a2SCédric Le Goater #define VSD_MODE_EXCLUSIVE 2 233*2dfa91a2SCédric Le Goater #define VSD_MODE_FORWARD 3 234*2dfa91a2SCédric Le Goater #define VSD_ADDRESS_MASK 0x0ffffffffffff000ull 235*2dfa91a2SCédric Le Goater #define VSD_MIGRATION_REG PPC_BITMASK(52, 55) 236*2dfa91a2SCédric Le Goater #define VSD_INDIRECT PPC_BIT(56) 237*2dfa91a2SCédric Le Goater #define VSD_TSIZE PPC_BITMASK(59, 63) 238*2dfa91a2SCédric Le Goater #define VSD_FIRMWARE PPC_BIT(2) /* Read warning above */ 239*2dfa91a2SCédric Le Goater 240*2dfa91a2SCédric Le Goater #define VC_EQC_SYNC_MASK \ 241*2dfa91a2SCédric Le Goater (VC_EQC_CONF_SYNC_IPI | \ 242*2dfa91a2SCédric Le Goater VC_EQC_CONF_SYNC_HW | \ 243*2dfa91a2SCédric Le Goater VC_EQC_CONF_SYNC_ESC1 | \ 244*2dfa91a2SCédric Le Goater VC_EQC_CONF_SYNC_ESC2 | \ 245*2dfa91a2SCédric Le Goater VC_EQC_CONF_SYNC_REDI) 246*2dfa91a2SCédric Le Goater 247*2dfa91a2SCédric Le Goater 248*2dfa91a2SCédric Le Goater #endif /* PPC_PNV_XIVE_REGS_H */ 249