1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PPC_PNV_XIVE2_REGS_H 11 #define PPC_PNV_XIVE2_REGS_H 12 13 /* 14 * CQ Common Queue (PowerBus bridge) Registers 15 */ 16 17 /* XIVE2 Capabilities */ 18 #define X_CQ_XIVE_CAP 0x02 19 #define CQ_XIVE_CAP 0x010 20 #define CQ_XIVE_CAP_VERSION PPC_BITMASK(0, 3) 21 /* 4:6 reserved */ 22 #define CQ_XIVE_CAP_USER_INT_PRIO PPC_BITMASK(8, 9) 23 #define CQ_XIVE_CAP_USER_INT_PRIO_1 0 24 #define CQ_XIVE_CAP_USER_INT_PRIO_1_2 1 25 #define CQ_XIVE_CAP_USER_INT_PRIO_1_4 2 26 #define CQ_XIVE_CAP_USER_INT_PRIO_1_8 3 27 #define CQ_XIVE_CAP_VP_INT_PRIO PPC_BITMASK(10, 11) 28 #define CQ_XIVE_CAP_VP_INT_PRIO_1_8 0 29 #define CQ_XIVE_CAP_VP_INT_PRIO_2_8 1 30 #define CQ_XIVE_CAP_VP_INT_PRIO_4_8 2 31 #define CQ_XIVE_CAP_VP_INT_PRIO_8 3 32 #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13) 33 34 /* XIVE2 Configuration */ 35 #define X_CQ_XIVE_CFG 0x03 36 #define CQ_XIVE_CFG 0x018 37 38 /* 0:7 reserved */ 39 #define CQ_XIVE_CFG_USER_INT_PRIO PPC_BITMASK(8, 9) 40 #define CQ_XIVE_CFG_VP_INT_PRIO PPC_BITMASK(10, 11) 41 #define CQ_XIVE_CFG_INT_PRIO_1 0 42 #define CQ_XIVE_CFG_INT_PRIO_2 1 43 #define CQ_XIVE_CFG_INT_PRIO_4 2 44 #define CQ_XIVE_CFG_INT_PRIO_8 3 45 #define CQ_XIVE_CFG_BLOCK_ID_WIDTH PPC_BITMASK(12, 13) 46 #define CQ_XIVE_CFG_BLOCK_ID_4BITS 0 47 #define CQ_XIVE_CFG_BLOCK_ID_5BITS 1 48 #define CQ_XIVE_CFG_BLOCK_ID_6BITS 2 49 #define CQ_XIVE_CFG_BLOCK_ID_7BITS 3 50 #define CQ_XIVE_CFG_HYP_HARD_RANGE PPC_BITMASK(14, 15) 51 #define CQ_XIVE_CFG_THREADID_7BITS 0 52 #define CQ_XIVE_CFG_THREADID_8BITS 1 53 #define CQ_XIVE_CFG_THREADID_9BITS 2 54 #define CQ_XIVE_CFG_THREADID_10BITs 3 55 #define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16) 56 #define CQ_XIVE_CFG_HYP_HARD_BLOCK_ID PPC_BITMASK(17, 23) 57 58 /* Interrupt Controller Base Address Register - 512 pages (32M) */ 59 #define X_CQ_IC_BAR 0x08 60 #define CQ_IC_BAR 0x040 61 #define CQ_IC_BAR_VALID PPC_BIT(0) 62 #define CQ_IC_BAR_64K PPC_BIT(1) 63 /* 2:7 reserved */ 64 #define CQ_IC_BAR_ADDR PPC_BITMASK(8, 42) 65 /* 43:63 reserved */ 66 67 /* Thread Management Base Address Register - 4 pages */ 68 #define X_CQ_TM_BAR 0x09 69 #define CQ_TM_BAR 0x048 70 #define CQ_TM_BAR_VALID PPC_BIT(0) 71 #define CQ_TM_BAR_64K PPC_BIT(1) 72 #define CQ_TM_BAR_ADDR PPC_BITMASK(8, 49) 73 74 /* ESB Base Address Register */ 75 #define X_CQ_ESB_BAR 0x0A 76 #define CQ_ESB_BAR 0x050 77 #define CQ_BAR_VALID PPC_BIT(0) 78 #define CQ_BAR_64K PPC_BIT(1) 79 /* 2:7 reserved */ 80 #define CQ_BAR_ADDR PPC_BITMASK(8, 39) 81 #define CQ_BAR_SET_DIV PPC_BITMASK(56, 58) 82 #define CQ_BAR_RANGE PPC_BITMASK(59, 63) 83 /* 0 (16M) - 16 (16T) */ 84 85 /* END Base Address Register */ 86 #define X_CQ_END_BAR 0x0B 87 #define CQ_END_BAR 0x058 88 89 /* NVPG Base Address Register */ 90 #define X_CQ_NVPG_BAR 0x0C 91 #define CQ_NVPG_BAR 0x060 92 93 /* NVC Base Address Register */ 94 #define X_CQ_NVC_BAR 0x0D 95 #define CQ_NVC_BAR 0x068 96 97 /* Table Address Register */ 98 #define X_CQ_TAR 0x0E 99 #define CQ_TAR 0x070 100 #define CQ_TAR_AUTOINC PPC_BIT(0) 101 #define CQ_TAR_SELECT PPC_BITMASK(12, 15) 102 #define CQ_TAR_ESB 0 /* 0 - 15 */ 103 #define CQ_TAR_END 2 /* 0 - 15 */ 104 #define CQ_TAR_NVPG 3 /* 0 - 15 */ 105 #define CQ_TAR_NVC 5 /* 0 - 15 */ 106 #define CQ_TAR_ENTRY_SELECT PPC_BITMASK(28, 31) 107 108 /* Table Data Register */ 109 #define X_CQ_TDR 0x0F 110 #define CQ_TDR 0x078 111 /* for the NVPG, NVC, ESB, END Set Translation Tables */ 112 #define CQ_TDR_VALID PPC_BIT(0) 113 #define CQ_TDR_BLOCK_ID PPC_BITMASK(60, 63) 114 115 /* 116 * Processor Cores Enabled for MsgSnd 117 * Identifies which of the 32 possible core chiplets are enabled and 118 * available to receive the MsgSnd command 119 */ 120 #define X_CQ_MSGSND 0x10 121 #define CQ_MSGSND 0x080 122 123 /* Interrupt Unit Reset Control */ 124 #define X_CQ_RST_CTL 0x12 125 #define CQ_RST_CTL 0x090 126 #define CQ_RST_SYNC_RESET PPC_BIT(0) /* Write Only */ 127 #define CQ_RST_QUIESCE_PB PPC_BIT(1) /* RW */ 128 #define CQ_RST_MASTER_IDLE PPC_BIT(2) /* Read Only */ 129 #define CQ_RST_SAVE_IDLE PPC_BIT(3) /* Read Only */ 130 #define CQ_RST_PB_BAR_RESET PPC_BIT(4) /* Write Only */ 131 132 /* PowerBus General Configuration */ 133 #define X_CQ_CFG_PB_GEN 0x14 134 #define CQ_CFG_PB_GEN 0x0A0 135 #define CQ_CFG_PB_GEN_PB_INIT PPC_BIT(45) 136 137 /* 138 * FIR 139 * (And-Mask) 140 * (Or-Mask) 141 */ 142 #define X_CQ_FIR 0x30 143 #define X_CQ_FIR_AND 0x31 144 #define X_CQ_FIR_OR 0x32 145 #define CQ_FIR 0x180 146 #define CQ_FIR_AND 0x188 147 #define CQ_FIR_OR 0x190 148 #define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19) 149 #define CQ_FIR_VC_INFO_ERROR_0_2 PPC_BITMASK(61, 63) 150 151 /* 152 * FIR Mask 153 * (And-Mask) 154 * (Or-Mask) 155 */ 156 #define X_CQ_FIRMASK 0x33 157 #define X_CQ_FIRMASK_AND 0x34 158 #define X_CQ_FIRMASK_OR 0x35 159 #define CQ_FIRMASK 0x198 160 #define CQ_FIRMASK_AND 0x1A0 161 #define CQ_FIRMASK_OR 0x1A8 162 163 /* 164 * VC0 165 */ 166 167 /* VSD table address */ 168 #define X_VC_VSD_TABLE_ADDR 0x100 169 #define VC_VSD_TABLE_ADDR 0x000 170 #define VC_VSD_TABLE_AUTOINC PPC_BIT(0) 171 #define VC_VSD_TABLE_SELECT PPC_BITMASK(12, 15) 172 #define VC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31) 173 174 /* VSD table data */ 175 #define X_VC_VSD_TABLE_DATA 0x101 176 #define VC_VSD_TABLE_DATA 0x008 177 178 /* AIB AT macro indirect kill */ 179 #define X_VC_AT_MACRO_KILL 0x102 180 #define VC_AT_MACRO_KILL 0x010 181 #define VC_AT_MACRO_KILL_VALID PPC_BIT(0) 182 #define VC_AT_MACRO_KILL_VSD PPC_BITMASK(12, 15) 183 #define VC_AT_MACRO_KILL_BLOCK_ID PPC_BITMASK(28, 31) 184 #define VC_AT_MACRO_KILL_OFFSET PPC_BITMASK(48, 60) 185 186 /* AIB AT macro indirect kill mask (same bit definitions) */ 187 #define X_VC_AT_MACRO_KILL_MASK 0x103 188 #define VC_AT_MACRO_KILL_MASK 0x018 189 190 /* Remote IRQs and ERQs configuration [n] (n = 0:6) */ 191 #define X_VC_QUEUES_CFG_REM0 0x117 192 193 #define VC_QUEUES_CFG_REM0 0x0B8 194 #define VC_QUEUES_CFG_REM1 0x0C0 195 #define VC_QUEUES_CFG_REM2 0x0C8 196 #define VC_QUEUES_CFG_REM3 0x0D0 197 #define VC_QUEUES_CFG_REM4 0x0D8 198 #define VC_QUEUES_CFG_REM5 0x0E0 199 #define VC_QUEUES_CFG_REM6 0x0E8 200 #define VC_QUEUES_CFG_MEMB_EN PPC_BIT(38) 201 #define VC_QUEUES_CFG_MEMB_SZ PPC_BITMASK(42, 47) 202 203 /* 204 * VC1 205 */ 206 207 /* ESBC cache flush control trigger */ 208 #define X_VC_ESBC_FLUSH_CTRL 0x140 209 #define VC_ESBC_FLUSH_CTRL 0x200 210 #define VC_ESBC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) 211 #define VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) 212 213 /* ESBC cache flush poll trigger */ 214 #define X_VC_ESBC_FLUSH_POLL 0x141 215 #define VC_ESBC_FLUSH_POLL 0x208 216 #define VC_ESBC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3) 217 #define VC_ESBC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31) /* 28-bit */ 218 #define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35) 219 #define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */ 220 221 /* EASC flush control register */ 222 #define X_VC_EASC_FLUSH_CTRL 0x160 223 #define VC_EASC_FLUSH_CTRL 0x300 224 #define VC_EASC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) 225 #define VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) 226 227 /* EASC flush poll register */ 228 #define X_VC_EASC_FLUSH_POLL 0x161 229 #define VC_EASC_FLUSH_POLL 0x308 230 #define VC_EASC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3) 231 #define VC_EASC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31) /* 28-bit */ 232 #define VC_EASC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35) 233 #define VC_EASC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */ 234 235 /* 236 * VC2 237 */ 238 239 /* ENDC flush control register */ 240 #define X_VC_ENDC_FLUSH_CTRL 0x180 241 #define VC_ENDC_FLUSH_CTRL 0x400 242 #define VC_ENDC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) 243 #define VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) 244 #define VC_ENDC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3) 245 #define VC_ENDC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7) 246 247 /* ENDC flush poll register */ 248 #define X_VC_ENDC_FLUSH_POLL 0x181 249 #define VC_ENDC_FLUSH_POLL 0x408 250 #define VC_ENDC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4, 7) 251 #define VC_ENDC_FLUSH_POLL_OFFSET PPC_BITMASK(8, 31) /* 24-bit */ 252 #define VC_ENDC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36, 39) 253 #define VC_ENDC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40, 63) /* 24-bit */ 254 255 /* ENDC Sync done */ 256 #define X_VC_ENDC_SYNC_DONE 0x184 257 #define VC_ENDC_SYNC_DONE 0x420 258 #define VC_ENDC_SYNC_POLL_DONE PPC_BITMASK(0, 6) 259 #define VC_ENDC_SYNC_QUEUE_IPI PPC_BIT(0) 260 #define VC_ENDC_SYNC_QUEUE_HWD PPC_BIT(1) 261 #define VC_ENDC_SYNC_QUEUE_NXC PPC_BIT(2) 262 #define VC_ENDC_SYNC_QUEUE_INT PPC_BIT(3) 263 #define VC_ENDC_SYNC_QUEUE_OS PPC_BIT(4) 264 #define VC_ENDC_SYNC_QUEUE_POOL PPC_BIT(5) 265 #define VC_ENDC_SYNC_QUEUE_HARD PPC_BIT(6) 266 #define VC_QUEUE_COUNT 7 267 268 /* ENDC cache watch specification 0 */ 269 #define X_VC_ENDC_WATCH0_SPEC 0x1A0 270 #define VC_ENDC_WATCH0_SPEC 0x500 271 #define VC_ENDC_WATCH_CONFLICT PPC_BIT(0) 272 #define VC_ENDC_WATCH_FULL PPC_BIT(8) 273 #define VC_ENDC_WATCH_BLOCK_ID PPC_BITMASK(28, 31) 274 #define VC_ENDC_WATCH_INDEX PPC_BITMASK(40, 63) 275 276 /* ENDC cache watch data 0 */ 277 #define X_VC_ENDC_WATCH0_DATA0 0x1A4 278 #define X_VC_ENDC_WATCH0_DATA1 0x1A5 279 #define X_VC_ENDC_WATCH0_DATA2 0x1A6 280 #define X_VC_ENDC_WATCH0_DATA3 0x1A7 281 282 #define VC_ENDC_WATCH0_DATA0 0x520 283 #define VC_ENDC_WATCH0_DATA1 0x528 284 #define VC_ENDC_WATCH0_DATA2 0x530 285 #define VC_ENDC_WATCH0_DATA3 0x538 286 287 /* 288 * PC LSB1 289 */ 290 291 /* VSD table address register */ 292 #define X_PC_VSD_TABLE_ADDR 0x200 293 #define PC_VSD_TABLE_ADDR 0x000 294 #define PC_VSD_TABLE_AUTOINC PPC_BIT(0) 295 #define PC_VSD_TABLE_SELECT PPC_BITMASK(12, 15) 296 #define PC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31) 297 298 /* VSD table data register */ 299 #define X_PC_VSD_TABLE_DATA 0x201 300 #define PC_VSD_TABLE_DATA 0x008 301 302 /* AT indirect kill register */ 303 #define X_PC_AT_KILL 0x202 304 #define PC_AT_KILL 0x010 305 #define PC_AT_KILL_VALID PPC_BIT(0) 306 #define PC_AT_KILL_VSD_TYPE PPC_BITMASK(24, 27) 307 /* Only NVP, NVG, NVC */ 308 #define PC_AT_KILL_BLOCK_ID PPC_BITMASK(28, 31) 309 #define PC_AT_KILL_OFFSET PPC_BITMASK(48, 60) 310 311 /* AT indirect kill mask register */ 312 #define X_PC_AT_KILL_MASK 0x203 313 #define PC_AT_KILL_MASK 0x018 314 #define PC_AT_KILL_MASK_VSD_TYPE PPC_BITMASK(24, 27) 315 #define PC_AT_KILL_MASK_BLOCK_ID PPC_BITMASK(28, 31) 316 #define PC_AT_KILL_MASK_OFFSET PPC_BITMASK(48, 60) 317 318 /* 319 * PC LSB2 320 */ 321 322 /* NxC Cache flush control */ 323 #define X_PC_NXC_FLUSH_CTRL 0x280 324 #define PC_NXC_FLUSH_CTRL 0x400 325 #define PC_NXC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) 326 #define PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) 327 #define PC_NXC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3) 328 #define PC_NXC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7) 329 330 /* NxC Cache flush poll */ 331 #define X_PC_NXC_FLUSH_POLL 0x281 332 #define PC_NXC_FLUSH_POLL 0x408 333 #define PC_NXC_FLUSH_POLL_NXC_TYPE PPC_BITMASK(2, 3) 334 #define PC_NXC_FLUSH_POLL_NXC_TYPE_NVP 0 335 #define PC_NXC_FLUSH_POLL_NXC_TYPE_NVG 2 336 #define PC_NXC_FLUSH_POLL_NXC_TYPE_NVC 3 337 #define PC_NXC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4, 7) 338 #define PC_NXC_FLUSH_POLL_OFFSET PPC_BITMASK(8, 31) /* 24-bit */ 339 #define PC_NXC_FLUSH_POLL_NXC_TYPE_MASK PPC_BITMASK(34, 35) /* 0: Ign */ 340 #define PC_NXC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36, 39) 341 #define PC_NXC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40, 63) /* 24-bit */ 342 343 /* NxC Cache Watch 0 Specification */ 344 #define X_PC_NXC_WATCH0_SPEC 0x2A0 345 #define PC_NXC_WATCH0_SPEC 0x500 346 #define PC_NXC_WATCH_CONFLICT PPC_BIT(0) 347 #define PC_NXC_WATCH_FULL PPC_BIT(8) 348 #define PC_NXC_WATCH_NXC_TYPE PPC_BITMASK(26, 27) 349 #define PC_NXC_WATCH_NXC_NVP 0 350 #define PC_NXC_WATCH_NXC_NVG 2 351 #define PC_NXC_WATCH_NXC_NVC 3 352 #define PC_NXC_WATCH_BLOCK_ID PPC_BITMASK(28, 31) 353 #define PC_NXC_WATCH_INDEX PPC_BITMASK(40, 63) 354 355 /* NxC Cache Watch 0 Data */ 356 #define X_PC_NXC_WATCH0_DATA0 0x2A4 357 #define X_PC_NXC_WATCH0_DATA1 0x2A5 358 #define X_PC_NXC_WATCH0_DATA2 0x2A6 359 #define X_PC_NXC_WATCH0_DATA3 0x2A7 360 361 #define PC_NXC_WATCH0_DATA0 0x520 362 #define PC_NXC_WATCH0_DATA1 0x528 363 #define PC_NXC_WATCH0_DATA2 0x530 364 #define PC_NXC_WATCH0_DATA3 0x538 365 366 /* 367 * TCTXT Registers 368 */ 369 370 /* Physical Thread Enable0 register */ 371 #define X_TCTXT_EN0 0x300 372 #define TCTXT_EN0 0x000 373 374 /* Physical Thread Enable0 Set register */ 375 #define X_TCTXT_EN0_SET 0x302 376 #define TCTXT_EN0_SET 0x010 377 378 /* Physical Thread Enable0 Reset register */ 379 #define X_TCTXT_EN0_RESET 0x303 380 #define TCTXT_EN0_RESET 0x018 381 382 /* Physical Thread Enable1 register */ 383 #define X_TCTXT_EN1 0x304 384 #define TCTXT_EN1 0x020 385 386 /* Physical Thread Enable1 Set register */ 387 #define X_TCTXT_EN1_SET 0x306 388 #define TCTXT_EN1_SET 0x030 389 390 /* Physical Thread Enable1 Reset register */ 391 #define X_TCTXT_EN1_RESET 0x307 392 #define TCTXT_EN1_RESET 0x038 393 394 /* 395 * VSD Tables 396 */ 397 #define VST_ESB 0 398 #define VST_EAS 1 /* No used by PC */ 399 #define VST_END 2 400 #define VST_NVP 3 401 #define VST_NVG 4 402 #define VST_NVC 5 403 #define VST_IC 6 /* No used by PC */ 404 #define VST_SYNC 7 405 #define VST_ERQ 8 /* No used by PC */ 406 407 /* 408 * Bits in a VSD entry. 409 * 410 * Note: the address is naturally aligned, we don't use a PPC_BITMASK, 411 * but just a mask to apply to the address before OR'ing it in. 412 * 413 * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the 414 * VSD and is only meant to be used in indirect mode ! 415 */ 416 #define VSD_MODE PPC_BITMASK(0, 1) 417 #define VSD_MODE_SHARED 1 418 #define VSD_MODE_EXCLUSIVE 2 419 #define VSD_MODE_FORWARD 3 420 #define VSD_FIRMWARE PPC_BIT(2) /* Read warning */ 421 #define VSD_FIRMWARE2 PPC_BIT(3) /* unused */ 422 #define VSD_RESERVED PPC_BITMASK(4, 7) /* P10 reserved */ 423 #define VSD_ADDRESS_MASK 0x00fffffffffff000ull 424 #define VSD_MIGRATION_REG PPC_BITMASK(52, 55) 425 #define VSD_INDIRECT PPC_BIT(56) 426 #define VSD_TSIZE PPC_BITMASK(59, 63) 427 428 #endif /* PPC_PNV_XIVE2_REGS_H */ 429