1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PPC_PNV_XIVE2_REGS_H 11 #define PPC_PNV_XIVE2_REGS_H 12 13 /* 14 * CQ Common Queue (PowerBus bridge) Registers 15 */ 16 17 /* XIVE2 Capabilities */ 18 #define X_CQ_XIVE_CAP 0x02 19 #define CQ_XIVE_CAP 0x010 20 #define CQ_XIVE_CAP_VERSION PPC_BITMASK(0, 3) 21 /* 4:6 reserved */ 22 #define CQ_XIVE_CAP_USER_INT_PRIO PPC_BITMASK(8, 9) 23 #define CQ_XIVE_CAP_USER_INT_PRIO_1 0 24 #define CQ_XIVE_CAP_USER_INT_PRIO_1_2 1 25 #define CQ_XIVE_CAP_USER_INT_PRIO_1_4 2 26 #define CQ_XIVE_CAP_USER_INT_PRIO_1_8 3 27 #define CQ_XIVE_CAP_VP_INT_PRIO PPC_BITMASK(10, 11) 28 #define CQ_XIVE_CAP_VP_INT_PRIO_1_8 0 29 #define CQ_XIVE_CAP_VP_INT_PRIO_2_8 1 30 #define CQ_XIVE_CAP_VP_INT_PRIO_4_8 2 31 #define CQ_XIVE_CAP_VP_INT_PRIO_8 3 32 #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13) 33 34 #define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56) 35 #define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57) 36 #define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58) 37 #define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59) 38 39 /* XIVE2 Configuration */ 40 #define X_CQ_XIVE_CFG 0x03 41 #define CQ_XIVE_CFG 0x018 42 43 /* 0:7 reserved */ 44 #define CQ_XIVE_CFG_USER_INT_PRIO PPC_BITMASK(8, 9) 45 #define CQ_XIVE_CFG_VP_INT_PRIO PPC_BITMASK(10, 11) 46 #define CQ_XIVE_CFG_INT_PRIO_1 0 47 #define CQ_XIVE_CFG_INT_PRIO_2 1 48 #define CQ_XIVE_CFG_INT_PRIO_4 2 49 #define CQ_XIVE_CFG_INT_PRIO_8 3 50 #define CQ_XIVE_CFG_BLOCK_ID_WIDTH PPC_BITMASK(12, 13) 51 #define CQ_XIVE_CFG_BLOCK_ID_4BITS 0 52 #define CQ_XIVE_CFG_BLOCK_ID_5BITS 1 53 #define CQ_XIVE_CFG_BLOCK_ID_6BITS 2 54 #define CQ_XIVE_CFG_BLOCK_ID_7BITS 3 55 #define CQ_XIVE_CFG_HYP_HARD_RANGE PPC_BITMASK(14, 15) 56 #define CQ_XIVE_CFG_THREADID_7BITS 0 57 #define CQ_XIVE_CFG_THREADID_8BITS 1 58 #define CQ_XIVE_CFG_THREADID_9BITS 2 59 #define CQ_XIVE_CFG_THREADID_10BITs 3 60 #define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16) 61 #define CQ_XIVE_CFG_HYP_HARD_BLOCK_ID PPC_BITMASK(17, 23) 62 63 #define CQ_XIVE_CFG_GEN1_TIMA_OS PPC_BIT(24) 64 #define CQ_XIVE_CFG_GEN1_TIMA_HYP PPC_BIT(25) 65 #define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */ 66 #define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */ 67 #define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28) 68 69 /* Interrupt Controller Base Address Register - 512 pages (32M) */ 70 #define X_CQ_IC_BAR 0x08 71 #define CQ_IC_BAR 0x040 72 #define CQ_IC_BAR_VALID PPC_BIT(0) 73 #define CQ_IC_BAR_64K PPC_BIT(1) 74 /* 2:7 reserved */ 75 #define CQ_IC_BAR_ADDR PPC_BITMASK(8, 42) 76 /* 43:63 reserved */ 77 78 /* Thread Management Base Address Register - 4 pages */ 79 #define X_CQ_TM_BAR 0x09 80 #define CQ_TM_BAR 0x048 81 #define CQ_TM_BAR_VALID PPC_BIT(0) 82 #define CQ_TM_BAR_64K PPC_BIT(1) 83 #define CQ_TM_BAR_ADDR PPC_BITMASK(8, 49) 84 85 /* ESB Base Address Register */ 86 #define X_CQ_ESB_BAR 0x0A 87 #define CQ_ESB_BAR 0x050 88 #define CQ_BAR_VALID PPC_BIT(0) 89 #define CQ_BAR_64K PPC_BIT(1) 90 /* 2:7 reserved */ 91 #define CQ_BAR_ADDR PPC_BITMASK(8, 39) 92 #define CQ_BAR_SET_DIV PPC_BITMASK(56, 58) 93 #define CQ_BAR_RANGE PPC_BITMASK(59, 63) 94 /* 0 (16M) - 16 (16T) */ 95 96 /* END Base Address Register */ 97 #define X_CQ_END_BAR 0x0B 98 #define CQ_END_BAR 0x058 99 100 /* NVPG Base Address Register */ 101 #define X_CQ_NVPG_BAR 0x0C 102 #define CQ_NVPG_BAR 0x060 103 104 /* NVC Base Address Register */ 105 #define X_CQ_NVC_BAR 0x0D 106 #define CQ_NVC_BAR 0x068 107 108 /* Table Address Register */ 109 #define X_CQ_TAR 0x0E 110 #define CQ_TAR 0x070 111 #define CQ_TAR_AUTOINC PPC_BIT(0) 112 #define CQ_TAR_SELECT PPC_BITMASK(12, 15) 113 #define CQ_TAR_ESB 0 /* 0 - 15 */ 114 #define CQ_TAR_END 2 /* 0 - 15 */ 115 #define CQ_TAR_NVPG 3 /* 0 - 15 */ 116 #define CQ_TAR_NVC 5 /* 0 - 15 */ 117 #define CQ_TAR_ENTRY_SELECT PPC_BITMASK(28, 31) 118 119 /* Table Data Register */ 120 #define X_CQ_TDR 0x0F 121 #define CQ_TDR 0x078 122 /* for the NVPG, NVC, ESB, END Set Translation Tables */ 123 #define CQ_TDR_VALID PPC_BIT(0) 124 #define CQ_TDR_BLOCK_ID PPC_BITMASK(60, 63) 125 126 /* 127 * Processor Cores Enabled for MsgSnd 128 * Identifies which of the 32 possible core chiplets are enabled and 129 * available to receive the MsgSnd command 130 */ 131 #define X_CQ_MSGSND 0x10 132 #define CQ_MSGSND 0x080 133 134 /* Interrupt Unit Reset Control */ 135 #define X_CQ_RST_CTL 0x12 136 #define CQ_RST_CTL 0x090 137 #define CQ_RST_SYNC_RESET PPC_BIT(0) /* Write Only */ 138 #define CQ_RST_QUIESCE_PB PPC_BIT(1) /* RW */ 139 #define CQ_RST_MASTER_IDLE PPC_BIT(2) /* Read Only */ 140 #define CQ_RST_SAVE_IDLE PPC_BIT(3) /* Read Only */ 141 #define CQ_RST_PB_BAR_RESET PPC_BIT(4) /* Write Only */ 142 143 /* PowerBus General Configuration */ 144 #define X_CQ_CFG_PB_GEN 0x14 145 #define CQ_CFG_PB_GEN 0x0A0 146 #define CQ_CFG_PB_GEN_PB_INIT PPC_BIT(45) 147 148 /* 149 * FIR 150 * (And-Mask) 151 * (Or-Mask) 152 */ 153 #define X_CQ_FIR 0x30 154 #define X_CQ_FIR_AND 0x31 155 #define X_CQ_FIR_OR 0x32 156 #define CQ_FIR 0x180 157 #define CQ_FIR_AND 0x188 158 #define CQ_FIR_OR 0x190 159 #define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19) 160 #define CQ_FIR_VC_INFO_ERROR_0_2 PPC_BITMASK(61, 63) 161 162 /* 163 * FIR Mask 164 * (And-Mask) 165 * (Or-Mask) 166 */ 167 #define X_CQ_FIRMASK 0x33 168 #define X_CQ_FIRMASK_AND 0x34 169 #define X_CQ_FIRMASK_OR 0x35 170 #define CQ_FIRMASK 0x198 171 #define CQ_FIRMASK_AND 0x1A0 172 #define CQ_FIRMASK_OR 0x1A8 173 174 /* 175 * VC0 176 */ 177 178 /* VSD table address */ 179 #define X_VC_VSD_TABLE_ADDR 0x100 180 #define VC_VSD_TABLE_ADDR 0x000 181 #define VC_VSD_TABLE_AUTOINC PPC_BIT(0) 182 #define VC_VSD_TABLE_SELECT PPC_BITMASK(12, 15) 183 #define VC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31) 184 185 /* VSD table data */ 186 #define X_VC_VSD_TABLE_DATA 0x101 187 #define VC_VSD_TABLE_DATA 0x008 188 189 /* AIB AT macro indirect kill */ 190 #define X_VC_AT_MACRO_KILL 0x102 191 #define VC_AT_MACRO_KILL 0x010 192 #define VC_AT_MACRO_KILL_VALID PPC_BIT(0) 193 #define VC_AT_MACRO_KILL_VSD PPC_BITMASK(12, 15) 194 #define VC_AT_MACRO_KILL_BLOCK_ID PPC_BITMASK(28, 31) 195 #define VC_AT_MACRO_KILL_OFFSET PPC_BITMASK(48, 60) 196 197 /* AIB AT macro indirect kill mask (same bit definitions) */ 198 #define X_VC_AT_MACRO_KILL_MASK 0x103 199 #define VC_AT_MACRO_KILL_MASK 0x018 200 201 /* Remote IRQs and ERQs configuration [n] (n = 0:6) */ 202 #define X_VC_QUEUES_CFG_REM0 0x117 203 204 #define VC_QUEUES_CFG_REM0 0x0B8 205 #define VC_QUEUES_CFG_REM1 0x0C0 206 #define VC_QUEUES_CFG_REM2 0x0C8 207 #define VC_QUEUES_CFG_REM3 0x0D0 208 #define VC_QUEUES_CFG_REM4 0x0D8 209 #define VC_QUEUES_CFG_REM5 0x0E0 210 #define VC_QUEUES_CFG_REM6 0x0E8 211 #define VC_QUEUES_CFG_MEMB_EN PPC_BIT(38) 212 #define VC_QUEUES_CFG_MEMB_SZ PPC_BITMASK(42, 47) 213 214 /* 215 * VC1 216 */ 217 218 /* ESBC cache flush control trigger */ 219 #define X_VC_ESBC_FLUSH_CTRL 0x140 220 #define VC_ESBC_FLUSH_CTRL 0x200 221 #define VC_ESBC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) 222 #define VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) 223 224 /* ESBC cache flush poll trigger */ 225 #define X_VC_ESBC_FLUSH_POLL 0x141 226 #define VC_ESBC_FLUSH_POLL 0x208 227 #define VC_ESBC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3) 228 #define VC_ESBC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31) /* 28-bit */ 229 #define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35) 230 #define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */ 231 232 /* EASC flush control register */ 233 #define X_VC_EASC_FLUSH_CTRL 0x160 234 #define VC_EASC_FLUSH_CTRL 0x300 235 #define VC_EASC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) 236 #define VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) 237 238 /* EASC flush poll register */ 239 #define X_VC_EASC_FLUSH_POLL 0x161 240 #define VC_EASC_FLUSH_POLL 0x308 241 #define VC_EASC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3) 242 #define VC_EASC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31) /* 28-bit */ 243 #define VC_EASC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35) 244 #define VC_EASC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */ 245 246 /* 247 * VC2 248 */ 249 250 /* ENDC flush control register */ 251 #define X_VC_ENDC_FLUSH_CTRL 0x180 252 #define VC_ENDC_FLUSH_CTRL 0x400 253 #define VC_ENDC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) 254 #define VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) 255 #define VC_ENDC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3) 256 #define VC_ENDC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7) 257 258 /* ENDC flush poll register */ 259 #define X_VC_ENDC_FLUSH_POLL 0x181 260 #define VC_ENDC_FLUSH_POLL 0x408 261 #define VC_ENDC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4, 7) 262 #define VC_ENDC_FLUSH_POLL_OFFSET PPC_BITMASK(8, 31) /* 24-bit */ 263 #define VC_ENDC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36, 39) 264 #define VC_ENDC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40, 63) /* 24-bit */ 265 266 /* ENDC Sync done */ 267 #define X_VC_ENDC_SYNC_DONE 0x184 268 #define VC_ENDC_SYNC_DONE 0x420 269 #define VC_ENDC_SYNC_POLL_DONE PPC_BITMASK(0, 6) 270 #define VC_ENDC_SYNC_QUEUE_IPI PPC_BIT(0) 271 #define VC_ENDC_SYNC_QUEUE_HWD PPC_BIT(1) 272 #define VC_ENDC_SYNC_QUEUE_NXC PPC_BIT(2) 273 #define VC_ENDC_SYNC_QUEUE_INT PPC_BIT(3) 274 #define VC_ENDC_SYNC_QUEUE_OS PPC_BIT(4) 275 #define VC_ENDC_SYNC_QUEUE_POOL PPC_BIT(5) 276 #define VC_ENDC_SYNC_QUEUE_HARD PPC_BIT(6) 277 #define VC_QUEUE_COUNT 7 278 279 /* ENDC cache watch specification 0 */ 280 #define X_VC_ENDC_WATCH0_SPEC 0x1A0 281 #define VC_ENDC_WATCH0_SPEC 0x500 282 #define VC_ENDC_WATCH_CONFLICT PPC_BIT(0) 283 #define VC_ENDC_WATCH_FULL PPC_BIT(8) 284 #define VC_ENDC_WATCH_BLOCK_ID PPC_BITMASK(28, 31) 285 #define VC_ENDC_WATCH_INDEX PPC_BITMASK(40, 63) 286 287 /* ENDC cache watch data 0 */ 288 #define X_VC_ENDC_WATCH0_DATA0 0x1A4 289 #define X_VC_ENDC_WATCH0_DATA1 0x1A5 290 #define X_VC_ENDC_WATCH0_DATA2 0x1A6 291 #define X_VC_ENDC_WATCH0_DATA3 0x1A7 292 293 #define VC_ENDC_WATCH0_DATA0 0x520 294 #define VC_ENDC_WATCH0_DATA1 0x528 295 #define VC_ENDC_WATCH0_DATA2 0x530 296 #define VC_ENDC_WATCH0_DATA3 0x538 297 298 /* 299 * PC LSB1 300 */ 301 302 /* VSD table address register */ 303 #define X_PC_VSD_TABLE_ADDR 0x200 304 #define PC_VSD_TABLE_ADDR 0x000 305 #define PC_VSD_TABLE_AUTOINC PPC_BIT(0) 306 #define PC_VSD_TABLE_SELECT PPC_BITMASK(12, 15) 307 #define PC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31) 308 309 /* VSD table data register */ 310 #define X_PC_VSD_TABLE_DATA 0x201 311 #define PC_VSD_TABLE_DATA 0x008 312 313 /* AT indirect kill register */ 314 #define X_PC_AT_KILL 0x202 315 #define PC_AT_KILL 0x010 316 #define PC_AT_KILL_VALID PPC_BIT(0) 317 #define PC_AT_KILL_VSD_TYPE PPC_BITMASK(24, 27) 318 /* Only NVP, NVG, NVC */ 319 #define PC_AT_KILL_BLOCK_ID PPC_BITMASK(28, 31) 320 #define PC_AT_KILL_OFFSET PPC_BITMASK(48, 60) 321 322 /* AT indirect kill mask register */ 323 #define X_PC_AT_KILL_MASK 0x203 324 #define PC_AT_KILL_MASK 0x018 325 #define PC_AT_KILL_MASK_VSD_TYPE PPC_BITMASK(24, 27) 326 #define PC_AT_KILL_MASK_BLOCK_ID PPC_BITMASK(28, 31) 327 #define PC_AT_KILL_MASK_OFFSET PPC_BITMASK(48, 60) 328 329 /* 330 * PC LSB2 331 */ 332 333 /* NxC Cache flush control */ 334 #define X_PC_NXC_FLUSH_CTRL 0x280 335 #define PC_NXC_FLUSH_CTRL 0x400 336 #define PC_NXC_FLUSH_CTRL_POLL_VALID PPC_BIT(0) 337 #define PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2) 338 #define PC_NXC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3) 339 #define PC_NXC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7) 340 341 /* NxC Cache flush poll */ 342 #define X_PC_NXC_FLUSH_POLL 0x281 343 #define PC_NXC_FLUSH_POLL 0x408 344 #define PC_NXC_FLUSH_POLL_NXC_TYPE PPC_BITMASK(2, 3) 345 #define PC_NXC_FLUSH_POLL_NXC_TYPE_NVP 0 346 #define PC_NXC_FLUSH_POLL_NXC_TYPE_NVG 2 347 #define PC_NXC_FLUSH_POLL_NXC_TYPE_NVC 3 348 #define PC_NXC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4, 7) 349 #define PC_NXC_FLUSH_POLL_OFFSET PPC_BITMASK(8, 31) /* 24-bit */ 350 #define PC_NXC_FLUSH_POLL_NXC_TYPE_MASK PPC_BITMASK(34, 35) /* 0: Ign */ 351 #define PC_NXC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36, 39) 352 #define PC_NXC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40, 63) /* 24-bit */ 353 354 /* NxC Cache Watch 0 Specification */ 355 #define X_PC_NXC_WATCH0_SPEC 0x2A0 356 #define PC_NXC_WATCH0_SPEC 0x500 357 #define PC_NXC_WATCH_CONFLICT PPC_BIT(0) 358 #define PC_NXC_WATCH_FULL PPC_BIT(8) 359 #define PC_NXC_WATCH_NXC_TYPE PPC_BITMASK(26, 27) 360 #define PC_NXC_WATCH_NXC_NVP 0 361 #define PC_NXC_WATCH_NXC_NVG 2 362 #define PC_NXC_WATCH_NXC_NVC 3 363 #define PC_NXC_WATCH_BLOCK_ID PPC_BITMASK(28, 31) 364 #define PC_NXC_WATCH_INDEX PPC_BITMASK(40, 63) 365 366 /* NxC Cache Watch 0 Data */ 367 #define X_PC_NXC_WATCH0_DATA0 0x2A4 368 #define X_PC_NXC_WATCH0_DATA1 0x2A5 369 #define X_PC_NXC_WATCH0_DATA2 0x2A6 370 #define X_PC_NXC_WATCH0_DATA3 0x2A7 371 372 #define PC_NXC_WATCH0_DATA0 0x520 373 #define PC_NXC_WATCH0_DATA1 0x528 374 #define PC_NXC_WATCH0_DATA2 0x530 375 #define PC_NXC_WATCH0_DATA3 0x538 376 377 /* 378 * TCTXT Registers 379 */ 380 381 /* Physical Thread Enable0 register */ 382 #define X_TCTXT_EN0 0x300 383 #define TCTXT_EN0 0x000 384 385 /* Physical Thread Enable0 Set register */ 386 #define X_TCTXT_EN0_SET 0x302 387 #define TCTXT_EN0_SET 0x010 388 389 /* Physical Thread Enable0 Reset register */ 390 #define X_TCTXT_EN0_RESET 0x303 391 #define TCTXT_EN0_RESET 0x018 392 393 /* Physical Thread Enable1 register */ 394 #define X_TCTXT_EN1 0x304 395 #define TCTXT_EN1 0x020 396 397 /* Physical Thread Enable1 Set register */ 398 #define X_TCTXT_EN1_SET 0x306 399 #define TCTXT_EN1_SET 0x030 400 401 /* Physical Thread Enable1 Reset register */ 402 #define X_TCTXT_EN1_RESET 0x307 403 #define TCTXT_EN1_RESET 0x038 404 405 /* 406 * VSD Tables 407 */ 408 #define VST_ESB 0 409 #define VST_EAS 1 /* No used by PC */ 410 #define VST_END 2 411 #define VST_NVP 3 412 #define VST_NVG 4 413 #define VST_NVC 5 414 #define VST_IC 6 /* No used by PC */ 415 #define VST_SYNC 7 416 #define VST_ERQ 8 /* No used by PC */ 417 418 /* 419 * Bits in a VSD entry. 420 * 421 * Note: the address is naturally aligned, we don't use a PPC_BITMASK, 422 * but just a mask to apply to the address before OR'ing it in. 423 * 424 * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the 425 * VSD and is only meant to be used in indirect mode ! 426 */ 427 #define VSD_MODE PPC_BITMASK(0, 1) 428 #define VSD_MODE_SHARED 1 429 #define VSD_MODE_EXCLUSIVE 2 430 #define VSD_MODE_FORWARD 3 431 #define VSD_FIRMWARE PPC_BIT(2) /* Read warning */ 432 #define VSD_FIRMWARE2 PPC_BIT(3) /* unused */ 433 #define VSD_RESERVED PPC_BITMASK(4, 7) /* P10 reserved */ 434 #define VSD_ADDRESS_MASK 0x00fffffffffff000ull 435 #define VSD_MIGRATION_REG PPC_BITMASK(52, 55) 436 #define VSD_INDIRECT PPC_BIT(56) 437 #define VSD_TSIZE PPC_BITMASK(59, 63) 438 439 #endif /* PPC_PNV_XIVE2_REGS_H */ 440