1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "sysemu/cpus.h" 15 #include "sysemu/dma.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/pnv.h" 19 #include "hw/ppc/pnv_chip.h" 20 #include "hw/ppc/pnv_core.h" 21 #include "hw/ppc/pnv_xscom.h" 22 #include "hw/ppc/xive2.h" 23 #include "hw/ppc/pnv_xive.h" 24 #include "hw/ppc/xive_regs.h" 25 #include "hw/ppc/xive2_regs.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/qdev-properties.h" 28 #include "sysemu/reset.h" 29 30 #include <libfdt.h> 31 32 #include "pnv_xive2_regs.h" 33 34 #undef XIVE2_DEBUG 35 36 /* 37 * Virtual structures table (VST) 38 */ 39 #define SBE_PER_BYTE 4 40 41 typedef struct XiveVstInfo { 42 const char *name; 43 uint32_t size; 44 uint32_t max_blocks; 45 } XiveVstInfo; 46 47 static const XiveVstInfo vst_infos[] = { 48 49 [VST_EAS] = { "EAT", sizeof(Xive2Eas), 16 }, 50 [VST_ESB] = { "ESB", 1, 16 }, 51 [VST_END] = { "ENDT", sizeof(Xive2End), 16 }, 52 53 [VST_NVP] = { "NVPT", sizeof(Xive2Nvp), 16 }, 54 [VST_NVG] = { "NVGT", sizeof(Xive2Nvgc), 16 }, 55 [VST_NVC] = { "NVCT", sizeof(Xive2Nvgc), 16 }, 56 57 [VST_IC] = { "IC", 1 /* ? */ , 16 }, /* Topology # */ 58 [VST_SYNC] = { "SYNC", 1 /* ? */ , 16 }, /* Topology # */ 59 60 /* 61 * This table contains the backing store pages for the interrupt 62 * fifos of the VC sub-engine in case of overflow. 63 * 64 * 0 - IPI, 65 * 1 - HWD, 66 * 2 - NxC, 67 * 3 - INT, 68 * 4 - OS-Queue, 69 * 5 - Pool-Queue, 70 * 6 - Hard-Queue 71 */ 72 [VST_ERQ] = { "ERQ", 1, VC_QUEUE_COUNT }, 73 }; 74 75 #define xive2_error(xive, fmt, ...) \ 76 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 77 (xive)->chip->chip_id, ## __VA_ARGS__); 78 79 /* 80 * TODO: Document block id override 81 */ 82 static uint32_t pnv_xive2_block_id(PnvXive2 *xive) 83 { 84 uint8_t blk = xive->chip->chip_id; 85 uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3]; 86 87 if (cfg_val & CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE) { 88 blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val); 89 } 90 91 return blk; 92 } 93 94 /* 95 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 96 * of the chips is good enough. 97 * 98 * TODO: Block scope support 99 */ 100 static PnvXive2 *pnv_xive2_get_remote(uint8_t blk) 101 { 102 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 103 int i; 104 105 for (i = 0; i < pnv->num_chips; i++) { 106 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 107 PnvXive2 *xive = &chip10->xive; 108 109 if (pnv_xive2_block_id(xive) == blk) { 110 return xive; 111 } 112 } 113 return NULL; 114 } 115 116 /* 117 * VST accessors for ESB, EAT, ENDT, NVP 118 * 119 * Indirect VST tables are arrays of VSDs pointing to a page (of same 120 * size). Each page is a direct VST table. 121 */ 122 123 #define XIVE_VSD_SIZE 8 124 125 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 126 static uint64_t pnv_xive2_vst_page_size_allowed(uint32_t page_shift) 127 { 128 return page_shift == 12 || page_shift == 16 || 129 page_shift == 21 || page_shift == 24; 130 } 131 132 static uint64_t pnv_xive2_vst_addr_direct(PnvXive2 *xive, uint32_t type, 133 uint64_t vsd, uint32_t idx) 134 { 135 const XiveVstInfo *info = &vst_infos[type]; 136 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 137 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 138 uint32_t idx_max; 139 140 idx_max = vst_tsize / info->size - 1; 141 if (idx > idx_max) { 142 #ifdef XIVE2_DEBUG 143 xive2_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 144 info->name, idx, idx_max); 145 #endif 146 return 0; 147 } 148 149 return vst_addr + idx * info->size; 150 } 151 152 static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type, 153 uint64_t vsd, uint32_t idx) 154 { 155 const XiveVstInfo *info = &vst_infos[type]; 156 uint64_t vsd_addr; 157 uint32_t vsd_idx; 158 uint32_t page_shift; 159 uint32_t vst_per_page; 160 161 /* Get the page size of the indirect table. */ 162 vsd_addr = vsd & VSD_ADDRESS_MASK; 163 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 164 165 if (!(vsd & VSD_ADDRESS_MASK)) { 166 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 167 return 0; 168 } 169 170 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 171 172 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 173 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 174 page_shift); 175 return 0; 176 } 177 178 vst_per_page = (1ull << page_shift) / info->size; 179 vsd_idx = idx / vst_per_page; 180 181 /* Load the VSD we are looking for, if not already done */ 182 if (vsd_idx) { 183 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 184 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, 185 MEMTXATTRS_UNSPECIFIED); 186 187 if (!(vsd & VSD_ADDRESS_MASK)) { 188 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 189 return 0; 190 } 191 192 /* 193 * Check that the pages have a consistent size across the 194 * indirect table 195 */ 196 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 197 xive2_error(xive, "VST: %s entry %x indirect page size differ !?", 198 info->name, idx); 199 return 0; 200 } 201 } 202 203 return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 204 } 205 206 static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk, 207 uint32_t idx) 208 { 209 const XiveVstInfo *info = &vst_infos[type]; 210 uint64_t vsd; 211 212 if (blk >= info->max_blocks) { 213 xive2_error(xive, "VST: invalid block id %d for VST %s %d !?", 214 blk, info->name, idx); 215 return 0; 216 } 217 218 vsd = xive->vsds[type][blk]; 219 220 /* Remote VST access */ 221 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 222 xive = pnv_xive2_get_remote(blk); 223 224 return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0; 225 } 226 227 if (VSD_INDIRECT & vsd) { 228 return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx); 229 } 230 231 return pnv_xive2_vst_addr_direct(xive, type, vsd, idx); 232 } 233 234 static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk, 235 uint32_t idx, void *data) 236 { 237 const XiveVstInfo *info = &vst_infos[type]; 238 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 239 240 if (!addr) { 241 return -1; 242 } 243 244 cpu_physical_memory_read(addr, data, info->size); 245 return 0; 246 } 247 248 #define XIVE_VST_WORD_ALL -1 249 250 static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk, 251 uint32_t idx, void *data, uint32_t word_number) 252 { 253 const XiveVstInfo *info = &vst_infos[type]; 254 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 255 256 if (!addr) { 257 return -1; 258 } 259 260 if (word_number == XIVE_VST_WORD_ALL) { 261 cpu_physical_memory_write(addr, data, info->size); 262 } else { 263 cpu_physical_memory_write(addr + word_number * 4, 264 data + word_number * 4, 4); 265 } 266 return 0; 267 } 268 269 static int pnv_xive2_get_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 270 uint8_t *pq) 271 { 272 PnvXive2 *xive = PNV_XIVE2(xrtr); 273 274 if (pnv_xive2_block_id(xive) != blk) { 275 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 276 return -1; 277 } 278 279 *pq = xive_source_esb_get(&xive->ipi_source, idx); 280 return 0; 281 } 282 283 static int pnv_xive2_set_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 284 uint8_t *pq) 285 { 286 PnvXive2 *xive = PNV_XIVE2(xrtr); 287 288 if (pnv_xive2_block_id(xive) != blk) { 289 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 290 return -1; 291 } 292 293 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq); 294 return 0; 295 } 296 297 static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 298 Xive2End *end) 299 { 300 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_END, blk, idx, end); 301 } 302 303 static int pnv_xive2_write_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 304 Xive2End *end, uint8_t word_number) 305 { 306 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_END, blk, idx, end, 307 word_number); 308 } 309 310 static int pnv_xive2_end_update(PnvXive2 *xive) 311 { 312 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 313 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 314 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 315 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 316 int i; 317 uint64_t endc_watch[4]; 318 319 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 320 endc_watch[i] = 321 cpu_to_be64(xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i]); 322 } 323 324 return pnv_xive2_vst_write(xive, VST_END, blk, idx, endc_watch, 325 XIVE_VST_WORD_ALL); 326 } 327 328 static void pnv_xive2_end_cache_load(PnvXive2 *xive) 329 { 330 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 331 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 332 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 333 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 334 uint64_t endc_watch[4] = { 0 }; 335 int i; 336 337 if (pnv_xive2_vst_read(xive, VST_END, blk, idx, endc_watch)) { 338 xive2_error(xive, "VST: no END entry %x/%x !?", blk, idx); 339 } 340 341 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 342 xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i] = 343 be64_to_cpu(endc_watch[i]); 344 } 345 } 346 347 static int pnv_xive2_get_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 348 Xive2Nvp *nvp) 349 { 350 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp); 351 } 352 353 static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 354 Xive2Nvp *nvp, uint8_t word_number) 355 { 356 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp, 357 word_number); 358 } 359 360 static int pnv_xive2_nvp_update(PnvXive2 *xive) 361 { 362 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 363 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 364 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 365 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 366 int i; 367 uint64_t nxc_watch[4]; 368 369 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 370 nxc_watch[i] = 371 cpu_to_be64(xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i]); 372 } 373 374 return pnv_xive2_vst_write(xive, VST_NVP, blk, idx, nxc_watch, 375 XIVE_VST_WORD_ALL); 376 } 377 378 static void pnv_xive2_nvp_cache_load(PnvXive2 *xive) 379 { 380 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 381 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 382 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 383 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 384 uint64_t nxc_watch[4] = { 0 }; 385 int i; 386 387 if (pnv_xive2_vst_read(xive, VST_NVP, blk, idx, nxc_watch)) { 388 xive2_error(xive, "VST: no NVP entry %x/%x !?", blk, idx); 389 } 390 391 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 392 xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i] = 393 be64_to_cpu(nxc_watch[i]); 394 } 395 } 396 397 static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 398 Xive2Eas *eas) 399 { 400 PnvXive2 *xive = PNV_XIVE2(xrtr); 401 402 if (pnv_xive2_block_id(xive) != blk) { 403 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 404 return -1; 405 } 406 407 return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas); 408 } 409 410 static uint32_t pnv_xive2_get_config(Xive2Router *xrtr) 411 { 412 PnvXive2 *xive = PNV_XIVE2(xrtr); 413 uint32_t cfg = 0; 414 415 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { 416 cfg |= XIVE2_GEN1_TIMA_OS; 417 } 418 419 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) { 420 cfg |= XIVE2_VP_SAVE_RESTORE; 421 } 422 423 if (GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, 424 xive->cq_regs[CQ_XIVE_CFG >> 3]) == CQ_XIVE_CFG_THREADID_8BITS) { 425 cfg |= XIVE2_THREADID_8BITS; 426 } 427 428 return cfg; 429 } 430 431 static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu) 432 { 433 int pir = ppc_cpu_pir(cpu); 434 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); 435 uint64_t reg = fc < 8 ? TCTXT_EN0 : TCTXT_EN1; 436 uint32_t bit = pir & 0x3f; 437 438 return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit); 439 } 440 441 static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, 442 uint8_t nvt_blk, uint32_t nvt_idx, 443 bool cam_ignore, uint8_t priority, 444 uint32_t logic_serv, XiveTCTXMatch *match) 445 { 446 PnvXive2 *xive = PNV_XIVE2(xptr); 447 PnvChip *chip = xive->chip; 448 int count = 0; 449 int i, j; 450 bool gen1_tima_os = 451 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 452 453 for (i = 0; i < chip->nr_cores; i++) { 454 PnvCore *pc = chip->cores[i]; 455 CPUCore *cc = CPU_CORE(pc); 456 457 for (j = 0; j < cc->nr_threads; j++) { 458 PowerPCCPU *cpu = pc->threads[j]; 459 XiveTCTX *tctx; 460 int ring; 461 462 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 463 continue; 464 } 465 466 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 467 468 if (gen1_tima_os) { 469 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, 470 nvt_idx, cam_ignore, 471 logic_serv); 472 } else { 473 ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk, 474 nvt_idx, cam_ignore, 475 logic_serv); 476 } 477 478 /* 479 * Save the context and follow on to catch duplicates, 480 * that we don't support yet. 481 */ 482 if (ring != -1) { 483 if (match->tctx) { 484 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 485 "thread context NVT %x/%x\n", 486 nvt_blk, nvt_idx); 487 return false; 488 } 489 490 match->ring = ring; 491 match->tctx = tctx; 492 count++; 493 } 494 } 495 } 496 497 return count; 498 } 499 500 static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) 501 { 502 return pnv_xive2_block_id(PNV_XIVE2(xrtr)); 503 } 504 505 /* 506 * The TIMA MMIO space is shared among the chips and to identify the 507 * chip from which the access is being done, we extract the chip id 508 * from the PIR. 509 */ 510 static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu) 511 { 512 int pir = ppc_cpu_pir(cpu); 513 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; 514 PnvXive2 *xive = PNV_XIVE2(xptr); 515 516 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 517 xive2_error(xive, "IC: CPU %x is not enabled", pir); 518 } 519 return xive; 520 } 521 522 /* 523 * The internal sources of the interrupt controller have no knowledge 524 * of the XIVE2 chip on which they reside. Encode the block id in the 525 * source interrupt number before forwarding the source event 526 * notification to the Router. This is required on a multichip system. 527 */ 528 static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked) 529 { 530 PnvXive2 *xive = PNV_XIVE2(xn); 531 uint8_t blk = pnv_xive2_block_id(xive); 532 533 xive2_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked); 534 } 535 536 /* 537 * Set Translation Tables 538 * 539 * TODO add support for multiple sets 540 */ 541 static int pnv_xive2_stt_set_data(PnvXive2 *xive, uint64_t val) 542 { 543 uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]); 544 uint8_t entry = GETFIELD(CQ_TAR_ENTRY_SELECT, 545 xive->cq_regs[CQ_TAR >> 3]); 546 547 switch (tsel) { 548 case CQ_TAR_NVPG: 549 case CQ_TAR_ESB: 550 case CQ_TAR_END: 551 xive->tables[tsel][entry] = val; 552 break; 553 default: 554 xive2_error(xive, "IC: unsupported table %d", tsel); 555 return -1; 556 } 557 558 if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) { 559 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT, 560 xive->cq_regs[CQ_TAR >> 3], ++entry); 561 } 562 563 return 0; 564 } 565 /* 566 * Virtual Structure Tables (VST) configuration 567 */ 568 static void pnv_xive2_vst_set_exclusive(PnvXive2 *xive, uint8_t type, 569 uint8_t blk, uint64_t vsd) 570 { 571 Xive2EndSource *end_xsrc = &xive->end_source; 572 XiveSource *xsrc = &xive->ipi_source; 573 const XiveVstInfo *info = &vst_infos[type]; 574 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 575 uint64_t vst_tsize = 1ull << page_shift; 576 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 577 578 /* Basic checks */ 579 580 if (VSD_INDIRECT & vsd) { 581 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 582 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 583 page_shift); 584 return; 585 } 586 } 587 588 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 589 xive2_error(xive, "VST: %s table address 0x%"PRIx64 590 " is not aligned with page shift %d", 591 info->name, vst_addr, page_shift); 592 return; 593 } 594 595 /* Record the table configuration (in SRAM on HW) */ 596 xive->vsds[type][blk] = vsd; 597 598 /* Now tune the models with the configuration provided by the FW */ 599 600 switch (type) { 601 case VST_ESB: 602 /* 603 * Backing store pages for the source PQ bits. The model does 604 * not use these PQ bits backed in RAM because the XiveSource 605 * model has its own. 606 * 607 * If the table is direct, we can compute the number of PQ 608 * entries provisioned by FW (such as skiboot) and resize the 609 * ESB window accordingly. 610 */ 611 if (!(VSD_INDIRECT & vsd)) { 612 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 613 * (1ull << xsrc->esb_shift)); 614 } 615 616 memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio); 617 break; 618 619 case VST_EAS: /* Nothing to be done */ 620 break; 621 622 case VST_END: 623 /* 624 * Backing store pages for the END. 625 */ 626 if (!(VSD_INDIRECT & vsd)) { 627 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 628 * (1ull << end_xsrc->esb_shift)); 629 } 630 memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio); 631 break; 632 633 case VST_NVP: /* Not modeled */ 634 case VST_NVG: /* Not modeled */ 635 case VST_NVC: /* Not modeled */ 636 case VST_IC: /* Not modeled */ 637 case VST_SYNC: /* Not modeled */ 638 case VST_ERQ: /* Not modeled */ 639 break; 640 641 default: 642 g_assert_not_reached(); 643 } 644 } 645 646 /* 647 * Both PC and VC sub-engines are configured as each use the Virtual 648 * Structure Tables 649 */ 650 static void pnv_xive2_vst_set_data(PnvXive2 *xive, uint64_t vsd) 651 { 652 uint8_t mode = GETFIELD(VSD_MODE, vsd); 653 uint8_t type = GETFIELD(VC_VSD_TABLE_SELECT, 654 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 655 uint8_t blk = GETFIELD(VC_VSD_TABLE_ADDRESS, 656 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 657 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 658 659 if (type > VST_ERQ) { 660 xive2_error(xive, "VST: invalid table type %d", type); 661 return; 662 } 663 664 if (blk >= vst_infos[type].max_blocks) { 665 xive2_error(xive, "VST: invalid block id %d for" 666 " %s table", blk, vst_infos[type].name); 667 return; 668 } 669 670 if (!vst_addr) { 671 xive2_error(xive, "VST: invalid %s table address", 672 vst_infos[type].name); 673 return; 674 } 675 676 switch (mode) { 677 case VSD_MODE_FORWARD: 678 xive->vsds[type][blk] = vsd; 679 break; 680 681 case VSD_MODE_EXCLUSIVE: 682 pnv_xive2_vst_set_exclusive(xive, type, blk, vsd); 683 break; 684 685 default: 686 xive2_error(xive, "VST: unsupported table mode %d", mode); 687 return; 688 } 689 } 690 691 /* 692 * MMIO handlers 693 */ 694 695 696 /* 697 * IC BAR layout 698 * 699 * Page 0: Internal CQ register accesses (reads & writes) 700 * Page 1: Internal PC register accesses (reads & writes) 701 * Page 2: Internal VC register accesses (reads & writes) 702 * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes) 703 * Page 4: Notify Port page (writes only, w/data), 704 * Page 5: Reserved 705 * Page 6: Sync Poll page (writes only, dataless) 706 * Page 7: Sync Inject page (writes only, dataless) 707 * Page 8: LSI Trigger page (writes only, dataless) 708 * Page 9: LSI SB Management page (reads & writes dataless) 709 * Pages 10-255: Reserved 710 * Pages 256-383: Direct mapped Thread Context Area (reads & writes) 711 * covering the 128 threads in P10. 712 * Pages 384-511: Reserved 713 */ 714 typedef struct PnvXive2Region { 715 const char *name; 716 uint32_t pgoff; 717 uint32_t pgsize; 718 const MemoryRegionOps *ops; 719 } PnvXive2Region; 720 721 static const MemoryRegionOps pnv_xive2_ic_cq_ops; 722 static const MemoryRegionOps pnv_xive2_ic_pc_ops; 723 static const MemoryRegionOps pnv_xive2_ic_vc_ops; 724 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops; 725 static const MemoryRegionOps pnv_xive2_ic_notify_ops; 726 static const MemoryRegionOps pnv_xive2_ic_sync_ops; 727 static const MemoryRegionOps pnv_xive2_ic_lsi_ops; 728 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops; 729 730 /* 512 pages. 4K: 2M range, 64K: 32M range */ 731 static const PnvXive2Region pnv_xive2_ic_regions[] = { 732 { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops }, 733 { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops }, 734 { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops }, 735 { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops }, 736 { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops }, 737 /* page 5 reserved */ 738 { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops }, 739 { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops }, 740 /* pages 10-255 reserved */ 741 { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops }, 742 /* pages 384-511 reserved */ 743 }; 744 745 /* 746 * CQ operations 747 */ 748 749 static uint64_t pnv_xive2_ic_cq_read(void *opaque, hwaddr offset, 750 unsigned size) 751 { 752 PnvXive2 *xive = PNV_XIVE2(opaque); 753 uint32_t reg = offset >> 3; 754 uint64_t val = 0; 755 756 switch (offset) { 757 case CQ_XIVE_CAP: /* Set at reset */ 758 case CQ_XIVE_CFG: 759 val = xive->cq_regs[reg]; 760 break; 761 case CQ_MSGSND: /* TODO check the #cores of the machine */ 762 val = 0xffffffff00000000; 763 break; 764 case CQ_CFG_PB_GEN: 765 val = CQ_CFG_PB_GEN_PB_INIT; /* TODO: fix CQ_CFG_PB_GEN default value */ 766 break; 767 default: 768 xive2_error(xive, "CQ: invalid read @%"HWADDR_PRIx, offset); 769 } 770 771 return val; 772 } 773 774 static uint64_t pnv_xive2_bar_size(uint64_t val) 775 { 776 return 1ull << (GETFIELD(CQ_BAR_RANGE, val) + 24); 777 } 778 779 static void pnv_xive2_ic_cq_write(void *opaque, hwaddr offset, 780 uint64_t val, unsigned size) 781 { 782 PnvXive2 *xive = PNV_XIVE2(opaque); 783 MemoryRegion *sysmem = get_system_memory(); 784 uint32_t reg = offset >> 3; 785 int i; 786 787 switch (offset) { 788 case CQ_XIVE_CFG: 789 case CQ_RST_CTL: /* TODO: reset all BARs */ 790 break; 791 792 case CQ_IC_BAR: 793 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 794 if (!(val & CQ_IC_BAR_VALID)) { 795 xive->ic_base = 0; 796 if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) { 797 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 798 memory_region_del_subregion(&xive->ic_mmio, 799 &xive->ic_mmios[i]); 800 } 801 memory_region_del_subregion(sysmem, &xive->ic_mmio); 802 } 803 } else { 804 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 805 if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) { 806 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 807 memory_region_add_subregion(&xive->ic_mmio, 808 pnv_xive2_ic_regions[i].pgoff << xive->ic_shift, 809 &xive->ic_mmios[i]); 810 } 811 memory_region_add_subregion(sysmem, xive->ic_base, 812 &xive->ic_mmio); 813 } 814 } 815 break; 816 817 case CQ_TM_BAR: 818 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 819 if (!(val & CQ_TM_BAR_VALID)) { 820 xive->tm_base = 0; 821 if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) { 822 memory_region_del_subregion(sysmem, &xive->tm_mmio); 823 } 824 } else { 825 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 826 if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) { 827 memory_region_add_subregion(sysmem, xive->tm_base, 828 &xive->tm_mmio); 829 } 830 } 831 break; 832 833 case CQ_ESB_BAR: 834 xive->esb_shift = val & CQ_BAR_64K ? 16 : 12; 835 if (!(val & CQ_BAR_VALID)) { 836 xive->esb_base = 0; 837 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 838 memory_region_del_subregion(sysmem, &xive->esb_mmio); 839 } 840 } else { 841 xive->esb_base = val & CQ_BAR_ADDR; 842 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 843 memory_region_set_size(&xive->esb_mmio, 844 pnv_xive2_bar_size(val)); 845 memory_region_add_subregion(sysmem, xive->esb_base, 846 &xive->esb_mmio); 847 } 848 } 849 break; 850 851 case CQ_END_BAR: 852 xive->end_shift = val & CQ_BAR_64K ? 16 : 12; 853 if (!(val & CQ_BAR_VALID)) { 854 xive->end_base = 0; 855 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 856 memory_region_del_subregion(sysmem, &xive->end_mmio); 857 } 858 } else { 859 xive->end_base = val & CQ_BAR_ADDR; 860 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 861 memory_region_set_size(&xive->end_mmio, 862 pnv_xive2_bar_size(val)); 863 memory_region_add_subregion(sysmem, xive->end_base, 864 &xive->end_mmio); 865 } 866 } 867 break; 868 869 case CQ_NVC_BAR: 870 xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12; 871 if (!(val & CQ_BAR_VALID)) { 872 xive->nvc_base = 0; 873 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 874 memory_region_del_subregion(sysmem, &xive->nvc_mmio); 875 } 876 } else { 877 xive->nvc_base = val & CQ_BAR_ADDR; 878 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 879 memory_region_set_size(&xive->nvc_mmio, 880 pnv_xive2_bar_size(val)); 881 memory_region_add_subregion(sysmem, xive->nvc_base, 882 &xive->nvc_mmio); 883 } 884 } 885 break; 886 887 case CQ_NVPG_BAR: 888 xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12; 889 if (!(val & CQ_BAR_VALID)) { 890 xive->nvpg_base = 0; 891 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 892 memory_region_del_subregion(sysmem, &xive->nvpg_mmio); 893 } 894 } else { 895 xive->nvpg_base = val & CQ_BAR_ADDR; 896 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 897 memory_region_set_size(&xive->nvpg_mmio, 898 pnv_xive2_bar_size(val)); 899 memory_region_add_subregion(sysmem, xive->nvpg_base, 900 &xive->nvpg_mmio); 901 } 902 } 903 break; 904 905 case CQ_TAR: /* Set Translation Table Address */ 906 break; 907 case CQ_TDR: /* Set Translation Table Data */ 908 pnv_xive2_stt_set_data(xive, val); 909 break; 910 case CQ_FIRMASK_OR: /* FIR error reporting */ 911 break; 912 default: 913 xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset); 914 return; 915 } 916 917 xive->cq_regs[reg] = val; 918 } 919 920 static const MemoryRegionOps pnv_xive2_ic_cq_ops = { 921 .read = pnv_xive2_ic_cq_read, 922 .write = pnv_xive2_ic_cq_write, 923 .endianness = DEVICE_BIG_ENDIAN, 924 .valid = { 925 .min_access_size = 8, 926 .max_access_size = 8, 927 }, 928 .impl = { 929 .min_access_size = 8, 930 .max_access_size = 8, 931 }, 932 }; 933 934 static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, 935 unsigned size) 936 { 937 PnvXive2 *xive = PNV_XIVE2(opaque); 938 uint64_t val = 0; 939 uint32_t reg = offset >> 3; 940 941 switch (offset) { 942 /* 943 * VSD table settings. 944 */ 945 case VC_VSD_TABLE_ADDR: 946 case VC_VSD_TABLE_DATA: 947 val = xive->vc_regs[reg]; 948 break; 949 950 /* 951 * ESB cache updates (not modeled) 952 */ 953 case VC_ESBC_FLUSH_CTRL: 954 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID; 955 val = xive->vc_regs[reg]; 956 break; 957 958 case VC_ESBC_CFG: 959 val = xive->vc_regs[reg]; 960 break; 961 962 /* 963 * EAS cache updates (not modeled) 964 */ 965 case VC_EASC_FLUSH_CTRL: 966 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID; 967 val = xive->vc_regs[reg]; 968 break; 969 970 /* 971 * END cache updates 972 */ 973 case VC_ENDC_WATCH0_SPEC: 974 xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT); 975 val = xive->vc_regs[reg]; 976 break; 977 978 case VC_ENDC_WATCH0_DATA0: 979 /* 980 * Load DATA registers from cache with data requested by the 981 * SPEC register 982 */ 983 pnv_xive2_end_cache_load(xive); 984 val = xive->vc_regs[reg]; 985 break; 986 987 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 988 val = xive->vc_regs[reg]; 989 break; 990 991 case VC_ENDC_FLUSH_CTRL: 992 xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID; 993 val = xive->vc_regs[reg]; 994 break; 995 996 /* 997 * Indirect invalidation 998 */ 999 case VC_AT_MACRO_KILL_MASK: 1000 val = xive->vc_regs[reg]; 1001 break; 1002 1003 case VC_AT_MACRO_KILL: 1004 xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID; 1005 val = xive->vc_regs[reg]; 1006 break; 1007 1008 /* 1009 * Interrupt fifo overflow in memory backing store (Not modeled) 1010 */ 1011 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1012 val = xive->vc_regs[reg]; 1013 break; 1014 1015 /* 1016 * Synchronisation 1017 */ 1018 case VC_ENDC_SYNC_DONE: 1019 val = VC_ENDC_SYNC_POLL_DONE; 1020 break; 1021 default: 1022 xive2_error(xive, "VC: invalid read @%"HWADDR_PRIx, offset); 1023 } 1024 1025 return val; 1026 } 1027 1028 static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, 1029 uint64_t val, unsigned size) 1030 { 1031 PnvXive2 *xive = PNV_XIVE2(opaque); 1032 uint32_t reg = offset >> 3; 1033 1034 switch (offset) { 1035 /* 1036 * VSD table settings. 1037 */ 1038 case VC_VSD_TABLE_ADDR: 1039 break; 1040 case VC_VSD_TABLE_DATA: 1041 pnv_xive2_vst_set_data(xive, val); 1042 break; 1043 1044 /* 1045 * ESB cache updates (not modeled) 1046 */ 1047 /* case VC_ESBC_FLUSH_CTRL: */ 1048 case VC_ESBC_FLUSH_POLL: 1049 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; 1050 /* ESB update */ 1051 break; 1052 1053 case VC_ESBC_CFG: 1054 break; 1055 1056 /* 1057 * EAS cache updates (not modeled) 1058 */ 1059 /* case VC_EASC_FLUSH_CTRL: */ 1060 case VC_EASC_FLUSH_POLL: 1061 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; 1062 /* EAS update */ 1063 break; 1064 1065 /* 1066 * END cache updates 1067 */ 1068 case VC_ENDC_WATCH0_SPEC: 1069 val &= ~VC_ENDC_WATCH_CONFLICT; /* HW will set this bit */ 1070 break; 1071 1072 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1073 break; 1074 case VC_ENDC_WATCH0_DATA0: 1075 /* writing to DATA0 triggers the cache write */ 1076 xive->vc_regs[reg] = val; 1077 pnv_xive2_end_update(xive); 1078 break; 1079 1080 1081 /* case VC_ENDC_FLUSH_CTRL: */ 1082 case VC_ENDC_FLUSH_POLL: 1083 xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; 1084 break; 1085 1086 /* 1087 * Indirect invalidation 1088 */ 1089 case VC_AT_MACRO_KILL: 1090 case VC_AT_MACRO_KILL_MASK: 1091 break; 1092 1093 /* 1094 * Interrupt fifo overflow in memory backing store (Not modeled) 1095 */ 1096 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1097 break; 1098 1099 /* 1100 * Synchronisation 1101 */ 1102 case VC_ENDC_SYNC_DONE: 1103 break; 1104 1105 default: 1106 xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset); 1107 return; 1108 } 1109 1110 xive->vc_regs[reg] = val; 1111 } 1112 1113 static const MemoryRegionOps pnv_xive2_ic_vc_ops = { 1114 .read = pnv_xive2_ic_vc_read, 1115 .write = pnv_xive2_ic_vc_write, 1116 .endianness = DEVICE_BIG_ENDIAN, 1117 .valid = { 1118 .min_access_size = 8, 1119 .max_access_size = 8, 1120 }, 1121 .impl = { 1122 .min_access_size = 8, 1123 .max_access_size = 8, 1124 }, 1125 }; 1126 1127 static uint64_t pnv_xive2_ic_pc_read(void *opaque, hwaddr offset, 1128 unsigned size) 1129 { 1130 PnvXive2 *xive = PNV_XIVE2(opaque); 1131 uint64_t val = -1; 1132 uint32_t reg = offset >> 3; 1133 1134 switch (offset) { 1135 /* 1136 * VSD table settings. 1137 */ 1138 case PC_VSD_TABLE_ADDR: 1139 case PC_VSD_TABLE_DATA: 1140 val = xive->pc_regs[reg]; 1141 break; 1142 1143 /* 1144 * cache updates 1145 */ 1146 case PC_NXC_WATCH0_SPEC: 1147 xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT); 1148 val = xive->pc_regs[reg]; 1149 break; 1150 1151 case PC_NXC_WATCH0_DATA0: 1152 /* 1153 * Load DATA registers from cache with data requested by the 1154 * SPEC register 1155 */ 1156 pnv_xive2_nvp_cache_load(xive); 1157 val = xive->pc_regs[reg]; 1158 break; 1159 1160 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1161 val = xive->pc_regs[reg]; 1162 break; 1163 1164 case PC_NXC_FLUSH_CTRL: 1165 xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID; 1166 val = xive->pc_regs[reg]; 1167 break; 1168 1169 /* 1170 * Indirect invalidation 1171 */ 1172 case PC_AT_KILL: 1173 xive->pc_regs[reg] &= ~PC_AT_KILL_VALID; 1174 val = xive->pc_regs[reg]; 1175 break; 1176 1177 default: 1178 xive2_error(xive, "PC: invalid read @%"HWADDR_PRIx, offset); 1179 } 1180 1181 return val; 1182 } 1183 1184 static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset, 1185 uint64_t val, unsigned size) 1186 { 1187 PnvXive2 *xive = PNV_XIVE2(opaque); 1188 uint32_t reg = offset >> 3; 1189 1190 switch (offset) { 1191 1192 /* 1193 * VSD table settings. Only taken into account in the VC 1194 * sub-engine because the Xive2Router model combines both VC and PC 1195 * sub-engines 1196 */ 1197 case PC_VSD_TABLE_ADDR: 1198 case PC_VSD_TABLE_DATA: 1199 break; 1200 1201 /* 1202 * cache updates 1203 */ 1204 case PC_NXC_WATCH0_SPEC: 1205 val &= ~PC_NXC_WATCH_CONFLICT; /* HW will set this bit */ 1206 break; 1207 1208 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1209 break; 1210 case PC_NXC_WATCH0_DATA0: 1211 /* writing to DATA0 triggers the cache write */ 1212 xive->pc_regs[reg] = val; 1213 pnv_xive2_nvp_update(xive); 1214 break; 1215 1216 /* case PC_NXC_FLUSH_CTRL: */ 1217 case PC_NXC_FLUSH_POLL: 1218 xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; 1219 break; 1220 1221 /* 1222 * Indirect invalidation 1223 */ 1224 case PC_AT_KILL: 1225 case PC_AT_KILL_MASK: 1226 break; 1227 1228 default: 1229 xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset); 1230 return; 1231 } 1232 1233 xive->pc_regs[reg] = val; 1234 } 1235 1236 static const MemoryRegionOps pnv_xive2_ic_pc_ops = { 1237 .read = pnv_xive2_ic_pc_read, 1238 .write = pnv_xive2_ic_pc_write, 1239 .endianness = DEVICE_BIG_ENDIAN, 1240 .valid = { 1241 .min_access_size = 8, 1242 .max_access_size = 8, 1243 }, 1244 .impl = { 1245 .min_access_size = 8, 1246 .max_access_size = 8, 1247 }, 1248 }; 1249 1250 1251 static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset, 1252 unsigned size) 1253 { 1254 PnvXive2 *xive = PNV_XIVE2(opaque); 1255 uint64_t val = -1; 1256 uint32_t reg = offset >> 3; 1257 1258 switch (offset) { 1259 /* 1260 * XIVE2 hardware thread enablement 1261 */ 1262 case TCTXT_EN0: 1263 case TCTXT_EN1: 1264 val = xive->tctxt_regs[reg]; 1265 break; 1266 1267 case TCTXT_EN0_SET: 1268 case TCTXT_EN0_RESET: 1269 val = xive->tctxt_regs[TCTXT_EN0 >> 3]; 1270 break; 1271 case TCTXT_EN1_SET: 1272 case TCTXT_EN1_RESET: 1273 val = xive->tctxt_regs[TCTXT_EN1 >> 3]; 1274 break; 1275 case TCTXT_CFG: 1276 val = xive->tctxt_regs[reg]; 1277 break; 1278 default: 1279 xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); 1280 } 1281 1282 return val; 1283 } 1284 1285 static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, 1286 uint64_t val, unsigned size) 1287 { 1288 PnvXive2 *xive = PNV_XIVE2(opaque); 1289 uint32_t reg = offset >> 3; 1290 1291 switch (offset) { 1292 /* 1293 * XIVE2 hardware thread enablement 1294 */ 1295 case TCTXT_EN0: /* Physical Thread Enable */ 1296 case TCTXT_EN1: /* Physical Thread Enable (fused core) */ 1297 xive->tctxt_regs[reg] = val; 1298 break; 1299 1300 case TCTXT_EN0_SET: 1301 xive->tctxt_regs[TCTXT_EN0 >> 3] |= val; 1302 break; 1303 case TCTXT_EN1_SET: 1304 xive->tctxt_regs[TCTXT_EN1 >> 3] |= val; 1305 break; 1306 case TCTXT_EN0_RESET: 1307 xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val; 1308 break; 1309 case TCTXT_EN1_RESET: 1310 xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; 1311 break; 1312 case TCTXT_CFG: 1313 xive->tctxt_regs[reg] = val; 1314 break; 1315 default: 1316 xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); 1317 return; 1318 } 1319 } 1320 1321 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = { 1322 .read = pnv_xive2_ic_tctxt_read, 1323 .write = pnv_xive2_ic_tctxt_write, 1324 .endianness = DEVICE_BIG_ENDIAN, 1325 .valid = { 1326 .min_access_size = 8, 1327 .max_access_size = 8, 1328 }, 1329 .impl = { 1330 .min_access_size = 8, 1331 .max_access_size = 8, 1332 }, 1333 }; 1334 1335 /* 1336 * Redirect XSCOM to MMIO handlers 1337 */ 1338 static uint64_t pnv_xive2_xscom_read(void *opaque, hwaddr offset, 1339 unsigned size) 1340 { 1341 PnvXive2 *xive = PNV_XIVE2(opaque); 1342 uint64_t val = -1; 1343 uint32_t xscom_reg = offset >> 3; 1344 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1345 1346 switch (xscom_reg) { 1347 case 0x000 ... 0x0FF: 1348 val = pnv_xive2_ic_cq_read(opaque, mmio_offset, size); 1349 break; 1350 case 0x100 ... 0x1FF: 1351 val = pnv_xive2_ic_vc_read(opaque, mmio_offset, size); 1352 break; 1353 case 0x200 ... 0x2FF: 1354 val = pnv_xive2_ic_pc_read(opaque, mmio_offset, size); 1355 break; 1356 case 0x300 ... 0x3FF: 1357 val = pnv_xive2_ic_tctxt_read(opaque, mmio_offset, size); 1358 break; 1359 default: 1360 xive2_error(xive, "XSCOM: invalid read @%"HWADDR_PRIx, offset); 1361 } 1362 1363 return val; 1364 } 1365 1366 static void pnv_xive2_xscom_write(void *opaque, hwaddr offset, 1367 uint64_t val, unsigned size) 1368 { 1369 PnvXive2 *xive = PNV_XIVE2(opaque); 1370 uint32_t xscom_reg = offset >> 3; 1371 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1372 1373 switch (xscom_reg) { 1374 case 0x000 ... 0x0FF: 1375 pnv_xive2_ic_cq_write(opaque, mmio_offset, val, size); 1376 break; 1377 case 0x100 ... 0x1FF: 1378 pnv_xive2_ic_vc_write(opaque, mmio_offset, val, size); 1379 break; 1380 case 0x200 ... 0x2FF: 1381 pnv_xive2_ic_pc_write(opaque, mmio_offset, val, size); 1382 break; 1383 case 0x300 ... 0x3FF: 1384 pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size); 1385 break; 1386 default: 1387 xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset); 1388 } 1389 } 1390 1391 static const MemoryRegionOps pnv_xive2_xscom_ops = { 1392 .read = pnv_xive2_xscom_read, 1393 .write = pnv_xive2_xscom_write, 1394 .endianness = DEVICE_BIG_ENDIAN, 1395 .valid = { 1396 .min_access_size = 8, 1397 .max_access_size = 8, 1398 }, 1399 .impl = { 1400 .min_access_size = 8, 1401 .max_access_size = 8, 1402 }, 1403 }; 1404 1405 /* 1406 * Notify port page. The layout is compatible between 4K and 64K pages : 1407 * 1408 * Page 1 Notify page (writes only) 1409 * 0x000 - 0x7FF IPI interrupt (NPU) 1410 * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB) 1411 */ 1412 1413 static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr, 1414 uint64_t val) 1415 { 1416 uint8_t blk; 1417 uint32_t idx; 1418 1419 if (val & XIVE_TRIGGER_END) { 1420 xive2_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1421 addr, val); 1422 return; 1423 } 1424 1425 /* 1426 * Forward the source event notification directly to the Router. 1427 * The source interrupt number should already be correctly encoded 1428 * with the chip block id by the sending device (PHB, PSI). 1429 */ 1430 blk = XIVE_EAS_BLOCK(val); 1431 idx = XIVE_EAS_INDEX(val); 1432 1433 xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx), 1434 !!(val & XIVE_TRIGGER_PQ)); 1435 } 1436 1437 static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset, 1438 uint64_t val, unsigned size) 1439 { 1440 PnvXive2 *xive = PNV_XIVE2(opaque); 1441 1442 /* VC: IPI triggers */ 1443 switch (offset) { 1444 case 0x000 ... 0x7FF: 1445 /* TODO: check IPI notify sub-page routing */ 1446 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1447 break; 1448 1449 /* VC: HW triggers */ 1450 case 0x800 ... 0xFFF: 1451 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1452 break; 1453 1454 default: 1455 xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset); 1456 } 1457 } 1458 1459 static uint64_t pnv_xive2_ic_notify_read(void *opaque, hwaddr offset, 1460 unsigned size) 1461 { 1462 PnvXive2 *xive = PNV_XIVE2(opaque); 1463 1464 /* loads are invalid */ 1465 xive2_error(xive, "NOTIFY: invalid read @%"HWADDR_PRIx, offset); 1466 return -1; 1467 } 1468 1469 static const MemoryRegionOps pnv_xive2_ic_notify_ops = { 1470 .read = pnv_xive2_ic_notify_read, 1471 .write = pnv_xive2_ic_notify_write, 1472 .endianness = DEVICE_BIG_ENDIAN, 1473 .valid = { 1474 .min_access_size = 8, 1475 .max_access_size = 8, 1476 }, 1477 .impl = { 1478 .min_access_size = 8, 1479 .max_access_size = 8, 1480 }, 1481 }; 1482 1483 static uint64_t pnv_xive2_ic_lsi_read(void *opaque, hwaddr offset, 1484 unsigned size) 1485 { 1486 PnvXive2 *xive = PNV_XIVE2(opaque); 1487 1488 xive2_error(xive, "LSI: invalid read @%"HWADDR_PRIx, offset); 1489 return -1; 1490 } 1491 1492 static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset, 1493 uint64_t val, unsigned size) 1494 { 1495 PnvXive2 *xive = PNV_XIVE2(opaque); 1496 1497 xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset); 1498 } 1499 1500 static const MemoryRegionOps pnv_xive2_ic_lsi_ops = { 1501 .read = pnv_xive2_ic_lsi_read, 1502 .write = pnv_xive2_ic_lsi_write, 1503 .endianness = DEVICE_BIG_ENDIAN, 1504 .valid = { 1505 .min_access_size = 8, 1506 .max_access_size = 8, 1507 }, 1508 .impl = { 1509 .min_access_size = 8, 1510 .max_access_size = 8, 1511 }, 1512 }; 1513 1514 /* 1515 * Sync MMIO page (write only) 1516 */ 1517 #define PNV_XIVE2_SYNC_IPI 0x000 1518 #define PNV_XIVE2_SYNC_HW 0x080 1519 #define PNV_XIVE2_SYNC_NxC 0x100 1520 #define PNV_XIVE2_SYNC_INT 0x180 1521 #define PNV_XIVE2_SYNC_OS_ESC 0x200 1522 #define PNV_XIVE2_SYNC_POOL_ESC 0x280 1523 #define PNV_XIVE2_SYNC_HARD_ESC 0x300 1524 1525 static uint64_t pnv_xive2_ic_sync_read(void *opaque, hwaddr offset, 1526 unsigned size) 1527 { 1528 PnvXive2 *xive = PNV_XIVE2(opaque); 1529 1530 /* loads are invalid */ 1531 xive2_error(xive, "SYNC: invalid read @%"HWADDR_PRIx, offset); 1532 return -1; 1533 } 1534 1535 static void pnv_xive2_ic_sync_write(void *opaque, hwaddr offset, 1536 uint64_t val, unsigned size) 1537 { 1538 PnvXive2 *xive = PNV_XIVE2(opaque); 1539 1540 switch (offset) { 1541 case PNV_XIVE2_SYNC_IPI: 1542 case PNV_XIVE2_SYNC_HW: 1543 case PNV_XIVE2_SYNC_NxC: 1544 case PNV_XIVE2_SYNC_INT: 1545 case PNV_XIVE2_SYNC_OS_ESC: 1546 case PNV_XIVE2_SYNC_POOL_ESC: 1547 case PNV_XIVE2_SYNC_HARD_ESC: 1548 break; 1549 default: 1550 xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset); 1551 } 1552 } 1553 1554 static const MemoryRegionOps pnv_xive2_ic_sync_ops = { 1555 .read = pnv_xive2_ic_sync_read, 1556 .write = pnv_xive2_ic_sync_write, 1557 .endianness = DEVICE_BIG_ENDIAN, 1558 .valid = { 1559 .min_access_size = 8, 1560 .max_access_size = 8, 1561 }, 1562 .impl = { 1563 .min_access_size = 8, 1564 .max_access_size = 8, 1565 }, 1566 }; 1567 1568 /* 1569 * When the TM direct pages of the IC controller are accessed, the 1570 * target HW thread is deduced from the page offset. 1571 */ 1572 static uint32_t pnv_xive2_ic_tm_get_pir(PnvXive2 *xive, hwaddr offset) 1573 { 1574 /* On P10, the node ID shift in the PIR register is 8 bits */ 1575 return xive->chip->chip_id << 8 | offset >> xive->ic_shift; 1576 } 1577 1578 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) 1579 { 1580 PnvChip *chip = xive->chip; 1581 PowerPCCPU *cpu = NULL; 1582 1583 cpu = pnv_chip_find_cpu(chip, pir); 1584 if (!cpu) { 1585 xive2_error(xive, "IC: invalid PIR %x for indirect access", pir); 1586 return NULL; 1587 } 1588 1589 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 1590 xive2_error(xive, "IC: CPU %x is not enabled", pir); 1591 } 1592 1593 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1594 } 1595 1596 static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset, 1597 unsigned size) 1598 { 1599 PnvXive2 *xive = PNV_XIVE2(opaque); 1600 uint32_t pir; 1601 XiveTCTX *tctx; 1602 uint64_t val = -1; 1603 1604 pir = pnv_xive2_ic_tm_get_pir(xive, offset); 1605 tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1606 if (tctx) { 1607 val = xive_tctx_tm_read(NULL, tctx, offset, size); 1608 } 1609 1610 return val; 1611 } 1612 1613 static void pnv_xive2_ic_tm_indirect_write(void *opaque, hwaddr offset, 1614 uint64_t val, unsigned size) 1615 { 1616 PnvXive2 *xive = PNV_XIVE2(opaque); 1617 uint32_t pir; 1618 XiveTCTX *tctx; 1619 1620 pir = pnv_xive2_ic_tm_get_pir(xive, offset); 1621 tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1622 if (tctx) { 1623 xive_tctx_tm_write(NULL, tctx, offset, val, size); 1624 } 1625 } 1626 1627 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = { 1628 .read = pnv_xive2_ic_tm_indirect_read, 1629 .write = pnv_xive2_ic_tm_indirect_write, 1630 .endianness = DEVICE_BIG_ENDIAN, 1631 .valid = { 1632 .min_access_size = 8, 1633 .max_access_size = 8, 1634 }, 1635 .impl = { 1636 .min_access_size = 8, 1637 .max_access_size = 8, 1638 }, 1639 }; 1640 1641 /* 1642 * TIMA ops 1643 */ 1644 1645 /* 1646 * Special TIMA offsets to handle accesses in a POWER10 way. 1647 * 1648 * Only the CAM line updates done by the hypervisor should be handled 1649 * specifically. 1650 */ 1651 #define HV_PAGE_OFFSET (XIVE_TM_HV_PAGE << TM_SHIFT) 1652 #define HV_PUSH_OS_CTX_OFFSET (HV_PAGE_OFFSET | (TM_QW1_OS + TM_WORD2)) 1653 #define HV_PULL_OS_CTX_OFFSET (HV_PAGE_OFFSET | TM_SPC_PULL_OS_CTX) 1654 1655 static void pnv_xive2_tm_write(void *opaque, hwaddr offset, 1656 uint64_t value, unsigned size) 1657 { 1658 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1659 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1660 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1661 XivePresenter *xptr = XIVE_PRESENTER(xive); 1662 bool gen1_tima_os = 1663 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 1664 1665 /* TODO: should we switch the TM ops table instead ? */ 1666 if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) { 1667 xive2_tm_push_os_ctx(xptr, tctx, offset, value, size); 1668 return; 1669 } 1670 1671 /* Other TM ops are the same as XIVE1 */ 1672 xive_tctx_tm_write(xptr, tctx, offset, value, size); 1673 } 1674 1675 static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) 1676 { 1677 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1678 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1679 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1680 XivePresenter *xptr = XIVE_PRESENTER(xive); 1681 bool gen1_tima_os = 1682 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 1683 1684 /* TODO: should we switch the TM ops table instead ? */ 1685 if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) { 1686 return xive2_tm_pull_os_ctx(xptr, tctx, offset, size); 1687 } 1688 1689 /* Other TM ops are the same as XIVE1 */ 1690 return xive_tctx_tm_read(xptr, tctx, offset, size); 1691 } 1692 1693 static const MemoryRegionOps pnv_xive2_tm_ops = { 1694 .read = pnv_xive2_tm_read, 1695 .write = pnv_xive2_tm_write, 1696 .endianness = DEVICE_BIG_ENDIAN, 1697 .valid = { 1698 .min_access_size = 1, 1699 .max_access_size = 8, 1700 }, 1701 .impl = { 1702 .min_access_size = 1, 1703 .max_access_size = 8, 1704 }, 1705 }; 1706 1707 static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset, 1708 unsigned size) 1709 { 1710 PnvXive2 *xive = PNV_XIVE2(opaque); 1711 1712 xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset); 1713 return -1; 1714 } 1715 1716 static void pnv_xive2_nvc_write(void *opaque, hwaddr offset, 1717 uint64_t val, unsigned size) 1718 { 1719 PnvXive2 *xive = PNV_XIVE2(opaque); 1720 1721 xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset); 1722 } 1723 1724 static const MemoryRegionOps pnv_xive2_nvc_ops = { 1725 .read = pnv_xive2_nvc_read, 1726 .write = pnv_xive2_nvc_write, 1727 .endianness = DEVICE_BIG_ENDIAN, 1728 .valid = { 1729 .min_access_size = 8, 1730 .max_access_size = 8, 1731 }, 1732 .impl = { 1733 .min_access_size = 8, 1734 .max_access_size = 8, 1735 }, 1736 }; 1737 1738 static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset, 1739 unsigned size) 1740 { 1741 PnvXive2 *xive = PNV_XIVE2(opaque); 1742 1743 xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset); 1744 return -1; 1745 } 1746 1747 static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset, 1748 uint64_t val, unsigned size) 1749 { 1750 PnvXive2 *xive = PNV_XIVE2(opaque); 1751 1752 xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset); 1753 } 1754 1755 static const MemoryRegionOps pnv_xive2_nvpg_ops = { 1756 .read = pnv_xive2_nvpg_read, 1757 .write = pnv_xive2_nvpg_write, 1758 .endianness = DEVICE_BIG_ENDIAN, 1759 .valid = { 1760 .min_access_size = 8, 1761 .max_access_size = 8, 1762 }, 1763 .impl = { 1764 .min_access_size = 8, 1765 .max_access_size = 8, 1766 }, 1767 }; 1768 1769 /* 1770 * POWER10 default capabilities: 0x2000120076f000FC 1771 */ 1772 #define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC 1773 1774 /* 1775 * POWER10 default configuration: 0x0030000033000000 1776 * 1777 * 8bits thread id was dropped for P10 1778 */ 1779 #define PNV_XIVE2_CONFIGURATION 0x0030000033000000 1780 1781 static void pnv_xive2_reset(void *dev) 1782 { 1783 PnvXive2 *xive = PNV_XIVE2(dev); 1784 XiveSource *xsrc = &xive->ipi_source; 1785 Xive2EndSource *end_xsrc = &xive->end_source; 1786 1787 xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities; 1788 xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config; 1789 1790 /* HW hardwires the #Topology of the chip in the block field */ 1791 xive->cq_regs[CQ_XIVE_CFG >> 3] |= 1792 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id); 1793 1794 /* Set default page size to 64k */ 1795 xive->ic_shift = xive->esb_shift = xive->end_shift = 16; 1796 xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16; 1797 1798 /* Clear source MMIOs */ 1799 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 1800 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); 1801 } 1802 1803 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 1804 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); 1805 } 1806 } 1807 1808 /* 1809 * Maximum number of IRQs and ENDs supported by HW. Will be tuned by 1810 * software. 1811 */ 1812 #define PNV_XIVE2_NR_IRQS (PNV10_XIVE2_ESB_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1813 #define PNV_XIVE2_NR_ENDS (PNV10_XIVE2_END_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1814 1815 static void pnv_xive2_realize(DeviceState *dev, Error **errp) 1816 { 1817 PnvXive2 *xive = PNV_XIVE2(dev); 1818 PnvXive2Class *pxc = PNV_XIVE2_GET_CLASS(dev); 1819 XiveSource *xsrc = &xive->ipi_source; 1820 Xive2EndSource *end_xsrc = &xive->end_source; 1821 Error *local_err = NULL; 1822 int i; 1823 1824 pxc->parent_realize(dev, &local_err); 1825 if (local_err) { 1826 error_propagate(errp, local_err); 1827 return; 1828 } 1829 1830 assert(xive->chip); 1831 1832 /* 1833 * The XiveSource and Xive2EndSource objects are realized with the 1834 * maximum allowed HW configuration. The ESB MMIO regions will be 1835 * resized dynamically when the controller is configured by the FW 1836 * to limit accesses to resources not provisioned. 1837 */ 1838 object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI, 1839 &error_fatal); 1840 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS, 1841 &error_fatal); 1842 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), 1843 &error_fatal); 1844 qdev_realize(DEVICE(xsrc), NULL, &local_err); 1845 if (local_err) { 1846 error_propagate(errp, local_err); 1847 return; 1848 } 1849 1850 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS, 1851 &error_fatal); 1852 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 1853 &error_abort); 1854 qdev_realize(DEVICE(end_xsrc), NULL, &local_err); 1855 if (local_err) { 1856 error_propagate(errp, local_err); 1857 return; 1858 } 1859 1860 /* XSCOM region, used for initial configuration of the BARs */ 1861 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), 1862 &pnv_xive2_xscom_ops, xive, "xscom-xive", 1863 PNV10_XSCOM_XIVE2_SIZE << 3); 1864 1865 /* Interrupt controller MMIO regions */ 1866 xive->ic_shift = 16; 1867 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 1868 PNV10_XIVE2_IC_SIZE); 1869 1870 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 1871 memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev), 1872 pnv_xive2_ic_regions[i].ops, xive, 1873 pnv_xive2_ic_regions[i].name, 1874 pnv_xive2_ic_regions[i].pgsize << xive->ic_shift); 1875 } 1876 1877 /* 1878 * VC MMIO regions. 1879 */ 1880 xive->esb_shift = 16; 1881 xive->end_shift = 16; 1882 memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb", 1883 PNV10_XIVE2_ESB_SIZE); 1884 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end", 1885 PNV10_XIVE2_END_SIZE); 1886 1887 /* Presenter Controller MMIO region (not modeled) */ 1888 xive->nvc_shift = 16; 1889 xive->nvpg_shift = 16; 1890 memory_region_init_io(&xive->nvc_mmio, OBJECT(dev), 1891 &pnv_xive2_nvc_ops, xive, 1892 "xive-nvc", PNV10_XIVE2_NVC_SIZE); 1893 1894 memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev), 1895 &pnv_xive2_nvpg_ops, xive, 1896 "xive-nvpg", PNV10_XIVE2_NVPG_SIZE); 1897 1898 /* Thread Interrupt Management Area (Direct) */ 1899 xive->tm_shift = 16; 1900 memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops, 1901 xive, "xive-tima", PNV10_XIVE2_TM_SIZE); 1902 1903 qemu_register_reset(pnv_xive2_reset, dev); 1904 } 1905 1906 static Property pnv_xive2_properties[] = { 1907 DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0), 1908 DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0), 1909 DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0), 1910 DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0), 1911 DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0), 1912 DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0), 1913 DEFINE_PROP_UINT64("capabilities", PnvXive2, capabilities, 1914 PNV_XIVE2_CAPABILITIES), 1915 DEFINE_PROP_UINT64("config", PnvXive2, config, 1916 PNV_XIVE2_CONFIGURATION), 1917 DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *), 1918 DEFINE_PROP_END_OF_LIST(), 1919 }; 1920 1921 static void pnv_xive2_instance_init(Object *obj) 1922 { 1923 PnvXive2 *xive = PNV_XIVE2(obj); 1924 1925 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 1926 TYPE_XIVE_SOURCE); 1927 object_initialize_child(obj, "end_source", &xive->end_source, 1928 TYPE_XIVE2_END_SOURCE); 1929 } 1930 1931 static int pnv_xive2_dt_xscom(PnvXScomInterface *dev, void *fdt, 1932 int xscom_offset) 1933 { 1934 const char compat_p10[] = "ibm,power10-xive-x"; 1935 char *name; 1936 int offset; 1937 uint32_t reg[] = { 1938 cpu_to_be32(PNV10_XSCOM_XIVE2_BASE), 1939 cpu_to_be32(PNV10_XSCOM_XIVE2_SIZE) 1940 }; 1941 1942 name = g_strdup_printf("xive@%x", PNV10_XSCOM_XIVE2_BASE); 1943 offset = fdt_add_subnode(fdt, xscom_offset, name); 1944 _FDT(offset); 1945 g_free(name); 1946 1947 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 1948 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, 1949 sizeof(compat_p10))); 1950 return 0; 1951 } 1952 1953 static void pnv_xive2_class_init(ObjectClass *klass, void *data) 1954 { 1955 DeviceClass *dc = DEVICE_CLASS(klass); 1956 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 1957 Xive2RouterClass *xrc = XIVE2_ROUTER_CLASS(klass); 1958 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1959 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 1960 PnvXive2Class *pxc = PNV_XIVE2_CLASS(klass); 1961 1962 xdc->dt_xscom = pnv_xive2_dt_xscom; 1963 1964 dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)"; 1965 device_class_set_parent_realize(dc, pnv_xive2_realize, 1966 &pxc->parent_realize); 1967 device_class_set_props(dc, pnv_xive2_properties); 1968 1969 xrc->get_eas = pnv_xive2_get_eas; 1970 xrc->get_pq = pnv_xive2_get_pq; 1971 xrc->set_pq = pnv_xive2_set_pq; 1972 xrc->get_end = pnv_xive2_get_end; 1973 xrc->write_end = pnv_xive2_write_end; 1974 xrc->get_nvp = pnv_xive2_get_nvp; 1975 xrc->write_nvp = pnv_xive2_write_nvp; 1976 xrc->get_config = pnv_xive2_get_config; 1977 xrc->get_block_id = pnv_xive2_get_block_id; 1978 1979 xnc->notify = pnv_xive2_notify; 1980 1981 xpc->match_nvt = pnv_xive2_match_nvt; 1982 }; 1983 1984 static const TypeInfo pnv_xive2_info = { 1985 .name = TYPE_PNV_XIVE2, 1986 .parent = TYPE_XIVE2_ROUTER, 1987 .instance_init = pnv_xive2_instance_init, 1988 .instance_size = sizeof(PnvXive2), 1989 .class_init = pnv_xive2_class_init, 1990 .class_size = sizeof(PnvXive2Class), 1991 .interfaces = (InterfaceInfo[]) { 1992 { TYPE_PNV_XSCOM_INTERFACE }, 1993 { } 1994 } 1995 }; 1996 1997 static void pnv_xive2_register_types(void) 1998 { 1999 type_register_static(&pnv_xive2_info); 2000 } 2001 2002 type_init(pnv_xive2_register_types) 2003 2004 static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, 2005 Monitor *mon) 2006 { 2007 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 2008 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 2009 2010 if (!xive2_nvp_is_valid(nvp)) { 2011 return; 2012 } 2013 2014 monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x", 2015 nvp_idx, eq_blk, eq_idx, 2016 xive_get_field32(NVP2_W2_IPB, nvp->w2)); 2017 /* 2018 * When the NVP is HW controlled, more fields are updated 2019 */ 2020 if (xive2_nvp_is_hw(nvp)) { 2021 monitor_printf(mon, " CPPR:%02x", 2022 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 2023 if (xive2_nvp_is_co(nvp)) { 2024 monitor_printf(mon, " CO:%04x", 2025 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 2026 } 2027 } 2028 monitor_printf(mon, "\n"); 2029 } 2030 2031 /* 2032 * If the table is direct, we can compute the number of PQ entries 2033 * provisioned by FW. 2034 */ 2035 static uint32_t pnv_xive2_nr_esbs(PnvXive2 *xive) 2036 { 2037 uint8_t blk = pnv_xive2_block_id(xive); 2038 uint64_t vsd = xive->vsds[VST_ESB][blk]; 2039 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 2040 2041 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 2042 } 2043 2044 /* 2045 * Compute the number of entries per indirect subpage. 2046 */ 2047 static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type) 2048 { 2049 uint8_t blk = pnv_xive2_block_id(xive); 2050 uint64_t vsd = xive->vsds[type][blk]; 2051 const XiveVstInfo *info = &vst_infos[type]; 2052 uint64_t vsd_addr; 2053 uint32_t page_shift; 2054 2055 /* For direct tables, fake a valid value */ 2056 if (!(VSD_INDIRECT & vsd)) { 2057 return 1; 2058 } 2059 2060 /* Get the page size of the indirect table. */ 2061 vsd_addr = vsd & VSD_ADDRESS_MASK; 2062 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 2063 2064 if (!(vsd & VSD_ADDRESS_MASK)) { 2065 #ifdef XIVE2_DEBUG 2066 xive2_error(xive, "VST: invalid %s entry!?", info->name); 2067 #endif 2068 return 0; 2069 } 2070 2071 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 2072 2073 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 2074 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 2075 page_shift); 2076 return 0; 2077 } 2078 2079 return (1ull << page_shift) / info->size; 2080 } 2081 2082 void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon) 2083 { 2084 Xive2Router *xrtr = XIVE2_ROUTER(xive); 2085 uint8_t blk = pnv_xive2_block_id(xive); 2086 uint8_t chip_id = xive->chip->chip_id; 2087 uint32_t srcno0 = XIVE_EAS(blk, 0); 2088 uint32_t nr_esbs = pnv_xive2_nr_esbs(xive); 2089 Xive2Eas eas; 2090 Xive2End end; 2091 Xive2Nvp nvp; 2092 int i; 2093 uint64_t xive_nvp_per_subpage; 2094 2095 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, 2096 srcno0 + nr_esbs - 1); 2097 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); 2098 2099 monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, 2100 srcno0 + nr_esbs - 1); 2101 for (i = 0; i < nr_esbs; i++) { 2102 if (xive2_router_get_eas(xrtr, blk, i, &eas)) { 2103 break; 2104 } 2105 if (!xive2_eas_is_masked(&eas)) { 2106 xive2_eas_pic_print_info(&eas, i, mon); 2107 } 2108 } 2109 2110 monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); 2111 i = 0; 2112 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2113 xive2_end_eas_pic_print_info(&end, i++, mon); 2114 } 2115 2116 monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); 2117 i = 0; 2118 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2119 xive2_end_pic_print_info(&end, i++, mon); 2120 } 2121 2122 monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk, 2123 0, XIVE2_NVP_COUNT - 1); 2124 xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); 2125 for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) { 2126 while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) { 2127 xive2_nvp_pic_print_info(&nvp, i++, mon); 2128 } 2129 } 2130 } 2131