1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "sysemu/cpus.h" 15 #include "sysemu/dma.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/pnv.h" 19 #include "hw/ppc/pnv_core.h" 20 #include "hw/ppc/pnv_xscom.h" 21 #include "hw/ppc/xive2.h" 22 #include "hw/ppc/pnv_xive.h" 23 #include "hw/ppc/xive_regs.h" 24 #include "hw/ppc/xive2_regs.h" 25 #include "hw/ppc/ppc.h" 26 #include "hw/qdev-properties.h" 27 #include "sysemu/reset.h" 28 29 #include <libfdt.h> 30 31 #include "pnv_xive2_regs.h" 32 33 #undef XIVE2_DEBUG 34 35 /* 36 * Virtual structures table (VST) 37 */ 38 #define SBE_PER_BYTE 4 39 40 typedef struct XiveVstInfo { 41 const char *name; 42 uint32_t size; 43 uint32_t max_blocks; 44 } XiveVstInfo; 45 46 static const XiveVstInfo vst_infos[] = { 47 48 [VST_EAS] = { "EAT", sizeof(Xive2Eas), 16 }, 49 [VST_ESB] = { "ESB", 1, 16 }, 50 [VST_END] = { "ENDT", sizeof(Xive2End), 16 }, 51 52 [VST_NVP] = { "NVPT", sizeof(Xive2Nvp), 16 }, 53 [VST_NVG] = { "NVGT", sizeof(Xive2Nvgc), 16 }, 54 [VST_NVC] = { "NVCT", sizeof(Xive2Nvgc), 16 }, 55 56 [VST_IC] = { "IC", 1 /* ? */ , 16 }, /* Topology # */ 57 [VST_SYNC] = { "SYNC", 1 /* ? */ , 16 }, /* Topology # */ 58 59 /* 60 * This table contains the backing store pages for the interrupt 61 * fifos of the VC sub-engine in case of overflow. 62 * 63 * 0 - IPI, 64 * 1 - HWD, 65 * 2 - NxC, 66 * 3 - INT, 67 * 4 - OS-Queue, 68 * 5 - Pool-Queue, 69 * 6 - Hard-Queue 70 */ 71 [VST_ERQ] = { "ERQ", 1, VC_QUEUE_COUNT }, 72 }; 73 74 #define xive2_error(xive, fmt, ...) \ 75 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 76 (xive)->chip->chip_id, ## __VA_ARGS__); 77 78 /* 79 * QEMU version of the GETFIELD/SETFIELD macros 80 * 81 * TODO: It might be better to use the existing extract64() and 82 * deposit64() but this means that all the register definitions will 83 * change and become incompatible with the ones found in skiboot. 84 * 85 * Keep it as it is for now until we find a common ground. 86 */ 87 static inline uint64_t GETFIELD(uint64_t mask, uint64_t word) 88 { 89 return (word & mask) >> ctz64(mask); 90 } 91 92 static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, 93 uint64_t value) 94 { 95 return (word & ~mask) | ((value << ctz64(mask)) & mask); 96 } 97 98 /* 99 * TODO: Document block id override 100 */ 101 static uint32_t pnv_xive2_block_id(PnvXive2 *xive) 102 { 103 uint8_t blk = xive->chip->chip_id; 104 uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3]; 105 106 if (cfg_val & CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE) { 107 blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val); 108 } 109 110 return blk; 111 } 112 113 /* 114 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 115 * of the chips is good enough. 116 * 117 * TODO: Block scope support 118 */ 119 static PnvXive2 *pnv_xive2_get_remote(uint8_t blk) 120 { 121 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 122 int i; 123 124 for (i = 0; i < pnv->num_chips; i++) { 125 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 126 PnvXive2 *xive = &chip10->xive; 127 128 if (pnv_xive2_block_id(xive) == blk) { 129 return xive; 130 } 131 } 132 return NULL; 133 } 134 135 /* 136 * VST accessors for ESB, EAT, ENDT, NVP 137 * 138 * Indirect VST tables are arrays of VSDs pointing to a page (of same 139 * size). Each page is a direct VST table. 140 */ 141 142 #define XIVE_VSD_SIZE 8 143 144 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 145 static uint64_t pnv_xive2_vst_page_size_allowed(uint32_t page_shift) 146 { 147 return page_shift == 12 || page_shift == 16 || 148 page_shift == 21 || page_shift == 24; 149 } 150 151 static uint64_t pnv_xive2_vst_addr_direct(PnvXive2 *xive, uint32_t type, 152 uint64_t vsd, uint32_t idx) 153 { 154 const XiveVstInfo *info = &vst_infos[type]; 155 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 156 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 157 uint32_t idx_max; 158 159 idx_max = vst_tsize / info->size - 1; 160 if (idx > idx_max) { 161 #ifdef XIVE2_DEBUG 162 xive2_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 163 info->name, idx, idx_max); 164 #endif 165 return 0; 166 } 167 168 return vst_addr + idx * info->size; 169 } 170 171 static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type, 172 uint64_t vsd, uint32_t idx) 173 { 174 const XiveVstInfo *info = &vst_infos[type]; 175 uint64_t vsd_addr; 176 uint32_t vsd_idx; 177 uint32_t page_shift; 178 uint32_t vst_per_page; 179 180 /* Get the page size of the indirect table. */ 181 vsd_addr = vsd & VSD_ADDRESS_MASK; 182 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 183 184 if (!(vsd & VSD_ADDRESS_MASK)) { 185 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 186 return 0; 187 } 188 189 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 190 191 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 192 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 193 page_shift); 194 return 0; 195 } 196 197 vst_per_page = (1ull << page_shift) / info->size; 198 vsd_idx = idx / vst_per_page; 199 200 /* Load the VSD we are looking for, if not already done */ 201 if (vsd_idx) { 202 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 203 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, 204 MEMTXATTRS_UNSPECIFIED); 205 206 if (!(vsd & VSD_ADDRESS_MASK)) { 207 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 208 return 0; 209 } 210 211 /* 212 * Check that the pages have a consistent size across the 213 * indirect table 214 */ 215 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 216 xive2_error(xive, "VST: %s entry %x indirect page size differ !?", 217 info->name, idx); 218 return 0; 219 } 220 } 221 222 return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 223 } 224 225 static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk, 226 uint32_t idx) 227 { 228 const XiveVstInfo *info = &vst_infos[type]; 229 uint64_t vsd; 230 231 if (blk >= info->max_blocks) { 232 xive2_error(xive, "VST: invalid block id %d for VST %s %d !?", 233 blk, info->name, idx); 234 return 0; 235 } 236 237 vsd = xive->vsds[type][blk]; 238 239 /* Remote VST access */ 240 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 241 xive = pnv_xive2_get_remote(blk); 242 243 return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0; 244 } 245 246 if (VSD_INDIRECT & vsd) { 247 return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx); 248 } 249 250 return pnv_xive2_vst_addr_direct(xive, type, vsd, idx); 251 } 252 253 static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk, 254 uint32_t idx, void *data) 255 { 256 const XiveVstInfo *info = &vst_infos[type]; 257 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 258 259 if (!addr) { 260 return -1; 261 } 262 263 cpu_physical_memory_read(addr, data, info->size); 264 return 0; 265 } 266 267 #define XIVE_VST_WORD_ALL -1 268 269 static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk, 270 uint32_t idx, void *data, uint32_t word_number) 271 { 272 const XiveVstInfo *info = &vst_infos[type]; 273 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 274 275 if (!addr) { 276 return -1; 277 } 278 279 if (word_number == XIVE_VST_WORD_ALL) { 280 cpu_physical_memory_write(addr, data, info->size); 281 } else { 282 cpu_physical_memory_write(addr + word_number * 4, 283 data + word_number * 4, 4); 284 } 285 return 0; 286 } 287 288 static int pnv_xive2_get_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 289 uint8_t *pq) 290 { 291 PnvXive2 *xive = PNV_XIVE2(xrtr); 292 293 if (pnv_xive2_block_id(xive) != blk) { 294 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 295 return -1; 296 } 297 298 *pq = xive_source_esb_get(&xive->ipi_source, idx); 299 return 0; 300 } 301 302 static int pnv_xive2_set_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 303 uint8_t *pq) 304 { 305 PnvXive2 *xive = PNV_XIVE2(xrtr); 306 307 if (pnv_xive2_block_id(xive) != blk) { 308 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 309 return -1; 310 } 311 312 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq); 313 return 0; 314 } 315 316 static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 317 Xive2End *end) 318 { 319 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_END, blk, idx, end); 320 } 321 322 static int pnv_xive2_write_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 323 Xive2End *end, uint8_t word_number) 324 { 325 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_END, blk, idx, end, 326 word_number); 327 } 328 329 static int pnv_xive2_end_update(PnvXive2 *xive) 330 { 331 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 332 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 333 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 334 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 335 int i; 336 uint64_t endc_watch[4]; 337 338 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 339 endc_watch[i] = 340 cpu_to_be64(xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i]); 341 } 342 343 return pnv_xive2_vst_write(xive, VST_END, blk, idx, endc_watch, 344 XIVE_VST_WORD_ALL); 345 } 346 347 static void pnv_xive2_end_cache_load(PnvXive2 *xive) 348 { 349 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 350 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 351 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 352 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 353 uint64_t endc_watch[4] = { 0 }; 354 int i; 355 356 if (pnv_xive2_vst_read(xive, VST_END, blk, idx, endc_watch)) { 357 xive2_error(xive, "VST: no END entry %x/%x !?", blk, idx); 358 } 359 360 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 361 xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i] = 362 be64_to_cpu(endc_watch[i]); 363 } 364 } 365 366 static int pnv_xive2_get_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 367 Xive2Nvp *nvp) 368 { 369 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp); 370 } 371 372 static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 373 Xive2Nvp *nvp, uint8_t word_number) 374 { 375 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp, 376 word_number); 377 } 378 379 static int pnv_xive2_nvp_update(PnvXive2 *xive) 380 { 381 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 382 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 383 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 384 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 385 int i; 386 uint64_t nxc_watch[4]; 387 388 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 389 nxc_watch[i] = 390 cpu_to_be64(xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i]); 391 } 392 393 return pnv_xive2_vst_write(xive, VST_NVP, blk, idx, nxc_watch, 394 XIVE_VST_WORD_ALL); 395 } 396 397 static void pnv_xive2_nvp_cache_load(PnvXive2 *xive) 398 { 399 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 400 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 401 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 402 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 403 uint64_t nxc_watch[4] = { 0 }; 404 int i; 405 406 if (pnv_xive2_vst_read(xive, VST_NVP, blk, idx, nxc_watch)) { 407 xive2_error(xive, "VST: no NVP entry %x/%x !?", blk, idx); 408 } 409 410 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 411 xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i] = 412 be64_to_cpu(nxc_watch[i]); 413 } 414 } 415 416 static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 417 Xive2Eas *eas) 418 { 419 PnvXive2 *xive = PNV_XIVE2(xrtr); 420 421 if (pnv_xive2_block_id(xive) != blk) { 422 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 423 return -1; 424 } 425 426 return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas); 427 } 428 429 static uint32_t pnv_xive2_get_config(Xive2Router *xrtr) 430 { 431 PnvXive2 *xive = PNV_XIVE2(xrtr); 432 uint32_t cfg = 0; 433 434 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { 435 cfg |= XIVE2_GEN1_TIMA_OS; 436 } 437 438 return cfg; 439 } 440 441 static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu) 442 { 443 int pir = ppc_cpu_pir(cpu); 444 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); 445 uint64_t reg = fc < 8 ? TCTXT_EN0 : TCTXT_EN1; 446 uint32_t bit = pir & 0x3f; 447 448 return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit); 449 } 450 451 static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, 452 uint8_t nvt_blk, uint32_t nvt_idx, 453 bool cam_ignore, uint8_t priority, 454 uint32_t logic_serv, XiveTCTXMatch *match) 455 { 456 PnvXive2 *xive = PNV_XIVE2(xptr); 457 PnvChip *chip = xive->chip; 458 int count = 0; 459 int i, j; 460 bool gen1_tima_os = 461 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 462 463 for (i = 0; i < chip->nr_cores; i++) { 464 PnvCore *pc = chip->cores[i]; 465 CPUCore *cc = CPU_CORE(pc); 466 467 for (j = 0; j < cc->nr_threads; j++) { 468 PowerPCCPU *cpu = pc->threads[j]; 469 XiveTCTX *tctx; 470 int ring; 471 472 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 473 continue; 474 } 475 476 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 477 478 if (gen1_tima_os) { 479 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, 480 nvt_idx, cam_ignore, 481 logic_serv); 482 } else { 483 ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk, 484 nvt_idx, cam_ignore, 485 logic_serv); 486 } 487 488 /* 489 * Save the context and follow on to catch duplicates, 490 * that we don't support yet. 491 */ 492 if (ring != -1) { 493 if (match->tctx) { 494 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 495 "thread context NVT %x/%x\n", 496 nvt_blk, nvt_idx); 497 return false; 498 } 499 500 match->ring = ring; 501 match->tctx = tctx; 502 count++; 503 } 504 } 505 } 506 507 return count; 508 } 509 510 static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) 511 { 512 return pnv_xive2_block_id(PNV_XIVE2(xrtr)); 513 } 514 515 /* 516 * The TIMA MMIO space is shared among the chips and to identify the 517 * chip from which the access is being done, we extract the chip id 518 * from the PIR. 519 */ 520 static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu) 521 { 522 int pir = ppc_cpu_pir(cpu); 523 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; 524 PnvXive2 *xive = PNV_XIVE2(xptr); 525 526 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 527 xive2_error(xive, "IC: CPU %x is not enabled", pir); 528 } 529 return xive; 530 } 531 532 /* 533 * The internal sources of the interrupt controller have no knowledge 534 * of the XIVE2 chip on which they reside. Encode the block id in the 535 * source interrupt number before forwarding the source event 536 * notification to the Router. This is required on a multichip system. 537 */ 538 static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked) 539 { 540 PnvXive2 *xive = PNV_XIVE2(xn); 541 uint8_t blk = pnv_xive2_block_id(xive); 542 543 xive2_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked); 544 } 545 546 /* 547 * Set Translation Tables 548 * 549 * TODO add support for multiple sets 550 */ 551 static int pnv_xive2_stt_set_data(PnvXive2 *xive, uint64_t val) 552 { 553 uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]); 554 uint8_t entry = GETFIELD(CQ_TAR_ENTRY_SELECT, 555 xive->cq_regs[CQ_TAR >> 3]); 556 557 switch (tsel) { 558 case CQ_TAR_NVPG: 559 case CQ_TAR_ESB: 560 case CQ_TAR_END: 561 xive->tables[tsel][entry] = val; 562 break; 563 default: 564 xive2_error(xive, "IC: unsupported table %d", tsel); 565 return -1; 566 } 567 568 if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) { 569 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT, 570 xive->cq_regs[CQ_TAR >> 3], ++entry); 571 } 572 573 return 0; 574 } 575 /* 576 * Virtual Structure Tables (VST) configuration 577 */ 578 static void pnv_xive2_vst_set_exclusive(PnvXive2 *xive, uint8_t type, 579 uint8_t blk, uint64_t vsd) 580 { 581 Xive2EndSource *end_xsrc = &xive->end_source; 582 XiveSource *xsrc = &xive->ipi_source; 583 const XiveVstInfo *info = &vst_infos[type]; 584 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 585 uint64_t vst_tsize = 1ull << page_shift; 586 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 587 588 /* Basic checks */ 589 590 if (VSD_INDIRECT & vsd) { 591 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 592 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 593 page_shift); 594 return; 595 } 596 } 597 598 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 599 xive2_error(xive, "VST: %s table address 0x%"PRIx64 600 " is not aligned with page shift %d", 601 info->name, vst_addr, page_shift); 602 return; 603 } 604 605 /* Record the table configuration (in SRAM on HW) */ 606 xive->vsds[type][blk] = vsd; 607 608 /* Now tune the models with the configuration provided by the FW */ 609 610 switch (type) { 611 case VST_ESB: 612 /* 613 * Backing store pages for the source PQ bits. The model does 614 * not use these PQ bits backed in RAM because the XiveSource 615 * model has its own. 616 * 617 * If the table is direct, we can compute the number of PQ 618 * entries provisioned by FW (such as skiboot) and resize the 619 * ESB window accordingly. 620 */ 621 if (!(VSD_INDIRECT & vsd)) { 622 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 623 * (1ull << xsrc->esb_shift)); 624 } 625 626 memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio); 627 break; 628 629 case VST_EAS: /* Nothing to be done */ 630 break; 631 632 case VST_END: 633 /* 634 * Backing store pages for the END. 635 */ 636 if (!(VSD_INDIRECT & vsd)) { 637 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 638 * (1ull << end_xsrc->esb_shift)); 639 } 640 memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio); 641 break; 642 643 case VST_NVP: /* Not modeled */ 644 case VST_NVG: /* Not modeled */ 645 case VST_NVC: /* Not modeled */ 646 case VST_IC: /* Not modeled */ 647 case VST_SYNC: /* Not modeled */ 648 case VST_ERQ: /* Not modeled */ 649 break; 650 651 default: 652 g_assert_not_reached(); 653 } 654 } 655 656 /* 657 * Both PC and VC sub-engines are configured as each use the Virtual 658 * Structure Tables 659 */ 660 static void pnv_xive2_vst_set_data(PnvXive2 *xive, uint64_t vsd) 661 { 662 uint8_t mode = GETFIELD(VSD_MODE, vsd); 663 uint8_t type = GETFIELD(VC_VSD_TABLE_SELECT, 664 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 665 uint8_t blk = GETFIELD(VC_VSD_TABLE_ADDRESS, 666 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 667 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 668 669 if (type > VST_ERQ) { 670 xive2_error(xive, "VST: invalid table type %d", type); 671 return; 672 } 673 674 if (blk >= vst_infos[type].max_blocks) { 675 xive2_error(xive, "VST: invalid block id %d for" 676 " %s table", blk, vst_infos[type].name); 677 return; 678 } 679 680 if (!vst_addr) { 681 xive2_error(xive, "VST: invalid %s table address", 682 vst_infos[type].name); 683 return; 684 } 685 686 switch (mode) { 687 case VSD_MODE_FORWARD: 688 xive->vsds[type][blk] = vsd; 689 break; 690 691 case VSD_MODE_EXCLUSIVE: 692 pnv_xive2_vst_set_exclusive(xive, type, blk, vsd); 693 break; 694 695 default: 696 xive2_error(xive, "VST: unsupported table mode %d", mode); 697 return; 698 } 699 } 700 701 /* 702 * MMIO handlers 703 */ 704 705 706 /* 707 * IC BAR layout 708 * 709 * Page 0: Internal CQ register accesses (reads & writes) 710 * Page 1: Internal PC register accesses (reads & writes) 711 * Page 2: Internal VC register accesses (reads & writes) 712 * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes) 713 * Page 4: Notify Port page (writes only, w/data), 714 * Page 5: Reserved 715 * Page 6: Sync Poll page (writes only, dataless) 716 * Page 7: Sync Inject page (writes only, dataless) 717 * Page 8: LSI Trigger page (writes only, dataless) 718 * Page 9: LSI SB Management page (reads & writes dataless) 719 * Pages 10-255: Reserved 720 * Pages 256-383: Direct mapped Thread Context Area (reads & writes) 721 * covering the 128 threads in P10. 722 * Pages 384-511: Reserved 723 */ 724 typedef struct PnvXive2Region { 725 const char *name; 726 uint32_t pgoff; 727 uint32_t pgsize; 728 const MemoryRegionOps *ops; 729 } PnvXive2Region; 730 731 static const MemoryRegionOps pnv_xive2_ic_cq_ops; 732 static const MemoryRegionOps pnv_xive2_ic_pc_ops; 733 static const MemoryRegionOps pnv_xive2_ic_vc_ops; 734 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops; 735 static const MemoryRegionOps pnv_xive2_ic_notify_ops; 736 static const MemoryRegionOps pnv_xive2_ic_sync_ops; 737 static const MemoryRegionOps pnv_xive2_ic_lsi_ops; 738 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops; 739 740 /* 512 pages. 4K: 2M range, 64K: 32M range */ 741 static const PnvXive2Region pnv_xive2_ic_regions[] = { 742 { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops }, 743 { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops }, 744 { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops }, 745 { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops }, 746 { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops }, 747 /* page 5 reserved */ 748 { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops }, 749 { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops }, 750 /* pages 10-255 reserved */ 751 { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops }, 752 /* pages 384-511 reserved */ 753 }; 754 755 /* 756 * CQ operations 757 */ 758 759 static uint64_t pnv_xive2_ic_cq_read(void *opaque, hwaddr offset, 760 unsigned size) 761 { 762 PnvXive2 *xive = PNV_XIVE2(opaque); 763 uint32_t reg = offset >> 3; 764 uint64_t val = 0; 765 766 switch (offset) { 767 case CQ_XIVE_CAP: /* Set at reset */ 768 case CQ_XIVE_CFG: 769 val = xive->cq_regs[reg]; 770 break; 771 case CQ_MSGSND: /* TODO check the #cores of the machine */ 772 val = 0xffffffff00000000; 773 break; 774 case CQ_CFG_PB_GEN: 775 val = CQ_CFG_PB_GEN_PB_INIT; /* TODO: fix CQ_CFG_PB_GEN default value */ 776 break; 777 default: 778 xive2_error(xive, "CQ: invalid read @%"HWADDR_PRIx, offset); 779 } 780 781 return val; 782 } 783 784 static uint64_t pnv_xive2_bar_size(uint64_t val) 785 { 786 return 1ull << (GETFIELD(CQ_BAR_RANGE, val) + 24); 787 } 788 789 static void pnv_xive2_ic_cq_write(void *opaque, hwaddr offset, 790 uint64_t val, unsigned size) 791 { 792 PnvXive2 *xive = PNV_XIVE2(opaque); 793 MemoryRegion *sysmem = get_system_memory(); 794 uint32_t reg = offset >> 3; 795 int i; 796 797 switch (offset) { 798 case CQ_XIVE_CFG: 799 case CQ_RST_CTL: /* TODO: reset all BARs */ 800 break; 801 802 case CQ_IC_BAR: 803 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 804 if (!(val & CQ_IC_BAR_VALID)) { 805 xive->ic_base = 0; 806 if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) { 807 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 808 memory_region_del_subregion(&xive->ic_mmio, 809 &xive->ic_mmios[i]); 810 } 811 memory_region_del_subregion(sysmem, &xive->ic_mmio); 812 } 813 } else { 814 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 815 if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) { 816 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 817 memory_region_add_subregion(&xive->ic_mmio, 818 pnv_xive2_ic_regions[i].pgoff << xive->ic_shift, 819 &xive->ic_mmios[i]); 820 } 821 memory_region_add_subregion(sysmem, xive->ic_base, 822 &xive->ic_mmio); 823 } 824 } 825 break; 826 827 case CQ_TM_BAR: 828 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 829 if (!(val & CQ_TM_BAR_VALID)) { 830 xive->tm_base = 0; 831 if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) { 832 memory_region_del_subregion(sysmem, &xive->tm_mmio); 833 } 834 } else { 835 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 836 if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) { 837 memory_region_add_subregion(sysmem, xive->tm_base, 838 &xive->tm_mmio); 839 } 840 } 841 break; 842 843 case CQ_ESB_BAR: 844 xive->esb_shift = val & CQ_BAR_64K ? 16 : 12; 845 if (!(val & CQ_BAR_VALID)) { 846 xive->esb_base = 0; 847 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 848 memory_region_del_subregion(sysmem, &xive->esb_mmio); 849 } 850 } else { 851 xive->esb_base = val & CQ_BAR_ADDR; 852 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 853 memory_region_set_size(&xive->esb_mmio, 854 pnv_xive2_bar_size(val)); 855 memory_region_add_subregion(sysmem, xive->esb_base, 856 &xive->esb_mmio); 857 } 858 } 859 break; 860 861 case CQ_END_BAR: 862 xive->end_shift = val & CQ_BAR_64K ? 16 : 12; 863 if (!(val & CQ_BAR_VALID)) { 864 xive->end_base = 0; 865 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 866 memory_region_del_subregion(sysmem, &xive->end_mmio); 867 } 868 } else { 869 xive->end_base = val & CQ_BAR_ADDR; 870 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 871 memory_region_set_size(&xive->end_mmio, 872 pnv_xive2_bar_size(val)); 873 memory_region_add_subregion(sysmem, xive->end_base, 874 &xive->end_mmio); 875 } 876 } 877 break; 878 879 case CQ_NVC_BAR: 880 xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12; 881 if (!(val & CQ_BAR_VALID)) { 882 xive->nvc_base = 0; 883 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 884 memory_region_del_subregion(sysmem, &xive->nvc_mmio); 885 } 886 } else { 887 xive->nvc_base = val & CQ_BAR_ADDR; 888 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 889 memory_region_set_size(&xive->nvc_mmio, 890 pnv_xive2_bar_size(val)); 891 memory_region_add_subregion(sysmem, xive->nvc_base, 892 &xive->nvc_mmio); 893 } 894 } 895 break; 896 897 case CQ_NVPG_BAR: 898 xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12; 899 if (!(val & CQ_BAR_VALID)) { 900 xive->nvpg_base = 0; 901 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 902 memory_region_del_subregion(sysmem, &xive->nvpg_mmio); 903 } 904 } else { 905 xive->nvpg_base = val & CQ_BAR_ADDR; 906 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 907 memory_region_set_size(&xive->nvpg_mmio, 908 pnv_xive2_bar_size(val)); 909 memory_region_add_subregion(sysmem, xive->nvpg_base, 910 &xive->nvpg_mmio); 911 } 912 } 913 break; 914 915 case CQ_TAR: /* Set Translation Table Address */ 916 break; 917 case CQ_TDR: /* Set Translation Table Data */ 918 pnv_xive2_stt_set_data(xive, val); 919 break; 920 case CQ_FIRMASK_OR: /* FIR error reporting */ 921 break; 922 default: 923 xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset); 924 return; 925 } 926 927 xive->cq_regs[reg] = val; 928 } 929 930 static const MemoryRegionOps pnv_xive2_ic_cq_ops = { 931 .read = pnv_xive2_ic_cq_read, 932 .write = pnv_xive2_ic_cq_write, 933 .endianness = DEVICE_BIG_ENDIAN, 934 .valid = { 935 .min_access_size = 8, 936 .max_access_size = 8, 937 }, 938 .impl = { 939 .min_access_size = 8, 940 .max_access_size = 8, 941 }, 942 }; 943 944 static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, 945 unsigned size) 946 { 947 PnvXive2 *xive = PNV_XIVE2(opaque); 948 uint64_t val = 0; 949 uint32_t reg = offset >> 3; 950 951 switch (offset) { 952 /* 953 * VSD table settings. 954 */ 955 case VC_VSD_TABLE_ADDR: 956 case VC_VSD_TABLE_DATA: 957 val = xive->vc_regs[reg]; 958 break; 959 960 /* 961 * ESB cache updates (not modeled) 962 */ 963 case VC_ESBC_FLUSH_CTRL: 964 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID; 965 val = xive->vc_regs[reg]; 966 break; 967 968 /* 969 * EAS cache updates (not modeled) 970 */ 971 case VC_EASC_FLUSH_CTRL: 972 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID; 973 val = xive->vc_regs[reg]; 974 break; 975 976 /* 977 * END cache updates 978 */ 979 case VC_ENDC_WATCH0_SPEC: 980 xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT); 981 val = xive->vc_regs[reg]; 982 break; 983 984 case VC_ENDC_WATCH0_DATA0: 985 /* 986 * Load DATA registers from cache with data requested by the 987 * SPEC register 988 */ 989 pnv_xive2_end_cache_load(xive); 990 val = xive->vc_regs[reg]; 991 break; 992 993 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 994 val = xive->vc_regs[reg]; 995 break; 996 997 case VC_ENDC_FLUSH_CTRL: 998 xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID; 999 val = xive->vc_regs[reg]; 1000 break; 1001 1002 /* 1003 * Indirect invalidation 1004 */ 1005 case VC_AT_MACRO_KILL_MASK: 1006 val = xive->vc_regs[reg]; 1007 break; 1008 1009 case VC_AT_MACRO_KILL: 1010 xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID; 1011 val = xive->vc_regs[reg]; 1012 break; 1013 1014 /* 1015 * Interrupt fifo overflow in memory backing store (Not modeled) 1016 */ 1017 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1018 val = xive->vc_regs[reg]; 1019 break; 1020 1021 /* 1022 * Synchronisation 1023 */ 1024 case VC_ENDC_SYNC_DONE: 1025 val = VC_ENDC_SYNC_POLL_DONE; 1026 break; 1027 default: 1028 xive2_error(xive, "VC: invalid read @%"HWADDR_PRIx, offset); 1029 } 1030 1031 return val; 1032 } 1033 1034 static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, 1035 uint64_t val, unsigned size) 1036 { 1037 PnvXive2 *xive = PNV_XIVE2(opaque); 1038 uint32_t reg = offset >> 3; 1039 1040 switch (offset) { 1041 /* 1042 * VSD table settings. 1043 */ 1044 case VC_VSD_TABLE_ADDR: 1045 break; 1046 case VC_VSD_TABLE_DATA: 1047 pnv_xive2_vst_set_data(xive, val); 1048 break; 1049 1050 /* 1051 * ESB cache updates (not modeled) 1052 */ 1053 /* case VC_ESBC_FLUSH_CTRL: */ 1054 case VC_ESBC_FLUSH_POLL: 1055 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; 1056 /* ESB update */ 1057 break; 1058 1059 /* 1060 * EAS cache updates (not modeled) 1061 */ 1062 /* case VC_EASC_FLUSH_CTRL: */ 1063 case VC_EASC_FLUSH_POLL: 1064 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; 1065 /* EAS update */ 1066 break; 1067 1068 /* 1069 * END cache updates 1070 */ 1071 case VC_ENDC_WATCH0_SPEC: 1072 val &= ~VC_ENDC_WATCH_CONFLICT; /* HW will set this bit */ 1073 break; 1074 1075 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1076 break; 1077 case VC_ENDC_WATCH0_DATA0: 1078 /* writing to DATA0 triggers the cache write */ 1079 xive->vc_regs[reg] = val; 1080 pnv_xive2_end_update(xive); 1081 break; 1082 1083 1084 /* case VC_ENDC_FLUSH_CTRL: */ 1085 case VC_ENDC_FLUSH_POLL: 1086 xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; 1087 break; 1088 1089 /* 1090 * Indirect invalidation 1091 */ 1092 case VC_AT_MACRO_KILL: 1093 case VC_AT_MACRO_KILL_MASK: 1094 break; 1095 1096 /* 1097 * Interrupt fifo overflow in memory backing store (Not modeled) 1098 */ 1099 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1100 break; 1101 1102 /* 1103 * Synchronisation 1104 */ 1105 case VC_ENDC_SYNC_DONE: 1106 break; 1107 1108 default: 1109 xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset); 1110 return; 1111 } 1112 1113 xive->vc_regs[reg] = val; 1114 } 1115 1116 static const MemoryRegionOps pnv_xive2_ic_vc_ops = { 1117 .read = pnv_xive2_ic_vc_read, 1118 .write = pnv_xive2_ic_vc_write, 1119 .endianness = DEVICE_BIG_ENDIAN, 1120 .valid = { 1121 .min_access_size = 8, 1122 .max_access_size = 8, 1123 }, 1124 .impl = { 1125 .min_access_size = 8, 1126 .max_access_size = 8, 1127 }, 1128 }; 1129 1130 static uint64_t pnv_xive2_ic_pc_read(void *opaque, hwaddr offset, 1131 unsigned size) 1132 { 1133 PnvXive2 *xive = PNV_XIVE2(opaque); 1134 uint64_t val = -1; 1135 uint32_t reg = offset >> 3; 1136 1137 switch (offset) { 1138 /* 1139 * VSD table settings. 1140 */ 1141 case PC_VSD_TABLE_ADDR: 1142 case PC_VSD_TABLE_DATA: 1143 val = xive->pc_regs[reg]; 1144 break; 1145 1146 /* 1147 * cache updates 1148 */ 1149 case PC_NXC_WATCH0_SPEC: 1150 xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT); 1151 val = xive->pc_regs[reg]; 1152 break; 1153 1154 case PC_NXC_WATCH0_DATA0: 1155 /* 1156 * Load DATA registers from cache with data requested by the 1157 * SPEC register 1158 */ 1159 pnv_xive2_nvp_cache_load(xive); 1160 val = xive->pc_regs[reg]; 1161 break; 1162 1163 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1164 val = xive->pc_regs[reg]; 1165 break; 1166 1167 case PC_NXC_FLUSH_CTRL: 1168 xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID; 1169 val = xive->pc_regs[reg]; 1170 break; 1171 1172 /* 1173 * Indirect invalidation 1174 */ 1175 case PC_AT_KILL: 1176 xive->pc_regs[reg] &= ~PC_AT_KILL_VALID; 1177 val = xive->pc_regs[reg]; 1178 break; 1179 1180 default: 1181 xive2_error(xive, "PC: invalid read @%"HWADDR_PRIx, offset); 1182 } 1183 1184 return val; 1185 } 1186 1187 static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset, 1188 uint64_t val, unsigned size) 1189 { 1190 PnvXive2 *xive = PNV_XIVE2(opaque); 1191 uint32_t reg = offset >> 3; 1192 1193 switch (offset) { 1194 1195 /* 1196 * VSD table settings. Only taken into account in the VC 1197 * sub-engine because the Xive2Router model combines both VC and PC 1198 * sub-engines 1199 */ 1200 case PC_VSD_TABLE_ADDR: 1201 case PC_VSD_TABLE_DATA: 1202 break; 1203 1204 /* 1205 * cache updates 1206 */ 1207 case PC_NXC_WATCH0_SPEC: 1208 val &= ~PC_NXC_WATCH_CONFLICT; /* HW will set this bit */ 1209 break; 1210 1211 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1212 break; 1213 case PC_NXC_WATCH0_DATA0: 1214 /* writing to DATA0 triggers the cache write */ 1215 xive->pc_regs[reg] = val; 1216 pnv_xive2_nvp_update(xive); 1217 break; 1218 1219 /* case PC_NXC_FLUSH_CTRL: */ 1220 case PC_NXC_FLUSH_POLL: 1221 xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; 1222 break; 1223 1224 /* 1225 * Indirect invalidation 1226 */ 1227 case PC_AT_KILL: 1228 case PC_AT_KILL_MASK: 1229 break; 1230 1231 default: 1232 xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset); 1233 return; 1234 } 1235 1236 xive->pc_regs[reg] = val; 1237 } 1238 1239 static const MemoryRegionOps pnv_xive2_ic_pc_ops = { 1240 .read = pnv_xive2_ic_pc_read, 1241 .write = pnv_xive2_ic_pc_write, 1242 .endianness = DEVICE_BIG_ENDIAN, 1243 .valid = { 1244 .min_access_size = 8, 1245 .max_access_size = 8, 1246 }, 1247 .impl = { 1248 .min_access_size = 8, 1249 .max_access_size = 8, 1250 }, 1251 }; 1252 1253 1254 static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset, 1255 unsigned size) 1256 { 1257 PnvXive2 *xive = PNV_XIVE2(opaque); 1258 uint64_t val = -1; 1259 uint32_t reg = offset >> 3; 1260 1261 switch (offset) { 1262 /* 1263 * XIVE2 hardware thread enablement 1264 */ 1265 case TCTXT_EN0: 1266 case TCTXT_EN1: 1267 val = xive->tctxt_regs[reg]; 1268 break; 1269 1270 case TCTXT_EN0_SET: 1271 case TCTXT_EN0_RESET: 1272 val = xive->tctxt_regs[TCTXT_EN0 >> 3]; 1273 break; 1274 case TCTXT_EN1_SET: 1275 case TCTXT_EN1_RESET: 1276 val = xive->tctxt_regs[TCTXT_EN1 >> 3]; 1277 break; 1278 default: 1279 xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); 1280 } 1281 1282 return val; 1283 } 1284 1285 static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, 1286 uint64_t val, unsigned size) 1287 { 1288 PnvXive2 *xive = PNV_XIVE2(opaque); 1289 uint32_t reg = offset >> 3; 1290 1291 switch (offset) { 1292 /* 1293 * XIVE2 hardware thread enablement 1294 */ 1295 case TCTXT_EN0: /* Physical Thread Enable */ 1296 case TCTXT_EN1: /* Physical Thread Enable (fused core) */ 1297 break; 1298 1299 case TCTXT_EN0_SET: 1300 xive->tctxt_regs[TCTXT_EN0 >> 3] |= val; 1301 break; 1302 case TCTXT_EN1_SET: 1303 xive->tctxt_regs[TCTXT_EN1 >> 3] |= val; 1304 break; 1305 case TCTXT_EN0_RESET: 1306 xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val; 1307 break; 1308 case TCTXT_EN1_RESET: 1309 xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; 1310 break; 1311 1312 default: 1313 xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); 1314 return; 1315 } 1316 1317 xive->pc_regs[reg] = val; 1318 } 1319 1320 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = { 1321 .read = pnv_xive2_ic_tctxt_read, 1322 .write = pnv_xive2_ic_tctxt_write, 1323 .endianness = DEVICE_BIG_ENDIAN, 1324 .valid = { 1325 .min_access_size = 8, 1326 .max_access_size = 8, 1327 }, 1328 .impl = { 1329 .min_access_size = 8, 1330 .max_access_size = 8, 1331 }, 1332 }; 1333 1334 /* 1335 * Redirect XSCOM to MMIO handlers 1336 */ 1337 static uint64_t pnv_xive2_xscom_read(void *opaque, hwaddr offset, 1338 unsigned size) 1339 { 1340 PnvXive2 *xive = PNV_XIVE2(opaque); 1341 uint64_t val = -1; 1342 uint32_t xscom_reg = offset >> 3; 1343 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1344 1345 switch (xscom_reg) { 1346 case 0x000 ... 0x0FF: 1347 val = pnv_xive2_ic_cq_read(opaque, mmio_offset, size); 1348 break; 1349 case 0x100 ... 0x1FF: 1350 val = pnv_xive2_ic_vc_read(opaque, mmio_offset, size); 1351 break; 1352 case 0x200 ... 0x2FF: 1353 val = pnv_xive2_ic_pc_read(opaque, mmio_offset, size); 1354 break; 1355 case 0x300 ... 0x3FF: 1356 val = pnv_xive2_ic_tctxt_read(opaque, mmio_offset, size); 1357 break; 1358 default: 1359 xive2_error(xive, "XSCOM: invalid read @%"HWADDR_PRIx, offset); 1360 } 1361 1362 return val; 1363 } 1364 1365 static void pnv_xive2_xscom_write(void *opaque, hwaddr offset, 1366 uint64_t val, unsigned size) 1367 { 1368 PnvXive2 *xive = PNV_XIVE2(opaque); 1369 uint32_t xscom_reg = offset >> 3; 1370 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1371 1372 switch (xscom_reg) { 1373 case 0x000 ... 0x0FF: 1374 pnv_xive2_ic_cq_write(opaque, mmio_offset, val, size); 1375 break; 1376 case 0x100 ... 0x1FF: 1377 pnv_xive2_ic_vc_write(opaque, mmio_offset, val, size); 1378 break; 1379 case 0x200 ... 0x2FF: 1380 pnv_xive2_ic_pc_write(opaque, mmio_offset, val, size); 1381 break; 1382 case 0x300 ... 0x3FF: 1383 pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size); 1384 break; 1385 default: 1386 xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset); 1387 } 1388 } 1389 1390 static const MemoryRegionOps pnv_xive2_xscom_ops = { 1391 .read = pnv_xive2_xscom_read, 1392 .write = pnv_xive2_xscom_write, 1393 .endianness = DEVICE_BIG_ENDIAN, 1394 .valid = { 1395 .min_access_size = 8, 1396 .max_access_size = 8, 1397 }, 1398 .impl = { 1399 .min_access_size = 8, 1400 .max_access_size = 8, 1401 }, 1402 }; 1403 1404 /* 1405 * Notify port page. The layout is compatible between 4K and 64K pages : 1406 * 1407 * Page 1 Notify page (writes only) 1408 * 0x000 - 0x7FF IPI interrupt (NPU) 1409 * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB) 1410 */ 1411 1412 static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr, 1413 uint64_t val) 1414 { 1415 uint8_t blk; 1416 uint32_t idx; 1417 1418 if (val & XIVE_TRIGGER_END) { 1419 xive2_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1420 addr, val); 1421 return; 1422 } 1423 1424 /* 1425 * Forward the source event notification directly to the Router. 1426 * The source interrupt number should already be correctly encoded 1427 * with the chip block id by the sending device (PHB, PSI). 1428 */ 1429 blk = XIVE_EAS_BLOCK(val); 1430 idx = XIVE_EAS_INDEX(val); 1431 1432 xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx), 1433 !!(val & XIVE_TRIGGER_PQ)); 1434 } 1435 1436 static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset, 1437 uint64_t val, unsigned size) 1438 { 1439 PnvXive2 *xive = PNV_XIVE2(opaque); 1440 1441 /* VC: IPI triggers */ 1442 switch (offset) { 1443 case 0x000 ... 0x7FF: 1444 /* TODO: check IPI notify sub-page routing */ 1445 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1446 break; 1447 1448 /* VC: HW triggers */ 1449 case 0x800 ... 0xFFF: 1450 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1451 break; 1452 1453 default: 1454 xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset); 1455 } 1456 } 1457 1458 static uint64_t pnv_xive2_ic_notify_read(void *opaque, hwaddr offset, 1459 unsigned size) 1460 { 1461 PnvXive2 *xive = PNV_XIVE2(opaque); 1462 1463 /* loads are invalid */ 1464 xive2_error(xive, "NOTIFY: invalid read @%"HWADDR_PRIx, offset); 1465 return -1; 1466 } 1467 1468 static const MemoryRegionOps pnv_xive2_ic_notify_ops = { 1469 .read = pnv_xive2_ic_notify_read, 1470 .write = pnv_xive2_ic_notify_write, 1471 .endianness = DEVICE_BIG_ENDIAN, 1472 .valid = { 1473 .min_access_size = 8, 1474 .max_access_size = 8, 1475 }, 1476 .impl = { 1477 .min_access_size = 8, 1478 .max_access_size = 8, 1479 }, 1480 }; 1481 1482 static uint64_t pnv_xive2_ic_lsi_read(void *opaque, hwaddr offset, 1483 unsigned size) 1484 { 1485 PnvXive2 *xive = PNV_XIVE2(opaque); 1486 1487 xive2_error(xive, "LSI: invalid read @%"HWADDR_PRIx, offset); 1488 return -1; 1489 } 1490 1491 static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset, 1492 uint64_t val, unsigned size) 1493 { 1494 PnvXive2 *xive = PNV_XIVE2(opaque); 1495 1496 xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset); 1497 } 1498 1499 static const MemoryRegionOps pnv_xive2_ic_lsi_ops = { 1500 .read = pnv_xive2_ic_lsi_read, 1501 .write = pnv_xive2_ic_lsi_write, 1502 .endianness = DEVICE_BIG_ENDIAN, 1503 .valid = { 1504 .min_access_size = 8, 1505 .max_access_size = 8, 1506 }, 1507 .impl = { 1508 .min_access_size = 8, 1509 .max_access_size = 8, 1510 }, 1511 }; 1512 1513 /* 1514 * Sync MMIO page (write only) 1515 */ 1516 #define PNV_XIVE2_SYNC_IPI 0x000 1517 #define PNV_XIVE2_SYNC_HW 0x080 1518 #define PNV_XIVE2_SYNC_NxC 0x100 1519 #define PNV_XIVE2_SYNC_INT 0x180 1520 #define PNV_XIVE2_SYNC_OS_ESC 0x200 1521 #define PNV_XIVE2_SYNC_POOL_ESC 0x280 1522 #define PNV_XIVE2_SYNC_HARD_ESC 0x300 1523 1524 static uint64_t pnv_xive2_ic_sync_read(void *opaque, hwaddr offset, 1525 unsigned size) 1526 { 1527 PnvXive2 *xive = PNV_XIVE2(opaque); 1528 1529 /* loads are invalid */ 1530 xive2_error(xive, "SYNC: invalid read @%"HWADDR_PRIx, offset); 1531 return -1; 1532 } 1533 1534 static void pnv_xive2_ic_sync_write(void *opaque, hwaddr offset, 1535 uint64_t val, unsigned size) 1536 { 1537 PnvXive2 *xive = PNV_XIVE2(opaque); 1538 1539 switch (offset) { 1540 case PNV_XIVE2_SYNC_IPI: 1541 case PNV_XIVE2_SYNC_HW: 1542 case PNV_XIVE2_SYNC_NxC: 1543 case PNV_XIVE2_SYNC_INT: 1544 case PNV_XIVE2_SYNC_OS_ESC: 1545 case PNV_XIVE2_SYNC_POOL_ESC: 1546 case PNV_XIVE2_SYNC_HARD_ESC: 1547 break; 1548 default: 1549 xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset); 1550 } 1551 } 1552 1553 static const MemoryRegionOps pnv_xive2_ic_sync_ops = { 1554 .read = pnv_xive2_ic_sync_read, 1555 .write = pnv_xive2_ic_sync_write, 1556 .endianness = DEVICE_BIG_ENDIAN, 1557 .valid = { 1558 .min_access_size = 8, 1559 .max_access_size = 8, 1560 }, 1561 .impl = { 1562 .min_access_size = 8, 1563 .max_access_size = 8, 1564 }, 1565 }; 1566 1567 /* 1568 * When the TM direct pages of the IC controller are accessed, the 1569 * target HW thread is deduced from the page offset. 1570 */ 1571 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) 1572 { 1573 PnvChip *chip = xive->chip; 1574 PowerPCCPU *cpu = NULL; 1575 1576 cpu = pnv_chip_find_cpu(chip, pir); 1577 if (!cpu) { 1578 xive2_error(xive, "IC: invalid PIR %x for indirect access", pir); 1579 return NULL; 1580 } 1581 1582 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 1583 xive2_error(xive, "IC: CPU %x is not enabled", pir); 1584 } 1585 1586 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1587 } 1588 1589 static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset, 1590 unsigned size) 1591 { 1592 PnvXive2 *xive = PNV_XIVE2(opaque); 1593 uint32_t pir = offset >> xive->ic_shift; 1594 XiveTCTX *tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1595 uint64_t val = -1; 1596 1597 if (tctx) { 1598 val = xive_tctx_tm_read(NULL, tctx, offset, size); 1599 } 1600 1601 return val; 1602 } 1603 1604 static void pnv_xive2_ic_tm_indirect_write(void *opaque, hwaddr offset, 1605 uint64_t val, unsigned size) 1606 { 1607 PnvXive2 *xive = PNV_XIVE2(opaque); 1608 uint32_t pir = offset >> xive->ic_shift; 1609 XiveTCTX *tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1610 1611 if (tctx) { 1612 xive_tctx_tm_write(NULL, tctx, offset, val, size); 1613 } 1614 } 1615 1616 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = { 1617 .read = pnv_xive2_ic_tm_indirect_read, 1618 .write = pnv_xive2_ic_tm_indirect_write, 1619 .endianness = DEVICE_BIG_ENDIAN, 1620 .valid = { 1621 .min_access_size = 8, 1622 .max_access_size = 8, 1623 }, 1624 .impl = { 1625 .min_access_size = 8, 1626 .max_access_size = 8, 1627 }, 1628 }; 1629 1630 /* 1631 * TIMA ops 1632 */ 1633 1634 /* 1635 * Special TIMA offsets to handle accesses in a POWER10 way. 1636 * 1637 * Only the CAM line updates done by the hypervisor should be handled 1638 * specifically. 1639 */ 1640 #define HV_PAGE_OFFSET (XIVE_TM_HV_PAGE << TM_SHIFT) 1641 #define HV_PUSH_OS_CTX_OFFSET (HV_PAGE_OFFSET | (TM_QW1_OS + TM_WORD2)) 1642 #define HV_PULL_OS_CTX_OFFSET (HV_PAGE_OFFSET | TM_SPC_PULL_OS_CTX) 1643 1644 static void pnv_xive2_tm_write(void *opaque, hwaddr offset, 1645 uint64_t value, unsigned size) 1646 { 1647 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1648 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1649 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1650 XivePresenter *xptr = XIVE_PRESENTER(xive); 1651 bool gen1_tima_os = 1652 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 1653 1654 /* TODO: should we switch the TM ops table instead ? */ 1655 if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) { 1656 xive2_tm_push_os_ctx(xptr, tctx, offset, value, size); 1657 return; 1658 } 1659 1660 /* Other TM ops are the same as XIVE1 */ 1661 xive_tctx_tm_write(xptr, tctx, offset, value, size); 1662 } 1663 1664 static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) 1665 { 1666 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1667 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1668 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1669 XivePresenter *xptr = XIVE_PRESENTER(xive); 1670 bool gen1_tima_os = 1671 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 1672 1673 /* TODO: should we switch the TM ops table instead ? */ 1674 if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) { 1675 return xive2_tm_pull_os_ctx(xptr, tctx, offset, size); 1676 } 1677 1678 /* Other TM ops are the same as XIVE1 */ 1679 return xive_tctx_tm_read(xptr, tctx, offset, size); 1680 } 1681 1682 static const MemoryRegionOps pnv_xive2_tm_ops = { 1683 .read = pnv_xive2_tm_read, 1684 .write = pnv_xive2_tm_write, 1685 .endianness = DEVICE_BIG_ENDIAN, 1686 .valid = { 1687 .min_access_size = 1, 1688 .max_access_size = 8, 1689 }, 1690 .impl = { 1691 .min_access_size = 1, 1692 .max_access_size = 8, 1693 }, 1694 }; 1695 1696 static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset, 1697 unsigned size) 1698 { 1699 PnvXive2 *xive = PNV_XIVE2(opaque); 1700 1701 xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset); 1702 return -1; 1703 } 1704 1705 static void pnv_xive2_nvc_write(void *opaque, hwaddr offset, 1706 uint64_t val, unsigned size) 1707 { 1708 PnvXive2 *xive = PNV_XIVE2(opaque); 1709 1710 xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset); 1711 } 1712 1713 static const MemoryRegionOps pnv_xive2_nvc_ops = { 1714 .read = pnv_xive2_nvc_read, 1715 .write = pnv_xive2_nvc_write, 1716 .endianness = DEVICE_BIG_ENDIAN, 1717 .valid = { 1718 .min_access_size = 8, 1719 .max_access_size = 8, 1720 }, 1721 .impl = { 1722 .min_access_size = 8, 1723 .max_access_size = 8, 1724 }, 1725 }; 1726 1727 static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset, 1728 unsigned size) 1729 { 1730 PnvXive2 *xive = PNV_XIVE2(opaque); 1731 1732 xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset); 1733 return -1; 1734 } 1735 1736 static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset, 1737 uint64_t val, unsigned size) 1738 { 1739 PnvXive2 *xive = PNV_XIVE2(opaque); 1740 1741 xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset); 1742 } 1743 1744 static const MemoryRegionOps pnv_xive2_nvpg_ops = { 1745 .read = pnv_xive2_nvpg_read, 1746 .write = pnv_xive2_nvpg_write, 1747 .endianness = DEVICE_BIG_ENDIAN, 1748 .valid = { 1749 .min_access_size = 8, 1750 .max_access_size = 8, 1751 }, 1752 .impl = { 1753 .min_access_size = 8, 1754 .max_access_size = 8, 1755 }, 1756 }; 1757 1758 /* 1759 * POWER10 default capabilities: 0x2000120076f000FC 1760 */ 1761 #define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC 1762 1763 /* 1764 * POWER10 default configuration: 0x0030000033000000 1765 * 1766 * 8bits thread id was dropped for P10 1767 */ 1768 #define PNV_XIVE2_CONFIGURATION 0x0030000033000000 1769 1770 static void pnv_xive2_reset(void *dev) 1771 { 1772 PnvXive2 *xive = PNV_XIVE2(dev); 1773 XiveSource *xsrc = &xive->ipi_source; 1774 Xive2EndSource *end_xsrc = &xive->end_source; 1775 1776 xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities; 1777 xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config; 1778 1779 /* HW hardwires the #Topology of the chip in the block field */ 1780 xive->cq_regs[CQ_XIVE_CFG >> 3] |= 1781 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id); 1782 1783 /* Set default page size to 64k */ 1784 xive->ic_shift = xive->esb_shift = xive->end_shift = 16; 1785 xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16; 1786 1787 /* Clear source MMIOs */ 1788 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 1789 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); 1790 } 1791 1792 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 1793 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); 1794 } 1795 } 1796 1797 /* 1798 * Maximum number of IRQs and ENDs supported by HW. Will be tuned by 1799 * software. 1800 */ 1801 #define PNV_XIVE2_NR_IRQS (PNV10_XIVE2_ESB_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1802 #define PNV_XIVE2_NR_ENDS (PNV10_XIVE2_END_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1803 1804 static void pnv_xive2_realize(DeviceState *dev, Error **errp) 1805 { 1806 PnvXive2 *xive = PNV_XIVE2(dev); 1807 PnvXive2Class *pxc = PNV_XIVE2_GET_CLASS(dev); 1808 XiveSource *xsrc = &xive->ipi_source; 1809 Xive2EndSource *end_xsrc = &xive->end_source; 1810 Error *local_err = NULL; 1811 int i; 1812 1813 pxc->parent_realize(dev, &local_err); 1814 if (local_err) { 1815 error_propagate(errp, local_err); 1816 return; 1817 } 1818 1819 assert(xive->chip); 1820 1821 /* 1822 * The XiveSource and Xive2EndSource objects are realized with the 1823 * maximum allowed HW configuration. The ESB MMIO regions will be 1824 * resized dynamically when the controller is configured by the FW 1825 * to limit accesses to resources not provisioned. 1826 */ 1827 object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI, 1828 &error_fatal); 1829 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS, 1830 &error_fatal); 1831 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), 1832 &error_fatal); 1833 qdev_realize(DEVICE(xsrc), NULL, &local_err); 1834 if (local_err) { 1835 error_propagate(errp, local_err); 1836 return; 1837 } 1838 1839 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS, 1840 &error_fatal); 1841 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 1842 &error_abort); 1843 qdev_realize(DEVICE(end_xsrc), NULL, &local_err); 1844 if (local_err) { 1845 error_propagate(errp, local_err); 1846 return; 1847 } 1848 1849 /* XSCOM region, used for initial configuration of the BARs */ 1850 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), 1851 &pnv_xive2_xscom_ops, xive, "xscom-xive", 1852 PNV10_XSCOM_XIVE2_SIZE << 3); 1853 1854 /* Interrupt controller MMIO regions */ 1855 xive->ic_shift = 16; 1856 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 1857 PNV10_XIVE2_IC_SIZE); 1858 1859 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 1860 memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev), 1861 pnv_xive2_ic_regions[i].ops, xive, 1862 pnv_xive2_ic_regions[i].name, 1863 pnv_xive2_ic_regions[i].pgsize << xive->ic_shift); 1864 } 1865 1866 /* 1867 * VC MMIO regions. 1868 */ 1869 xive->esb_shift = 16; 1870 xive->end_shift = 16; 1871 memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb", 1872 PNV10_XIVE2_ESB_SIZE); 1873 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end", 1874 PNV10_XIVE2_END_SIZE); 1875 1876 /* Presenter Controller MMIO region (not modeled) */ 1877 xive->nvc_shift = 16; 1878 xive->nvpg_shift = 16; 1879 memory_region_init_io(&xive->nvc_mmio, OBJECT(dev), 1880 &pnv_xive2_nvc_ops, xive, 1881 "xive-nvc", PNV10_XIVE2_NVC_SIZE); 1882 1883 memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev), 1884 &pnv_xive2_nvpg_ops, xive, 1885 "xive-nvpg", PNV10_XIVE2_NVPG_SIZE); 1886 1887 /* Thread Interrupt Management Area (Direct) */ 1888 xive->tm_shift = 16; 1889 memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops, 1890 xive, "xive-tima", PNV10_XIVE2_TM_SIZE); 1891 1892 qemu_register_reset(pnv_xive2_reset, dev); 1893 } 1894 1895 static Property pnv_xive2_properties[] = { 1896 DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0), 1897 DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0), 1898 DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0), 1899 DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0), 1900 DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0), 1901 DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0), 1902 DEFINE_PROP_UINT64("capabilities", PnvXive2, capabilities, 1903 PNV_XIVE2_CAPABILITIES), 1904 DEFINE_PROP_UINT64("config", PnvXive2, config, 1905 PNV_XIVE2_CONFIGURATION), 1906 DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *), 1907 DEFINE_PROP_END_OF_LIST(), 1908 }; 1909 1910 static void pnv_xive2_instance_init(Object *obj) 1911 { 1912 PnvXive2 *xive = PNV_XIVE2(obj); 1913 1914 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 1915 TYPE_XIVE_SOURCE); 1916 object_initialize_child(obj, "end_source", &xive->end_source, 1917 TYPE_XIVE2_END_SOURCE); 1918 } 1919 1920 static int pnv_xive2_dt_xscom(PnvXScomInterface *dev, void *fdt, 1921 int xscom_offset) 1922 { 1923 const char compat_p10[] = "ibm,power10-xive-x"; 1924 char *name; 1925 int offset; 1926 uint32_t reg[] = { 1927 cpu_to_be32(PNV10_XSCOM_XIVE2_BASE), 1928 cpu_to_be32(PNV10_XSCOM_XIVE2_SIZE) 1929 }; 1930 1931 name = g_strdup_printf("xive@%x", PNV10_XSCOM_XIVE2_BASE); 1932 offset = fdt_add_subnode(fdt, xscom_offset, name); 1933 _FDT(offset); 1934 g_free(name); 1935 1936 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 1937 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, 1938 sizeof(compat_p10))); 1939 return 0; 1940 } 1941 1942 static void pnv_xive2_class_init(ObjectClass *klass, void *data) 1943 { 1944 DeviceClass *dc = DEVICE_CLASS(klass); 1945 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 1946 Xive2RouterClass *xrc = XIVE2_ROUTER_CLASS(klass); 1947 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1948 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 1949 PnvXive2Class *pxc = PNV_XIVE2_CLASS(klass); 1950 1951 xdc->dt_xscom = pnv_xive2_dt_xscom; 1952 1953 dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)"; 1954 device_class_set_parent_realize(dc, pnv_xive2_realize, 1955 &pxc->parent_realize); 1956 device_class_set_props(dc, pnv_xive2_properties); 1957 1958 xrc->get_eas = pnv_xive2_get_eas; 1959 xrc->get_pq = pnv_xive2_get_pq; 1960 xrc->set_pq = pnv_xive2_set_pq; 1961 xrc->get_end = pnv_xive2_get_end; 1962 xrc->write_end = pnv_xive2_write_end; 1963 xrc->get_nvp = pnv_xive2_get_nvp; 1964 xrc->write_nvp = pnv_xive2_write_nvp; 1965 xrc->get_config = pnv_xive2_get_config; 1966 xrc->get_block_id = pnv_xive2_get_block_id; 1967 1968 xnc->notify = pnv_xive2_notify; 1969 1970 xpc->match_nvt = pnv_xive2_match_nvt; 1971 }; 1972 1973 static const TypeInfo pnv_xive2_info = { 1974 .name = TYPE_PNV_XIVE2, 1975 .parent = TYPE_XIVE2_ROUTER, 1976 .instance_init = pnv_xive2_instance_init, 1977 .instance_size = sizeof(PnvXive2), 1978 .class_init = pnv_xive2_class_init, 1979 .class_size = sizeof(PnvXive2Class), 1980 .interfaces = (InterfaceInfo[]) { 1981 { TYPE_PNV_XSCOM_INTERFACE }, 1982 { } 1983 } 1984 }; 1985 1986 static void pnv_xive2_register_types(void) 1987 { 1988 type_register_static(&pnv_xive2_info); 1989 } 1990 1991 type_init(pnv_xive2_register_types) 1992 1993 static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, 1994 Monitor *mon) 1995 { 1996 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 1997 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 1998 1999 if (!xive2_nvp_is_valid(nvp)) { 2000 return; 2001 } 2002 2003 monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", 2004 nvp_idx, eq_blk, eq_idx, 2005 xive_get_field32(NVP2_W2_IPB, nvp->w2)); 2006 } 2007 2008 /* 2009 * If the table is direct, we can compute the number of PQ entries 2010 * provisioned by FW. 2011 */ 2012 static uint32_t pnv_xive2_nr_esbs(PnvXive2 *xive) 2013 { 2014 uint8_t blk = pnv_xive2_block_id(xive); 2015 uint64_t vsd = xive->vsds[VST_ESB][blk]; 2016 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 2017 2018 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 2019 } 2020 2021 /* 2022 * Compute the number of entries per indirect subpage. 2023 */ 2024 static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type) 2025 { 2026 uint8_t blk = pnv_xive2_block_id(xive); 2027 uint64_t vsd = xive->vsds[type][blk]; 2028 const XiveVstInfo *info = &vst_infos[type]; 2029 uint64_t vsd_addr; 2030 uint32_t page_shift; 2031 2032 /* For direct tables, fake a valid value */ 2033 if (!(VSD_INDIRECT & vsd)) { 2034 return 1; 2035 } 2036 2037 /* Get the page size of the indirect table. */ 2038 vsd_addr = vsd & VSD_ADDRESS_MASK; 2039 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 2040 2041 if (!(vsd & VSD_ADDRESS_MASK)) { 2042 #ifdef XIVE2_DEBUG 2043 xive2_error(xive, "VST: invalid %s entry!?", info->name); 2044 #endif 2045 return 0; 2046 } 2047 2048 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 2049 2050 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 2051 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 2052 page_shift); 2053 return 0; 2054 } 2055 2056 return (1ull << page_shift) / info->size; 2057 } 2058 2059 void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon) 2060 { 2061 Xive2Router *xrtr = XIVE2_ROUTER(xive); 2062 uint8_t blk = pnv_xive2_block_id(xive); 2063 uint8_t chip_id = xive->chip->chip_id; 2064 uint32_t srcno0 = XIVE_EAS(blk, 0); 2065 uint32_t nr_esbs = pnv_xive2_nr_esbs(xive); 2066 Xive2Eas eas; 2067 Xive2End end; 2068 Xive2Nvp nvp; 2069 int i; 2070 uint64_t xive_nvp_per_subpage; 2071 2072 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, 2073 srcno0 + nr_esbs - 1); 2074 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); 2075 2076 monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, 2077 srcno0 + nr_esbs - 1); 2078 for (i = 0; i < nr_esbs; i++) { 2079 if (xive2_router_get_eas(xrtr, blk, i, &eas)) { 2080 break; 2081 } 2082 if (!xive2_eas_is_masked(&eas)) { 2083 xive2_eas_pic_print_info(&eas, i, mon); 2084 } 2085 } 2086 2087 monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); 2088 i = 0; 2089 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2090 xive2_end_eas_pic_print_info(&end, i++, mon); 2091 } 2092 2093 monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); 2094 i = 0; 2095 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2096 xive2_end_pic_print_info(&end, i++, mon); 2097 } 2098 2099 monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk, 2100 0, XIVE2_NVP_COUNT - 1); 2101 xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); 2102 for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) { 2103 while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) { 2104 xive2_nvp_pic_print_info(&nvp, i++, mon); 2105 } 2106 } 2107 } 2108