1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "sysemu/cpus.h" 15 #include "sysemu/dma.h" 16 #include "hw/ppc/fdt.h" 17 #include "hw/ppc/pnv.h" 18 #include "hw/ppc/pnv_chip.h" 19 #include "hw/ppc/pnv_core.h" 20 #include "hw/ppc/pnv_xscom.h" 21 #include "hw/ppc/xive2.h" 22 #include "hw/ppc/pnv_xive.h" 23 #include "hw/ppc/xive_regs.h" 24 #include "hw/ppc/xive2_regs.h" 25 #include "hw/ppc/ppc.h" 26 #include "hw/qdev-properties.h" 27 #include "sysemu/reset.h" 28 #include "sysemu/qtest.h" 29 30 #include <libfdt.h> 31 32 #include "pnv_xive2_regs.h" 33 34 #undef XIVE2_DEBUG 35 36 /* XIVE Sync or Flush Notification Block */ 37 typedef struct XiveSfnBlock { 38 uint8_t bytes[32]; 39 } XiveSfnBlock; 40 41 /* XIVE Thread Sync or Flush Notification Area */ 42 typedef struct XiveThreadNA { 43 XiveSfnBlock topo[16]; 44 } XiveThreadNA; 45 46 /* 47 * Virtual structures table (VST) 48 */ 49 #define SBE_PER_BYTE 4 50 51 typedef struct XiveVstInfo { 52 const char *name; 53 uint32_t size; 54 uint32_t max_blocks; 55 } XiveVstInfo; 56 57 static const XiveVstInfo vst_infos[] = { 58 59 [VST_EAS] = { "EAT", sizeof(Xive2Eas), 16 }, 60 [VST_ESB] = { "ESB", 1, 16 }, 61 [VST_END] = { "ENDT", sizeof(Xive2End), 16 }, 62 63 [VST_NVP] = { "NVPT", sizeof(Xive2Nvp), 16 }, 64 [VST_NVG] = { "NVGT", sizeof(Xive2Nvgc), 16 }, 65 [VST_NVC] = { "NVCT", sizeof(Xive2Nvgc), 16 }, 66 67 [VST_IC] = { "IC", 1, /* ? */ 16 }, /* Topology # */ 68 [VST_SYNC] = { "SYNC", sizeof(XiveThreadNA), 16 }, /* Topology # */ 69 70 /* 71 * This table contains the backing store pages for the interrupt 72 * fifos of the VC sub-engine in case of overflow. 73 * 74 * 0 - IPI, 75 * 1 - HWD, 76 * 2 - NxC, 77 * 3 - INT, 78 * 4 - OS-Queue, 79 * 5 - Pool-Queue, 80 * 6 - Hard-Queue 81 */ 82 [VST_ERQ] = { "ERQ", 1, VC_QUEUE_COUNT }, 83 }; 84 85 #define xive2_error(xive, fmt, ...) \ 86 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 87 (xive)->chip->chip_id, ## __VA_ARGS__); 88 89 /* 90 * TODO: Document block id override 91 */ 92 static uint32_t pnv_xive2_block_id(PnvXive2 *xive) 93 { 94 uint8_t blk = xive->chip->chip_id; 95 uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3]; 96 97 if (cfg_val & CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE) { 98 blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val); 99 } 100 101 return blk; 102 } 103 104 /* 105 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 106 * of the chips is good enough. 107 * 108 * TODO: Block scope support 109 */ 110 static PnvXive2 *pnv_xive2_get_remote(uint8_t blk) 111 { 112 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 113 int i; 114 115 for (i = 0; i < pnv->num_chips; i++) { 116 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 117 PnvXive2 *xive = &chip10->xive; 118 119 if (pnv_xive2_block_id(xive) == blk) { 120 return xive; 121 } 122 } 123 return NULL; 124 } 125 126 /* 127 * VST accessors for ESB, EAT, ENDT, NVP 128 * 129 * Indirect VST tables are arrays of VSDs pointing to a page (of same 130 * size). Each page is a direct VST table. 131 */ 132 133 #define XIVE_VSD_SIZE 8 134 135 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 136 static uint64_t pnv_xive2_vst_page_size_allowed(uint32_t page_shift) 137 { 138 return page_shift == 12 || page_shift == 16 || 139 page_shift == 21 || page_shift == 24; 140 } 141 142 static uint64_t pnv_xive2_vst_addr_direct(PnvXive2 *xive, uint32_t type, 143 uint64_t vsd, uint32_t idx) 144 { 145 const XiveVstInfo *info = &vst_infos[type]; 146 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 147 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 148 uint32_t idx_max; 149 150 idx_max = vst_tsize / info->size - 1; 151 if (idx > idx_max) { 152 #ifdef XIVE2_DEBUG 153 xive2_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 154 info->name, idx, idx_max); 155 #endif 156 return 0; 157 } 158 159 return vst_addr + idx * info->size; 160 } 161 162 static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type, 163 uint64_t vsd, uint32_t idx) 164 { 165 const XiveVstInfo *info = &vst_infos[type]; 166 uint64_t vsd_addr; 167 uint32_t vsd_idx; 168 uint32_t page_shift; 169 uint32_t vst_per_page; 170 171 /* Get the page size of the indirect table. */ 172 vsd_addr = vsd & VSD_ADDRESS_MASK; 173 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 174 175 if (!(vsd & VSD_ADDRESS_MASK)) { 176 #ifdef XIVE2_DEBUG 177 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 178 #endif 179 return 0; 180 } 181 182 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 183 184 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 185 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 186 page_shift); 187 return 0; 188 } 189 190 vst_per_page = (1ull << page_shift) / info->size; 191 vsd_idx = idx / vst_per_page; 192 193 /* Load the VSD we are looking for, if not already done */ 194 if (vsd_idx) { 195 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 196 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, 197 MEMTXATTRS_UNSPECIFIED); 198 199 if (!(vsd & VSD_ADDRESS_MASK)) { 200 #ifdef XIVE2_DEBUG 201 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 202 #endif 203 return 0; 204 } 205 206 /* 207 * Check that the pages have a consistent size across the 208 * indirect table 209 */ 210 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 211 xive2_error(xive, "VST: %s entry %x indirect page size differ !?", 212 info->name, idx); 213 return 0; 214 } 215 } 216 217 return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 218 } 219 220 static uint8_t pnv_xive2_nvc_table_compress_shift(PnvXive2 *xive) 221 { 222 uint8_t shift = GETFIELD(PC_NXC_PROC_CONFIG_NVC_TABLE_COMPRESS, 223 xive->pc_regs[PC_NXC_PROC_CONFIG >> 3]); 224 return shift > 8 ? 0 : shift; 225 } 226 227 static uint8_t pnv_xive2_nvg_table_compress_shift(PnvXive2 *xive) 228 { 229 uint8_t shift = GETFIELD(PC_NXC_PROC_CONFIG_NVG_TABLE_COMPRESS, 230 xive->pc_regs[PC_NXC_PROC_CONFIG >> 3]); 231 return shift > 8 ? 0 : shift; 232 } 233 234 static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk, 235 uint32_t idx) 236 { 237 const XiveVstInfo *info = &vst_infos[type]; 238 uint64_t vsd; 239 240 if (blk >= info->max_blocks) { 241 xive2_error(xive, "VST: invalid block id %d for VST %s %d !?", 242 blk, info->name, idx); 243 return 0; 244 } 245 246 vsd = xive->vsds[type][blk]; 247 248 /* Remote VST access */ 249 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 250 xive = pnv_xive2_get_remote(blk); 251 252 return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0; 253 } 254 255 if (type == VST_NVG) { 256 idx >>= pnv_xive2_nvg_table_compress_shift(xive); 257 } else if (type == VST_NVC) { 258 idx >>= pnv_xive2_nvc_table_compress_shift(xive); 259 } 260 261 if (VSD_INDIRECT & vsd) { 262 return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx); 263 } 264 265 return pnv_xive2_vst_addr_direct(xive, type, vsd, idx); 266 } 267 268 static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk, 269 uint32_t idx, void *data) 270 { 271 const XiveVstInfo *info = &vst_infos[type]; 272 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 273 MemTxResult result; 274 275 if (!addr) { 276 return -1; 277 } 278 279 result = address_space_read(&address_space_memory, addr, 280 MEMTXATTRS_UNSPECIFIED, data, 281 info->size); 282 if (result != MEMTX_OK) { 283 xive2_error(xive, "VST: read failed at @0x%" HWADDR_PRIx 284 " for VST %s %x/%x\n", addr, info->name, blk, idx); 285 return -1; 286 } 287 return 0; 288 } 289 290 #define XIVE_VST_WORD_ALL -1 291 292 static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk, 293 uint32_t idx, void *data, uint32_t word_number) 294 { 295 const XiveVstInfo *info = &vst_infos[type]; 296 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 297 MemTxResult result; 298 299 if (!addr) { 300 return -1; 301 } 302 303 if (word_number == XIVE_VST_WORD_ALL) { 304 result = address_space_write(&address_space_memory, addr, 305 MEMTXATTRS_UNSPECIFIED, data, 306 info->size); 307 } else { 308 result = address_space_write(&address_space_memory, 309 addr + word_number * 4, 310 MEMTXATTRS_UNSPECIFIED, 311 data + word_number * 4, 4); 312 } 313 314 if (result != MEMTX_OK) { 315 xive2_error(xive, "VST: write failed at @0x%" HWADDR_PRIx 316 "for VST %s %x/%x\n", addr, info->name, blk, idx); 317 return -1; 318 } 319 return 0; 320 } 321 322 static int pnv_xive2_get_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 323 uint8_t *pq) 324 { 325 PnvXive2 *xive = PNV_XIVE2(xrtr); 326 327 if (pnv_xive2_block_id(xive) != blk) { 328 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 329 return -1; 330 } 331 332 *pq = xive_source_esb_get(&xive->ipi_source, idx); 333 return 0; 334 } 335 336 static int pnv_xive2_set_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 337 uint8_t *pq) 338 { 339 PnvXive2 *xive = PNV_XIVE2(xrtr); 340 341 if (pnv_xive2_block_id(xive) != blk) { 342 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 343 return -1; 344 } 345 346 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq); 347 return 0; 348 } 349 350 static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 351 Xive2End *end) 352 { 353 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_END, blk, idx, end); 354 } 355 356 static int pnv_xive2_write_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 357 Xive2End *end, uint8_t word_number) 358 { 359 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_END, blk, idx, end, 360 word_number); 361 } 362 363 static inline int pnv_xive2_get_current_pir(PnvXive2 *xive) 364 { 365 if (!qtest_enabled()) { 366 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 367 return ppc_cpu_pir(cpu); 368 } 369 return 0; 370 } 371 372 /* 373 * After SW injects a Queue Sync or Cache Flush operation, HW will notify 374 * SW of the completion of the operation by writing a byte of all 1's (0xff) 375 * to a specific memory location. The memory location is calculated by first 376 * looking up a base address in the SYNC VSD using the Topology ID of the 377 * originating thread as the "block" number. This points to a 378 * 64k block of memory that is further divided into 128 512 byte chunks of 379 * memory, which is indexed by the thread id of the requesting thread. 380 * Finally, this 512 byte chunk of memory is divided into 16 32 byte 381 * chunks which are indexed by the topology id of the targeted IC's chip. 382 * The values below are the offsets into that 32 byte chunk of memory for 383 * each type of cache flush or queue sync operation. 384 */ 385 #define PNV_XIVE2_QUEUE_IPI 0x00 386 #define PNV_XIVE2_QUEUE_HW 0x01 387 #define PNV_XIVE2_QUEUE_NXC 0x02 388 #define PNV_XIVE2_QUEUE_INT 0x03 389 #define PNV_XIVE2_QUEUE_OS 0x04 390 #define PNV_XIVE2_QUEUE_POOL 0x05 391 #define PNV_XIVE2_QUEUE_HARD 0x06 392 #define PNV_XIVE2_CACHE_ENDC 0x08 393 #define PNV_XIVE2_CACHE_ESBC 0x09 394 #define PNV_XIVE2_CACHE_EASC 0x0a 395 #define PNV_XIVE2_QUEUE_NXC_LD_LCL_NCO 0x10 396 #define PNV_XIVE2_QUEUE_NXC_LD_LCL_CO 0x11 397 #define PNV_XIVE2_QUEUE_NXC_ST_LCL_NCI 0x12 398 #define PNV_XIVE2_QUEUE_NXC_ST_LCL_CI 0x13 399 #define PNV_XIVE2_QUEUE_NXC_ST_RMT_NCI 0x14 400 #define PNV_XIVE2_QUEUE_NXC_ST_RMT_CI 0x15 401 #define PNV_XIVE2_CACHE_NXC 0x18 402 403 static int pnv_xive2_inject_notify(PnvXive2 *xive, int type) 404 { 405 uint64_t addr; 406 int pir = pnv_xive2_get_current_pir(xive); 407 int thread_nr = PNV10_PIR2THREAD(pir); 408 int thread_topo_id = PNV10_PIR2CHIP(pir); 409 int ic_topo_id = xive->chip->chip_id; 410 uint64_t offset = ic_topo_id * sizeof(XiveSfnBlock); 411 uint8_t byte = 0xff; 412 MemTxResult result; 413 414 /* Retrieve the address of requesting thread's notification area */ 415 addr = pnv_xive2_vst_addr(xive, VST_SYNC, thread_topo_id, thread_nr); 416 417 if (!addr) { 418 xive2_error(xive, "VST: no SYNC entry %x/%x !?", 419 thread_topo_id, thread_nr); 420 return -1; 421 } 422 423 address_space_stb(&address_space_memory, addr + offset + type, byte, 424 MEMTXATTRS_UNSPECIFIED, &result); 425 assert(result == MEMTX_OK); 426 427 return 0; 428 } 429 430 static int pnv_xive2_end_update(PnvXive2 *xive, uint8_t watch_engine) 431 { 432 uint8_t blk; 433 uint32_t idx; 434 int i, spec_reg, data_reg; 435 uint64_t endc_watch[4]; 436 437 assert(watch_engine < ARRAY_SIZE(endc_watch)); 438 439 spec_reg = (VC_ENDC_WATCH0_SPEC + watch_engine * 0x40) >> 3; 440 data_reg = (VC_ENDC_WATCH0_DATA0 + watch_engine * 0x40) >> 3; 441 blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, xive->vc_regs[spec_reg]); 442 idx = GETFIELD(VC_ENDC_WATCH_INDEX, xive->vc_regs[spec_reg]); 443 444 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 445 endc_watch[i] = cpu_to_be64(xive->vc_regs[data_reg + i]); 446 } 447 448 return pnv_xive2_vst_write(xive, VST_END, blk, idx, endc_watch, 449 XIVE_VST_WORD_ALL); 450 } 451 452 static void pnv_xive2_end_cache_load(PnvXive2 *xive, uint8_t watch_engine) 453 { 454 uint8_t blk; 455 uint32_t idx; 456 uint64_t endc_watch[4] = { 0 }; 457 int i, spec_reg, data_reg; 458 459 assert(watch_engine < ARRAY_SIZE(endc_watch)); 460 461 spec_reg = (VC_ENDC_WATCH0_SPEC + watch_engine * 0x40) >> 3; 462 data_reg = (VC_ENDC_WATCH0_DATA0 + watch_engine * 0x40) >> 3; 463 blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, xive->vc_regs[spec_reg]); 464 idx = GETFIELD(VC_ENDC_WATCH_INDEX, xive->vc_regs[spec_reg]); 465 466 if (pnv_xive2_vst_read(xive, VST_END, blk, idx, endc_watch)) { 467 xive2_error(xive, "VST: no END entry %x/%x !?", blk, idx); 468 } 469 470 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 471 xive->vc_regs[data_reg + i] = be64_to_cpu(endc_watch[i]); 472 } 473 } 474 475 static int pnv_xive2_get_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 476 Xive2Nvp *nvp) 477 { 478 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp); 479 } 480 481 static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 482 Xive2Nvp *nvp, uint8_t word_number) 483 { 484 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp, 485 word_number); 486 } 487 488 static int pnv_xive2_nxc_to_table_type(uint8_t nxc_type, uint32_t *table_type) 489 { 490 switch (nxc_type) { 491 case PC_NXC_WATCH_NXC_NVP: 492 *table_type = VST_NVP; 493 break; 494 case PC_NXC_WATCH_NXC_NVG: 495 *table_type = VST_NVG; 496 break; 497 case PC_NXC_WATCH_NXC_NVC: 498 *table_type = VST_NVC; 499 break; 500 default: 501 qemu_log_mask(LOG_GUEST_ERROR, 502 "XIVE: invalid table type for nxc operation\n"); 503 return -1; 504 } 505 return 0; 506 } 507 508 static int pnv_xive2_nxc_update(PnvXive2 *xive, uint8_t watch_engine) 509 { 510 uint8_t blk, nxc_type; 511 uint32_t idx, table_type = -1; 512 int i, spec_reg, data_reg; 513 uint64_t nxc_watch[4]; 514 515 assert(watch_engine < ARRAY_SIZE(nxc_watch)); 516 517 spec_reg = (PC_NXC_WATCH0_SPEC + watch_engine * 0x40) >> 3; 518 data_reg = (PC_NXC_WATCH0_DATA0 + watch_engine * 0x40) >> 3; 519 nxc_type = GETFIELD(PC_NXC_WATCH_NXC_TYPE, xive->pc_regs[spec_reg]); 520 blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, xive->pc_regs[spec_reg]); 521 idx = GETFIELD(PC_NXC_WATCH_INDEX, xive->pc_regs[spec_reg]); 522 523 assert(!pnv_xive2_nxc_to_table_type(nxc_type, &table_type)); 524 525 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 526 nxc_watch[i] = cpu_to_be64(xive->pc_regs[data_reg + i]); 527 } 528 529 return pnv_xive2_vst_write(xive, table_type, blk, idx, nxc_watch, 530 XIVE_VST_WORD_ALL); 531 } 532 533 static void pnv_xive2_nxc_cache_load(PnvXive2 *xive, uint8_t watch_engine) 534 { 535 uint8_t blk, nxc_type; 536 uint32_t idx, table_type = -1; 537 uint64_t nxc_watch[4] = { 0 }; 538 int i, spec_reg, data_reg; 539 540 assert(watch_engine < ARRAY_SIZE(nxc_watch)); 541 542 spec_reg = (PC_NXC_WATCH0_SPEC + watch_engine * 0x40) >> 3; 543 data_reg = (PC_NXC_WATCH0_DATA0 + watch_engine * 0x40) >> 3; 544 nxc_type = GETFIELD(PC_NXC_WATCH_NXC_TYPE, xive->pc_regs[spec_reg]); 545 blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, xive->pc_regs[spec_reg]); 546 idx = GETFIELD(PC_NXC_WATCH_INDEX, xive->pc_regs[spec_reg]); 547 548 assert(!pnv_xive2_nxc_to_table_type(nxc_type, &table_type)); 549 550 if (pnv_xive2_vst_read(xive, table_type, blk, idx, nxc_watch)) { 551 xive2_error(xive, "VST: no NXC entry %x/%x in %s table!?", 552 blk, idx, vst_infos[table_type].name); 553 } 554 555 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 556 xive->pc_regs[data_reg + i] = be64_to_cpu(nxc_watch[i]); 557 } 558 } 559 560 static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 561 Xive2Eas *eas) 562 { 563 PnvXive2 *xive = PNV_XIVE2(xrtr); 564 565 if (pnv_xive2_block_id(xive) != blk) { 566 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 567 return -1; 568 } 569 570 return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas); 571 } 572 573 static uint32_t pnv_xive2_get_config(Xive2Router *xrtr) 574 { 575 PnvXive2 *xive = PNV_XIVE2(xrtr); 576 uint32_t cfg = 0; 577 578 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { 579 cfg |= XIVE2_GEN1_TIMA_OS; 580 } 581 582 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) { 583 cfg |= XIVE2_VP_SAVE_RESTORE; 584 } 585 586 if (GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, 587 xive->cq_regs[CQ_XIVE_CFG >> 3]) == CQ_XIVE_CFG_THREADID_8BITS) { 588 cfg |= XIVE2_THREADID_8BITS; 589 } 590 591 return cfg; 592 } 593 594 static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu) 595 { 596 int pir = ppc_cpu_pir(cpu); 597 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); 598 uint64_t reg = fc < 8 ? TCTXT_EN0 : TCTXT_EN1; 599 uint32_t bit = pir & 0x3f; 600 601 return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit); 602 } 603 604 static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, 605 uint8_t nvt_blk, uint32_t nvt_idx, 606 bool cam_ignore, uint8_t priority, 607 uint32_t logic_serv, XiveTCTXMatch *match) 608 { 609 PnvXive2 *xive = PNV_XIVE2(xptr); 610 PnvChip *chip = xive->chip; 611 int count = 0; 612 int i, j; 613 bool gen1_tima_os = 614 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 615 616 for (i = 0; i < chip->nr_cores; i++) { 617 PnvCore *pc = chip->cores[i]; 618 CPUCore *cc = CPU_CORE(pc); 619 620 for (j = 0; j < cc->nr_threads; j++) { 621 PowerPCCPU *cpu = pc->threads[j]; 622 XiveTCTX *tctx; 623 int ring; 624 625 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 626 continue; 627 } 628 629 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 630 631 if (gen1_tima_os) { 632 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, 633 nvt_idx, cam_ignore, 634 logic_serv); 635 } else { 636 ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk, 637 nvt_idx, cam_ignore, 638 logic_serv); 639 } 640 641 /* 642 * Save the context and follow on to catch duplicates, 643 * that we don't support yet. 644 */ 645 if (ring != -1) { 646 if (match->tctx) { 647 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 648 "thread context NVT %x/%x\n", 649 nvt_blk, nvt_idx); 650 return false; 651 } 652 653 match->ring = ring; 654 match->tctx = tctx; 655 count++; 656 } 657 } 658 } 659 660 return count; 661 } 662 663 static uint32_t pnv_xive2_presenter_get_config(XivePresenter *xptr) 664 { 665 PnvXive2 *xive = PNV_XIVE2(xptr); 666 uint32_t cfg = 0; 667 668 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { 669 cfg |= XIVE_PRESENTER_GEN1_TIMA_OS; 670 } 671 return cfg; 672 } 673 674 static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) 675 { 676 return pnv_xive2_block_id(PNV_XIVE2(xrtr)); 677 } 678 679 /* 680 * The TIMA MMIO space is shared among the chips and to identify the 681 * chip from which the access is being done, we extract the chip id 682 * from the PIR. 683 */ 684 static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu) 685 { 686 int pir = ppc_cpu_pir(cpu); 687 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; 688 PnvXive2 *xive = PNV_XIVE2(xptr); 689 690 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 691 xive2_error(xive, "IC: CPU %x is not enabled", pir); 692 } 693 return xive; 694 } 695 696 /* 697 * The internal sources of the interrupt controller have no knowledge 698 * of the XIVE2 chip on which they reside. Encode the block id in the 699 * source interrupt number before forwarding the source event 700 * notification to the Router. This is required on a multichip system. 701 */ 702 static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked) 703 { 704 PnvXive2 *xive = PNV_XIVE2(xn); 705 uint8_t blk = pnv_xive2_block_id(xive); 706 707 xive2_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked); 708 } 709 710 /* 711 * Set Translation Tables 712 * 713 * TODO add support for multiple sets 714 */ 715 static int pnv_xive2_stt_set_data(PnvXive2 *xive, uint64_t val) 716 { 717 uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]); 718 uint8_t entry = GETFIELD(CQ_TAR_ENTRY_SELECT, 719 xive->cq_regs[CQ_TAR >> 3]); 720 721 switch (tsel) { 722 case CQ_TAR_NVPG: 723 case CQ_TAR_ESB: 724 case CQ_TAR_END: 725 xive->tables[tsel][entry] = val; 726 break; 727 default: 728 xive2_error(xive, "IC: unsupported table %d", tsel); 729 return -1; 730 } 731 732 if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) { 733 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT, 734 xive->cq_regs[CQ_TAR >> 3], ++entry); 735 } 736 737 return 0; 738 } 739 /* 740 * Virtual Structure Tables (VST) configuration 741 */ 742 static void pnv_xive2_vst_set_exclusive(PnvXive2 *xive, uint8_t type, 743 uint8_t blk, uint64_t vsd) 744 { 745 Xive2EndSource *end_xsrc = &xive->end_source; 746 XiveSource *xsrc = &xive->ipi_source; 747 const XiveVstInfo *info = &vst_infos[type]; 748 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 749 uint64_t vst_tsize = 1ull << page_shift; 750 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 751 752 /* Basic checks */ 753 754 if (VSD_INDIRECT & vsd) { 755 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 756 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 757 page_shift); 758 return; 759 } 760 } 761 762 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 763 xive2_error(xive, "VST: %s table address 0x%"PRIx64 764 " is not aligned with page shift %d", 765 info->name, vst_addr, page_shift); 766 return; 767 } 768 769 /* Record the table configuration (in SRAM on HW) */ 770 xive->vsds[type][blk] = vsd; 771 772 /* Now tune the models with the configuration provided by the FW */ 773 774 switch (type) { 775 case VST_ESB: 776 /* 777 * Backing store pages for the source PQ bits. The model does 778 * not use these PQ bits backed in RAM because the XiveSource 779 * model has its own. 780 * 781 * If the table is direct, we can compute the number of PQ 782 * entries provisioned by FW (such as skiboot) and resize the 783 * ESB window accordingly. 784 */ 785 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 786 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); 787 } 788 if (!(VSD_INDIRECT & vsd)) { 789 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 790 * (1ull << xsrc->esb_shift)); 791 } 792 793 memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio); 794 break; 795 796 case VST_EAS: /* Nothing to be done */ 797 break; 798 799 case VST_END: 800 /* 801 * Backing store pages for the END. 802 */ 803 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 804 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); 805 } 806 if (!(VSD_INDIRECT & vsd)) { 807 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 808 * (1ull << end_xsrc->esb_shift)); 809 } 810 memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio); 811 break; 812 813 case VST_NVP: /* Not modeled */ 814 case VST_NVG: /* Not modeled */ 815 case VST_NVC: /* Not modeled */ 816 case VST_IC: /* Not modeled */ 817 case VST_SYNC: /* Not modeled */ 818 case VST_ERQ: /* Not modeled */ 819 break; 820 821 default: 822 g_assert_not_reached(); 823 } 824 } 825 826 /* 827 * Both PC and VC sub-engines are configured as each use the Virtual 828 * Structure Tables 829 */ 830 static void pnv_xive2_vst_set_data(PnvXive2 *xive, uint64_t vsd, 831 uint8_t type, uint8_t blk) 832 { 833 uint8_t mode = GETFIELD(VSD_MODE, vsd); 834 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 835 836 if (type > VST_ERQ) { 837 xive2_error(xive, "VST: invalid table type %d", type); 838 return; 839 } 840 841 if (blk >= vst_infos[type].max_blocks) { 842 xive2_error(xive, "VST: invalid block id %d for" 843 " %s table", blk, vst_infos[type].name); 844 return; 845 } 846 847 if (!vst_addr) { 848 xive2_error(xive, "VST: invalid %s table address", 849 vst_infos[type].name); 850 return; 851 } 852 853 switch (mode) { 854 case VSD_MODE_FORWARD: 855 xive->vsds[type][blk] = vsd; 856 break; 857 858 case VSD_MODE_EXCLUSIVE: 859 pnv_xive2_vst_set_exclusive(xive, type, blk, vsd); 860 break; 861 862 default: 863 xive2_error(xive, "VST: unsupported table mode %d", mode); 864 return; 865 } 866 } 867 868 static void pnv_xive2_vc_vst_set_data(PnvXive2 *xive, uint64_t vsd) 869 { 870 uint8_t type = GETFIELD(VC_VSD_TABLE_SELECT, 871 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 872 uint8_t blk = GETFIELD(VC_VSD_TABLE_ADDRESS, 873 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 874 875 pnv_xive2_vst_set_data(xive, vsd, type, blk); 876 } 877 878 /* 879 * MMIO handlers 880 */ 881 882 883 /* 884 * IC BAR layout 885 * 886 * Page 0: Internal CQ register accesses (reads & writes) 887 * Page 1: Internal PC register accesses (reads & writes) 888 * Page 2: Internal VC register accesses (reads & writes) 889 * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes) 890 * Page 4: Notify Port page (writes only, w/data), 891 * Page 5: Reserved 892 * Page 6: Sync Poll page (writes only, dataless) 893 * Page 7: Sync Inject page (writes only, dataless) 894 * Page 8: LSI Trigger page (writes only, dataless) 895 * Page 9: LSI SB Management page (reads & writes dataless) 896 * Pages 10-255: Reserved 897 * Pages 256-383: Direct mapped Thread Context Area (reads & writes) 898 * covering the 128 threads in P10. 899 * Pages 384-511: Reserved 900 */ 901 typedef struct PnvXive2Region { 902 const char *name; 903 uint32_t pgoff; 904 uint32_t pgsize; 905 const MemoryRegionOps *ops; 906 } PnvXive2Region; 907 908 static const MemoryRegionOps pnv_xive2_ic_cq_ops; 909 static const MemoryRegionOps pnv_xive2_ic_pc_ops; 910 static const MemoryRegionOps pnv_xive2_ic_vc_ops; 911 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops; 912 static const MemoryRegionOps pnv_xive2_ic_notify_ops; 913 static const MemoryRegionOps pnv_xive2_ic_sync_ops; 914 static const MemoryRegionOps pnv_xive2_ic_lsi_ops; 915 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops; 916 917 /* 512 pages. 4K: 2M range, 64K: 32M range */ 918 static const PnvXive2Region pnv_xive2_ic_regions[] = { 919 { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops }, 920 { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops }, 921 { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops }, 922 { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops }, 923 { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops }, 924 /* page 5 reserved */ 925 { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops }, 926 { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops }, 927 /* pages 10-255 reserved */ 928 { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops }, 929 /* pages 384-511 reserved */ 930 }; 931 932 /* 933 * CQ operations 934 */ 935 936 static uint64_t pnv_xive2_ic_cq_read(void *opaque, hwaddr offset, 937 unsigned size) 938 { 939 PnvXive2 *xive = PNV_XIVE2(opaque); 940 uint32_t reg = offset >> 3; 941 uint64_t val = 0; 942 943 switch (offset) { 944 case CQ_XIVE_CAP: /* Set at reset */ 945 case CQ_XIVE_CFG: 946 val = xive->cq_regs[reg]; 947 break; 948 case CQ_MSGSND: /* TODO check the #cores of the machine */ 949 val = 0xffffffff00000000; 950 break; 951 case CQ_CFG_PB_GEN: 952 val = CQ_CFG_PB_GEN_PB_INIT; /* TODO: fix CQ_CFG_PB_GEN default value */ 953 break; 954 default: 955 xive2_error(xive, "CQ: invalid read @%"HWADDR_PRIx, offset); 956 } 957 958 return val; 959 } 960 961 static uint64_t pnv_xive2_bar_size(uint64_t val) 962 { 963 return 1ull << (GETFIELD(CQ_BAR_RANGE, val) + 24); 964 } 965 966 static void pnv_xive2_ic_cq_write(void *opaque, hwaddr offset, 967 uint64_t val, unsigned size) 968 { 969 PnvXive2 *xive = PNV_XIVE2(opaque); 970 MemoryRegion *sysmem = get_system_memory(); 971 uint32_t reg = offset >> 3; 972 int i; 973 974 switch (offset) { 975 case CQ_XIVE_CFG: 976 case CQ_RST_CTL: /* TODO: reset all BARs */ 977 break; 978 979 case CQ_IC_BAR: 980 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 981 if (!(val & CQ_IC_BAR_VALID)) { 982 xive->ic_base = 0; 983 if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) { 984 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 985 memory_region_del_subregion(&xive->ic_mmio, 986 &xive->ic_mmios[i]); 987 } 988 memory_region_del_subregion(sysmem, &xive->ic_mmio); 989 } 990 } else { 991 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 992 if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) { 993 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 994 memory_region_add_subregion(&xive->ic_mmio, 995 pnv_xive2_ic_regions[i].pgoff << xive->ic_shift, 996 &xive->ic_mmios[i]); 997 } 998 memory_region_add_subregion(sysmem, xive->ic_base, 999 &xive->ic_mmio); 1000 } 1001 } 1002 break; 1003 1004 case CQ_TM_BAR: 1005 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 1006 if (!(val & CQ_TM_BAR_VALID)) { 1007 xive->tm_base = 0; 1008 if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) { 1009 memory_region_del_subregion(sysmem, &xive->tm_mmio); 1010 } 1011 } else { 1012 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 1013 if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) { 1014 memory_region_add_subregion(sysmem, xive->tm_base, 1015 &xive->tm_mmio); 1016 } 1017 } 1018 break; 1019 1020 case CQ_ESB_BAR: 1021 xive->esb_shift = val & CQ_BAR_64K ? 16 : 12; 1022 if (!(val & CQ_BAR_VALID)) { 1023 xive->esb_base = 0; 1024 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 1025 memory_region_del_subregion(sysmem, &xive->esb_mmio); 1026 } 1027 } else { 1028 xive->esb_base = val & CQ_BAR_ADDR; 1029 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 1030 memory_region_set_size(&xive->esb_mmio, 1031 pnv_xive2_bar_size(val)); 1032 memory_region_add_subregion(sysmem, xive->esb_base, 1033 &xive->esb_mmio); 1034 } 1035 } 1036 break; 1037 1038 case CQ_END_BAR: 1039 xive->end_shift = val & CQ_BAR_64K ? 16 : 12; 1040 if (!(val & CQ_BAR_VALID)) { 1041 xive->end_base = 0; 1042 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 1043 memory_region_del_subregion(sysmem, &xive->end_mmio); 1044 } 1045 } else { 1046 xive->end_base = val & CQ_BAR_ADDR; 1047 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 1048 memory_region_set_size(&xive->end_mmio, 1049 pnv_xive2_bar_size(val)); 1050 memory_region_add_subregion(sysmem, xive->end_base, 1051 &xive->end_mmio); 1052 } 1053 } 1054 break; 1055 1056 case CQ_NVC_BAR: 1057 xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12; 1058 if (!(val & CQ_BAR_VALID)) { 1059 xive->nvc_base = 0; 1060 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 1061 memory_region_del_subregion(sysmem, &xive->nvc_mmio); 1062 } 1063 } else { 1064 xive->nvc_base = val & CQ_BAR_ADDR; 1065 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 1066 memory_region_set_size(&xive->nvc_mmio, 1067 pnv_xive2_bar_size(val)); 1068 memory_region_add_subregion(sysmem, xive->nvc_base, 1069 &xive->nvc_mmio); 1070 } 1071 } 1072 break; 1073 1074 case CQ_NVPG_BAR: 1075 xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12; 1076 if (!(val & CQ_BAR_VALID)) { 1077 xive->nvpg_base = 0; 1078 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 1079 memory_region_del_subregion(sysmem, &xive->nvpg_mmio); 1080 } 1081 } else { 1082 xive->nvpg_base = val & CQ_BAR_ADDR; 1083 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 1084 memory_region_set_size(&xive->nvpg_mmio, 1085 pnv_xive2_bar_size(val)); 1086 memory_region_add_subregion(sysmem, xive->nvpg_base, 1087 &xive->nvpg_mmio); 1088 } 1089 } 1090 break; 1091 1092 case CQ_TAR: /* Set Translation Table Address */ 1093 break; 1094 case CQ_TDR: /* Set Translation Table Data */ 1095 pnv_xive2_stt_set_data(xive, val); 1096 break; 1097 case CQ_FIRMASK_OR: /* FIR error reporting */ 1098 break; 1099 default: 1100 xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset); 1101 return; 1102 } 1103 1104 xive->cq_regs[reg] = val; 1105 } 1106 1107 static const MemoryRegionOps pnv_xive2_ic_cq_ops = { 1108 .read = pnv_xive2_ic_cq_read, 1109 .write = pnv_xive2_ic_cq_write, 1110 .endianness = DEVICE_BIG_ENDIAN, 1111 .valid = { 1112 .min_access_size = 8, 1113 .max_access_size = 8, 1114 }, 1115 .impl = { 1116 .min_access_size = 8, 1117 .max_access_size = 8, 1118 }, 1119 }; 1120 1121 static uint8_t pnv_xive2_cache_watch_assign(uint64_t engine_mask, 1122 uint64_t *state) 1123 { 1124 uint8_t val = 0xFF; 1125 int i; 1126 1127 for (i = 3; i >= 0; i--) { 1128 if (BIT(i) & engine_mask) { 1129 if (!(BIT(i) & *state)) { 1130 *state |= BIT(i); 1131 val = 3 - i; 1132 break; 1133 } 1134 } 1135 } 1136 return val; 1137 } 1138 1139 static void pnv_xive2_cache_watch_release(uint64_t *state, uint8_t watch_engine) 1140 { 1141 uint8_t engine_bit = 3 - watch_engine; 1142 1143 if (*state & BIT(engine_bit)) { 1144 *state &= ~BIT(engine_bit); 1145 } 1146 } 1147 1148 static uint8_t pnv_xive2_endc_cache_watch_assign(PnvXive2 *xive) 1149 { 1150 uint64_t engine_mask = GETFIELD(VC_ENDC_CFG_CACHE_WATCH_ASSIGN, 1151 xive->vc_regs[VC_ENDC_CFG >> 3]); 1152 uint64_t state = xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3]; 1153 uint8_t val; 1154 1155 /* 1156 * We keep track of which engines are currently busy in the 1157 * VC_ENDC_WATCH_ASSIGN register directly. When the firmware reads 1158 * the register, we don't return its value but the ID of an engine 1159 * it can use. 1160 * There are 4 engines. 0xFF means no engine is available. 1161 */ 1162 val = pnv_xive2_cache_watch_assign(engine_mask, &state); 1163 if (val != 0xFF) { 1164 xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3] = state; 1165 } 1166 return val; 1167 } 1168 1169 static void pnv_xive2_endc_cache_watch_release(PnvXive2 *xive, 1170 uint8_t watch_engine) 1171 { 1172 uint64_t state = xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3]; 1173 1174 pnv_xive2_cache_watch_release(&state, watch_engine); 1175 xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3] = state; 1176 } 1177 1178 static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, 1179 unsigned size) 1180 { 1181 PnvXive2 *xive = PNV_XIVE2(opaque); 1182 uint64_t val = 0; 1183 uint32_t reg = offset >> 3; 1184 uint8_t watch_engine; 1185 1186 switch (offset) { 1187 /* 1188 * VSD table settings. 1189 */ 1190 case VC_VSD_TABLE_ADDR: 1191 case VC_VSD_TABLE_DATA: 1192 val = xive->vc_regs[reg]; 1193 break; 1194 1195 /* 1196 * ESB cache updates (not modeled) 1197 */ 1198 case VC_ESBC_FLUSH_CTRL: 1199 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID; 1200 val = xive->vc_regs[reg]; 1201 break; 1202 1203 case VC_ESBC_CFG: 1204 val = xive->vc_regs[reg]; 1205 break; 1206 1207 /* 1208 * EAS cache updates (not modeled) 1209 */ 1210 case VC_EASC_FLUSH_CTRL: 1211 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID; 1212 val = xive->vc_regs[reg]; 1213 break; 1214 1215 case VC_ENDC_WATCH_ASSIGN: 1216 val = pnv_xive2_endc_cache_watch_assign(xive); 1217 break; 1218 1219 case VC_ENDC_CFG: 1220 val = xive->vc_regs[reg]; 1221 break; 1222 1223 /* 1224 * END cache updates 1225 */ 1226 case VC_ENDC_WATCH0_SPEC: 1227 case VC_ENDC_WATCH1_SPEC: 1228 case VC_ENDC_WATCH2_SPEC: 1229 case VC_ENDC_WATCH3_SPEC: 1230 watch_engine = (offset - VC_ENDC_WATCH0_SPEC) >> 6; 1231 xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT); 1232 pnv_xive2_endc_cache_watch_release(xive, watch_engine); 1233 val = xive->vc_regs[reg]; 1234 break; 1235 1236 case VC_ENDC_WATCH0_DATA0: 1237 case VC_ENDC_WATCH1_DATA0: 1238 case VC_ENDC_WATCH2_DATA0: 1239 case VC_ENDC_WATCH3_DATA0: 1240 /* 1241 * Load DATA registers from cache with data requested by the 1242 * SPEC register 1243 */ 1244 watch_engine = (offset - VC_ENDC_WATCH0_DATA0) >> 6; 1245 pnv_xive2_end_cache_load(xive, watch_engine); 1246 val = xive->vc_regs[reg]; 1247 break; 1248 1249 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1250 case VC_ENDC_WATCH1_DATA1 ... VC_ENDC_WATCH1_DATA3: 1251 case VC_ENDC_WATCH2_DATA1 ... VC_ENDC_WATCH2_DATA3: 1252 case VC_ENDC_WATCH3_DATA1 ... VC_ENDC_WATCH3_DATA3: 1253 val = xive->vc_regs[reg]; 1254 break; 1255 1256 case VC_ENDC_FLUSH_CTRL: 1257 xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID; 1258 val = xive->vc_regs[reg]; 1259 break; 1260 1261 /* 1262 * Indirect invalidation 1263 */ 1264 case VC_AT_MACRO_KILL_MASK: 1265 val = xive->vc_regs[reg]; 1266 break; 1267 1268 case VC_AT_MACRO_KILL: 1269 xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID; 1270 val = xive->vc_regs[reg]; 1271 break; 1272 1273 /* 1274 * Interrupt fifo overflow in memory backing store (Not modeled) 1275 */ 1276 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1277 val = xive->vc_regs[reg]; 1278 break; 1279 1280 /* 1281 * Synchronisation 1282 */ 1283 case VC_ENDC_SYNC_DONE: 1284 val = VC_ENDC_SYNC_POLL_DONE; 1285 break; 1286 default: 1287 xive2_error(xive, "VC: invalid read @%"HWADDR_PRIx, offset); 1288 } 1289 1290 return val; 1291 } 1292 1293 static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, 1294 uint64_t val, unsigned size) 1295 { 1296 PnvXive2 *xive = PNV_XIVE2(opaque); 1297 uint32_t reg = offset >> 3; 1298 uint8_t watch_engine; 1299 1300 switch (offset) { 1301 /* 1302 * VSD table settings. 1303 */ 1304 case VC_VSD_TABLE_ADDR: 1305 break; 1306 case VC_VSD_TABLE_DATA: 1307 pnv_xive2_vc_vst_set_data(xive, val); 1308 break; 1309 1310 /* 1311 * ESB cache updates (not modeled) 1312 */ 1313 /* case VC_ESBC_FLUSH_CTRL: */ 1314 case VC_ESBC_FLUSH_POLL: 1315 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; 1316 /* ESB update */ 1317 break; 1318 1319 case VC_ESBC_FLUSH_INJECT: 1320 pnv_xive2_inject_notify(xive, PNV_XIVE2_CACHE_ESBC); 1321 break; 1322 1323 case VC_ESBC_CFG: 1324 break; 1325 1326 /* 1327 * EAS cache updates (not modeled) 1328 */ 1329 /* case VC_EASC_FLUSH_CTRL: */ 1330 case VC_EASC_FLUSH_POLL: 1331 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; 1332 /* EAS update */ 1333 break; 1334 1335 case VC_EASC_FLUSH_INJECT: 1336 pnv_xive2_inject_notify(xive, PNV_XIVE2_CACHE_EASC); 1337 break; 1338 1339 case VC_ENDC_CFG: 1340 break; 1341 1342 /* 1343 * END cache updates 1344 */ 1345 case VC_ENDC_WATCH0_SPEC: 1346 case VC_ENDC_WATCH1_SPEC: 1347 case VC_ENDC_WATCH2_SPEC: 1348 case VC_ENDC_WATCH3_SPEC: 1349 val &= ~VC_ENDC_WATCH_CONFLICT; /* HW will set this bit */ 1350 break; 1351 1352 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1353 case VC_ENDC_WATCH1_DATA1 ... VC_ENDC_WATCH1_DATA3: 1354 case VC_ENDC_WATCH2_DATA1 ... VC_ENDC_WATCH2_DATA3: 1355 case VC_ENDC_WATCH3_DATA1 ... VC_ENDC_WATCH3_DATA3: 1356 break; 1357 case VC_ENDC_WATCH0_DATA0: 1358 case VC_ENDC_WATCH1_DATA0: 1359 case VC_ENDC_WATCH2_DATA0: 1360 case VC_ENDC_WATCH3_DATA0: 1361 /* writing to DATA0 triggers the cache write */ 1362 watch_engine = (offset - VC_ENDC_WATCH0_DATA0) >> 6; 1363 xive->vc_regs[reg] = val; 1364 pnv_xive2_end_update(xive, watch_engine); 1365 break; 1366 1367 1368 /* case VC_ENDC_FLUSH_CTRL: */ 1369 case VC_ENDC_FLUSH_POLL: 1370 xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; 1371 break; 1372 1373 case VC_ENDC_FLUSH_INJECT: 1374 pnv_xive2_inject_notify(xive, PNV_XIVE2_CACHE_ENDC); 1375 break; 1376 1377 /* 1378 * Indirect invalidation 1379 */ 1380 case VC_AT_MACRO_KILL: 1381 case VC_AT_MACRO_KILL_MASK: 1382 break; 1383 1384 /* 1385 * Interrupt fifo overflow in memory backing store (Not modeled) 1386 */ 1387 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1388 break; 1389 1390 /* 1391 * Synchronisation 1392 */ 1393 case VC_ENDC_SYNC_DONE: 1394 break; 1395 1396 default: 1397 xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset); 1398 return; 1399 } 1400 1401 xive->vc_regs[reg] = val; 1402 } 1403 1404 static const MemoryRegionOps pnv_xive2_ic_vc_ops = { 1405 .read = pnv_xive2_ic_vc_read, 1406 .write = pnv_xive2_ic_vc_write, 1407 .endianness = DEVICE_BIG_ENDIAN, 1408 .valid = { 1409 .min_access_size = 8, 1410 .max_access_size = 8, 1411 }, 1412 .impl = { 1413 .min_access_size = 8, 1414 .max_access_size = 8, 1415 }, 1416 }; 1417 1418 static uint8_t pnv_xive2_nxc_cache_watch_assign(PnvXive2 *xive) 1419 { 1420 uint64_t engine_mask = GETFIELD(PC_NXC_PROC_CONFIG_WATCH_ASSIGN, 1421 xive->pc_regs[PC_NXC_PROC_CONFIG >> 3]); 1422 uint64_t state = xive->pc_regs[PC_NXC_WATCH_ASSIGN >> 3]; 1423 uint8_t val; 1424 1425 /* 1426 * We keep track of which engines are currently busy in the 1427 * PC_NXC_WATCH_ASSIGN register directly. When the firmware reads 1428 * the register, we don't return its value but the ID of an engine 1429 * it can use. 1430 * There are 4 engines. 0xFF means no engine is available. 1431 */ 1432 val = pnv_xive2_cache_watch_assign(engine_mask, &state); 1433 if (val != 0xFF) { 1434 xive->pc_regs[PC_NXC_WATCH_ASSIGN >> 3] = state; 1435 } 1436 return val; 1437 } 1438 1439 static void pnv_xive2_nxc_cache_watch_release(PnvXive2 *xive, 1440 uint8_t watch_engine) 1441 { 1442 uint64_t state = xive->pc_regs[PC_NXC_WATCH_ASSIGN >> 3]; 1443 1444 pnv_xive2_cache_watch_release(&state, watch_engine); 1445 xive->pc_regs[PC_NXC_WATCH_ASSIGN >> 3] = state; 1446 } 1447 1448 static uint64_t pnv_xive2_ic_pc_read(void *opaque, hwaddr offset, 1449 unsigned size) 1450 { 1451 PnvXive2 *xive = PNV_XIVE2(opaque); 1452 uint64_t val = -1; 1453 uint32_t reg = offset >> 3; 1454 uint8_t watch_engine; 1455 1456 switch (offset) { 1457 /* 1458 * VSD table settings. 1459 */ 1460 case PC_VSD_TABLE_ADDR: 1461 case PC_VSD_TABLE_DATA: 1462 val = xive->pc_regs[reg]; 1463 break; 1464 1465 case PC_NXC_WATCH_ASSIGN: 1466 val = pnv_xive2_nxc_cache_watch_assign(xive); 1467 break; 1468 1469 case PC_NXC_PROC_CONFIG: 1470 val = xive->pc_regs[reg]; 1471 break; 1472 1473 /* 1474 * cache updates 1475 */ 1476 case PC_NXC_WATCH0_SPEC: 1477 case PC_NXC_WATCH1_SPEC: 1478 case PC_NXC_WATCH2_SPEC: 1479 case PC_NXC_WATCH3_SPEC: 1480 watch_engine = (offset - PC_NXC_WATCH0_SPEC) >> 6; 1481 xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT); 1482 pnv_xive2_nxc_cache_watch_release(xive, watch_engine); 1483 val = xive->pc_regs[reg]; 1484 break; 1485 1486 case PC_NXC_WATCH0_DATA0: 1487 case PC_NXC_WATCH1_DATA0: 1488 case PC_NXC_WATCH2_DATA0: 1489 case PC_NXC_WATCH3_DATA0: 1490 /* 1491 * Load DATA registers from cache with data requested by the 1492 * SPEC register 1493 */ 1494 watch_engine = (offset - PC_NXC_WATCH0_DATA0) >> 6; 1495 pnv_xive2_nxc_cache_load(xive, watch_engine); 1496 val = xive->pc_regs[reg]; 1497 break; 1498 1499 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1500 case PC_NXC_WATCH1_DATA1 ... PC_NXC_WATCH1_DATA3: 1501 case PC_NXC_WATCH2_DATA1 ... PC_NXC_WATCH2_DATA3: 1502 case PC_NXC_WATCH3_DATA1 ... PC_NXC_WATCH3_DATA3: 1503 val = xive->pc_regs[reg]; 1504 break; 1505 1506 case PC_NXC_FLUSH_CTRL: 1507 xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID; 1508 val = xive->pc_regs[reg]; 1509 break; 1510 1511 /* 1512 * Indirect invalidation 1513 */ 1514 case PC_AT_KILL: 1515 xive->pc_regs[reg] &= ~PC_AT_KILL_VALID; 1516 val = xive->pc_regs[reg]; 1517 break; 1518 1519 default: 1520 xive2_error(xive, "PC: invalid read @%"HWADDR_PRIx, offset); 1521 } 1522 1523 return val; 1524 } 1525 1526 static void pnv_xive2_pc_vst_set_data(PnvXive2 *xive, uint64_t vsd) 1527 { 1528 uint8_t type = GETFIELD(PC_VSD_TABLE_SELECT, 1529 xive->pc_regs[PC_VSD_TABLE_ADDR >> 3]); 1530 uint8_t blk = GETFIELD(PC_VSD_TABLE_ADDRESS, 1531 xive->pc_regs[PC_VSD_TABLE_ADDR >> 3]); 1532 1533 pnv_xive2_vst_set_data(xive, vsd, type, blk); 1534 } 1535 1536 static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset, 1537 uint64_t val, unsigned size) 1538 { 1539 PnvXive2 *xive = PNV_XIVE2(opaque); 1540 uint32_t reg = offset >> 3; 1541 uint8_t watch_engine; 1542 1543 switch (offset) { 1544 1545 /* 1546 * VSD table settings. 1547 * The Xive2Router model combines both VC and PC sub-engines. We 1548 * allow to configure the tables through both, for the rare cases 1549 * where a table only really needs to be configured for one of 1550 * them (e.g. the NVG table for the presenter). It assumes that 1551 * firmware passes the same address to the VC and PC when tables 1552 * are defined for both, which seems acceptable. 1553 */ 1554 case PC_VSD_TABLE_ADDR: 1555 break; 1556 case PC_VSD_TABLE_DATA: 1557 pnv_xive2_pc_vst_set_data(xive, val); 1558 break; 1559 1560 case PC_NXC_PROC_CONFIG: 1561 break; 1562 1563 /* 1564 * cache updates 1565 */ 1566 case PC_NXC_WATCH0_SPEC: 1567 case PC_NXC_WATCH1_SPEC: 1568 case PC_NXC_WATCH2_SPEC: 1569 case PC_NXC_WATCH3_SPEC: 1570 val &= ~PC_NXC_WATCH_CONFLICT; /* HW will set this bit */ 1571 break; 1572 1573 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1574 case PC_NXC_WATCH1_DATA1 ... PC_NXC_WATCH1_DATA3: 1575 case PC_NXC_WATCH2_DATA1 ... PC_NXC_WATCH2_DATA3: 1576 case PC_NXC_WATCH3_DATA1 ... PC_NXC_WATCH3_DATA3: 1577 break; 1578 case PC_NXC_WATCH0_DATA0: 1579 case PC_NXC_WATCH1_DATA0: 1580 case PC_NXC_WATCH2_DATA0: 1581 case PC_NXC_WATCH3_DATA0: 1582 /* writing to DATA0 triggers the cache write */ 1583 watch_engine = (offset - PC_NXC_WATCH0_DATA0) >> 6; 1584 xive->pc_regs[reg] = val; 1585 pnv_xive2_nxc_update(xive, watch_engine); 1586 break; 1587 1588 /* case PC_NXC_FLUSH_CTRL: */ 1589 case PC_NXC_FLUSH_POLL: 1590 xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; 1591 break; 1592 1593 case PC_NXC_FLUSH_INJECT: 1594 pnv_xive2_inject_notify(xive, PNV_XIVE2_CACHE_NXC); 1595 break; 1596 1597 /* 1598 * Indirect invalidation 1599 */ 1600 case PC_AT_KILL: 1601 case PC_AT_KILL_MASK: 1602 break; 1603 1604 default: 1605 xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset); 1606 return; 1607 } 1608 1609 xive->pc_regs[reg] = val; 1610 } 1611 1612 static const MemoryRegionOps pnv_xive2_ic_pc_ops = { 1613 .read = pnv_xive2_ic_pc_read, 1614 .write = pnv_xive2_ic_pc_write, 1615 .endianness = DEVICE_BIG_ENDIAN, 1616 .valid = { 1617 .min_access_size = 8, 1618 .max_access_size = 8, 1619 }, 1620 .impl = { 1621 .min_access_size = 8, 1622 .max_access_size = 8, 1623 }, 1624 }; 1625 1626 1627 static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset, 1628 unsigned size) 1629 { 1630 PnvXive2 *xive = PNV_XIVE2(opaque); 1631 uint64_t val = -1; 1632 uint32_t reg = offset >> 3; 1633 1634 switch (offset) { 1635 /* 1636 * XIVE2 hardware thread enablement 1637 */ 1638 case TCTXT_EN0: 1639 case TCTXT_EN1: 1640 val = xive->tctxt_regs[reg]; 1641 break; 1642 1643 case TCTXT_EN0_SET: 1644 case TCTXT_EN0_RESET: 1645 val = xive->tctxt_regs[TCTXT_EN0 >> 3]; 1646 break; 1647 case TCTXT_EN1_SET: 1648 case TCTXT_EN1_RESET: 1649 val = xive->tctxt_regs[TCTXT_EN1 >> 3]; 1650 break; 1651 case TCTXT_CFG: 1652 val = xive->tctxt_regs[reg]; 1653 break; 1654 default: 1655 xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); 1656 } 1657 1658 return val; 1659 } 1660 1661 static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, 1662 uint64_t val, unsigned size) 1663 { 1664 PnvXive2 *xive = PNV_XIVE2(opaque); 1665 uint32_t reg = offset >> 3; 1666 1667 switch (offset) { 1668 /* 1669 * XIVE2 hardware thread enablement 1670 */ 1671 case TCTXT_EN0: /* Physical Thread Enable */ 1672 case TCTXT_EN1: /* Physical Thread Enable (fused core) */ 1673 xive->tctxt_regs[reg] = val; 1674 break; 1675 1676 case TCTXT_EN0_SET: 1677 xive->tctxt_regs[TCTXT_EN0 >> 3] |= val; 1678 break; 1679 case TCTXT_EN1_SET: 1680 xive->tctxt_regs[TCTXT_EN1 >> 3] |= val; 1681 break; 1682 case TCTXT_EN0_RESET: 1683 xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val; 1684 break; 1685 case TCTXT_EN1_RESET: 1686 xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; 1687 break; 1688 case TCTXT_CFG: 1689 xive->tctxt_regs[reg] = val; 1690 break; 1691 default: 1692 xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); 1693 return; 1694 } 1695 } 1696 1697 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = { 1698 .read = pnv_xive2_ic_tctxt_read, 1699 .write = pnv_xive2_ic_tctxt_write, 1700 .endianness = DEVICE_BIG_ENDIAN, 1701 .valid = { 1702 .min_access_size = 8, 1703 .max_access_size = 8, 1704 }, 1705 .impl = { 1706 .min_access_size = 8, 1707 .max_access_size = 8, 1708 }, 1709 }; 1710 1711 /* 1712 * Redirect XSCOM to MMIO handlers 1713 */ 1714 static uint64_t pnv_xive2_xscom_read(void *opaque, hwaddr offset, 1715 unsigned size) 1716 { 1717 PnvXive2 *xive = PNV_XIVE2(opaque); 1718 uint64_t val = -1; 1719 uint32_t xscom_reg = offset >> 3; 1720 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1721 1722 switch (xscom_reg) { 1723 case 0x000 ... 0x0FF: 1724 val = pnv_xive2_ic_cq_read(opaque, mmio_offset, size); 1725 break; 1726 case 0x100 ... 0x1FF: 1727 val = pnv_xive2_ic_vc_read(opaque, mmio_offset, size); 1728 break; 1729 case 0x200 ... 0x2FF: 1730 val = pnv_xive2_ic_pc_read(opaque, mmio_offset, size); 1731 break; 1732 case 0x300 ... 0x3FF: 1733 val = pnv_xive2_ic_tctxt_read(opaque, mmio_offset, size); 1734 break; 1735 default: 1736 xive2_error(xive, "XSCOM: invalid read @%"HWADDR_PRIx, offset); 1737 } 1738 1739 return val; 1740 } 1741 1742 static void pnv_xive2_xscom_write(void *opaque, hwaddr offset, 1743 uint64_t val, unsigned size) 1744 { 1745 PnvXive2 *xive = PNV_XIVE2(opaque); 1746 uint32_t xscom_reg = offset >> 3; 1747 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1748 1749 switch (xscom_reg) { 1750 case 0x000 ... 0x0FF: 1751 pnv_xive2_ic_cq_write(opaque, mmio_offset, val, size); 1752 break; 1753 case 0x100 ... 0x1FF: 1754 pnv_xive2_ic_vc_write(opaque, mmio_offset, val, size); 1755 break; 1756 case 0x200 ... 0x2FF: 1757 pnv_xive2_ic_pc_write(opaque, mmio_offset, val, size); 1758 break; 1759 case 0x300 ... 0x3FF: 1760 pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size); 1761 break; 1762 default: 1763 xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset); 1764 } 1765 } 1766 1767 static const MemoryRegionOps pnv_xive2_xscom_ops = { 1768 .read = pnv_xive2_xscom_read, 1769 .write = pnv_xive2_xscom_write, 1770 .endianness = DEVICE_BIG_ENDIAN, 1771 .valid = { 1772 .min_access_size = 8, 1773 .max_access_size = 8, 1774 }, 1775 .impl = { 1776 .min_access_size = 8, 1777 .max_access_size = 8, 1778 }, 1779 }; 1780 1781 /* 1782 * Notify port page. The layout is compatible between 4K and 64K pages : 1783 * 1784 * Page 1 Notify page (writes only) 1785 * 0x000 - 0x7FF IPI interrupt (NPU) 1786 * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB) 1787 */ 1788 1789 static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr, 1790 uint64_t val) 1791 { 1792 uint8_t blk; 1793 uint32_t idx; 1794 1795 if (val & XIVE_TRIGGER_END) { 1796 xive2_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1797 addr, val); 1798 return; 1799 } 1800 1801 /* 1802 * Forward the source event notification directly to the Router. 1803 * The source interrupt number should already be correctly encoded 1804 * with the chip block id by the sending device (PHB, PSI). 1805 */ 1806 blk = XIVE_EAS_BLOCK(val); 1807 idx = XIVE_EAS_INDEX(val); 1808 1809 xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx), 1810 !!(val & XIVE_TRIGGER_PQ)); 1811 } 1812 1813 static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset, 1814 uint64_t val, unsigned size) 1815 { 1816 PnvXive2 *xive = PNV_XIVE2(opaque); 1817 1818 /* VC: IPI triggers */ 1819 switch (offset) { 1820 case 0x000 ... 0x7FF: 1821 /* TODO: check IPI notify sub-page routing */ 1822 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1823 break; 1824 1825 /* VC: HW triggers */ 1826 case 0x800 ... 0xFFF: 1827 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1828 break; 1829 1830 default: 1831 xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset); 1832 } 1833 } 1834 1835 static uint64_t pnv_xive2_ic_notify_read(void *opaque, hwaddr offset, 1836 unsigned size) 1837 { 1838 PnvXive2 *xive = PNV_XIVE2(opaque); 1839 1840 /* loads are invalid */ 1841 xive2_error(xive, "NOTIFY: invalid read @%"HWADDR_PRIx, offset); 1842 return -1; 1843 } 1844 1845 static const MemoryRegionOps pnv_xive2_ic_notify_ops = { 1846 .read = pnv_xive2_ic_notify_read, 1847 .write = pnv_xive2_ic_notify_write, 1848 .endianness = DEVICE_BIG_ENDIAN, 1849 .valid = { 1850 .min_access_size = 8, 1851 .max_access_size = 8, 1852 }, 1853 .impl = { 1854 .min_access_size = 8, 1855 .max_access_size = 8, 1856 }, 1857 }; 1858 1859 static uint64_t pnv_xive2_ic_lsi_read(void *opaque, hwaddr offset, 1860 unsigned size) 1861 { 1862 PnvXive2 *xive = PNV_XIVE2(opaque); 1863 1864 xive2_error(xive, "LSI: invalid read @%"HWADDR_PRIx, offset); 1865 return -1; 1866 } 1867 1868 static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset, 1869 uint64_t val, unsigned size) 1870 { 1871 PnvXive2 *xive = PNV_XIVE2(opaque); 1872 1873 xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset); 1874 } 1875 1876 static const MemoryRegionOps pnv_xive2_ic_lsi_ops = { 1877 .read = pnv_xive2_ic_lsi_read, 1878 .write = pnv_xive2_ic_lsi_write, 1879 .endianness = DEVICE_BIG_ENDIAN, 1880 .valid = { 1881 .min_access_size = 8, 1882 .max_access_size = 8, 1883 }, 1884 .impl = { 1885 .min_access_size = 8, 1886 .max_access_size = 8, 1887 }, 1888 }; 1889 1890 /* 1891 * Sync MMIO page (write only) 1892 */ 1893 #define PNV_XIVE2_SYNC_IPI 0x000 1894 #define PNV_XIVE2_SYNC_HW 0x080 1895 #define PNV_XIVE2_SYNC_NxC 0x100 1896 #define PNV_XIVE2_SYNC_INT 0x180 1897 #define PNV_XIVE2_SYNC_OS_ESC 0x200 1898 #define PNV_XIVE2_SYNC_POOL_ESC 0x280 1899 #define PNV_XIVE2_SYNC_HARD_ESC 0x300 1900 #define PNV_XIVE2_SYNC_NXC_LD_LCL_NCO 0x800 1901 #define PNV_XIVE2_SYNC_NXC_LD_LCL_CO 0x880 1902 #define PNV_XIVE2_SYNC_NXC_ST_LCL_NCI 0x900 1903 #define PNV_XIVE2_SYNC_NXC_ST_LCL_CI 0x980 1904 #define PNV_XIVE2_SYNC_NXC_ST_RMT_NCI 0xA00 1905 #define PNV_XIVE2_SYNC_NXC_ST_RMT_CI 0xA80 1906 1907 static uint64_t pnv_xive2_ic_sync_read(void *opaque, hwaddr offset, 1908 unsigned size) 1909 { 1910 PnvXive2 *xive = PNV_XIVE2(opaque); 1911 1912 /* loads are invalid */ 1913 xive2_error(xive, "SYNC: invalid read @%"HWADDR_PRIx, offset); 1914 return -1; 1915 } 1916 1917 /* 1918 * The sync MMIO space spans two pages. The lower page is use for 1919 * queue sync "poll" requests while the upper page is used for queue 1920 * sync "inject" requests. Inject requests require the HW to write 1921 * a byte of all 1's to a predetermined location in memory in order 1922 * to signal completion of the request. Both pages have the same 1923 * layout, so it is easiest to handle both with a single function. 1924 */ 1925 static void pnv_xive2_ic_sync_write(void *opaque, hwaddr offset, 1926 uint64_t val, unsigned size) 1927 { 1928 PnvXive2 *xive = PNV_XIVE2(opaque); 1929 int inject_type; 1930 hwaddr pg_offset_mask = (1ull << xive->ic_shift) - 1; 1931 1932 /* adjust offset for inject page */ 1933 hwaddr adj_offset = offset & pg_offset_mask; 1934 1935 switch (adj_offset) { 1936 case PNV_XIVE2_SYNC_IPI: 1937 inject_type = PNV_XIVE2_QUEUE_IPI; 1938 break; 1939 case PNV_XIVE2_SYNC_HW: 1940 inject_type = PNV_XIVE2_QUEUE_HW; 1941 break; 1942 case PNV_XIVE2_SYNC_NxC: 1943 inject_type = PNV_XIVE2_QUEUE_NXC; 1944 break; 1945 case PNV_XIVE2_SYNC_INT: 1946 inject_type = PNV_XIVE2_QUEUE_INT; 1947 break; 1948 case PNV_XIVE2_SYNC_OS_ESC: 1949 inject_type = PNV_XIVE2_QUEUE_OS; 1950 break; 1951 case PNV_XIVE2_SYNC_POOL_ESC: 1952 inject_type = PNV_XIVE2_QUEUE_POOL; 1953 break; 1954 case PNV_XIVE2_SYNC_HARD_ESC: 1955 inject_type = PNV_XIVE2_QUEUE_HARD; 1956 break; 1957 case PNV_XIVE2_SYNC_NXC_LD_LCL_NCO: 1958 inject_type = PNV_XIVE2_QUEUE_NXC_LD_LCL_NCO; 1959 break; 1960 case PNV_XIVE2_SYNC_NXC_LD_LCL_CO: 1961 inject_type = PNV_XIVE2_QUEUE_NXC_LD_LCL_CO; 1962 break; 1963 case PNV_XIVE2_SYNC_NXC_ST_LCL_NCI: 1964 inject_type = PNV_XIVE2_QUEUE_NXC_ST_LCL_NCI; 1965 break; 1966 case PNV_XIVE2_SYNC_NXC_ST_LCL_CI: 1967 inject_type = PNV_XIVE2_QUEUE_NXC_ST_LCL_CI; 1968 break; 1969 case PNV_XIVE2_SYNC_NXC_ST_RMT_NCI: 1970 inject_type = PNV_XIVE2_QUEUE_NXC_ST_RMT_NCI; 1971 break; 1972 case PNV_XIVE2_SYNC_NXC_ST_RMT_CI: 1973 inject_type = PNV_XIVE2_QUEUE_NXC_ST_RMT_CI; 1974 break; 1975 default: 1976 xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset); 1977 return; 1978 } 1979 1980 /* Write Queue Sync notification byte if writing to sync inject page */ 1981 if ((offset & ~pg_offset_mask) != 0) { 1982 pnv_xive2_inject_notify(xive, inject_type); 1983 } 1984 } 1985 1986 static const MemoryRegionOps pnv_xive2_ic_sync_ops = { 1987 .read = pnv_xive2_ic_sync_read, 1988 .write = pnv_xive2_ic_sync_write, 1989 .endianness = DEVICE_BIG_ENDIAN, 1990 .valid = { 1991 .min_access_size = 8, 1992 .max_access_size = 8, 1993 }, 1994 .impl = { 1995 .min_access_size = 8, 1996 .max_access_size = 8, 1997 }, 1998 }; 1999 2000 /* 2001 * When the TM direct pages of the IC controller are accessed, the 2002 * target HW thread is deduced from the page offset. 2003 */ 2004 static uint32_t pnv_xive2_ic_tm_get_pir(PnvXive2 *xive, hwaddr offset) 2005 { 2006 /* On P10, the node ID shift in the PIR register is 8 bits */ 2007 return xive->chip->chip_id << 8 | offset >> xive->ic_shift; 2008 } 2009 2010 static uint32_t pnv_xive2_ic_tm_get_hw_page_offset(PnvXive2 *xive, 2011 hwaddr offset) 2012 { 2013 /* 2014 * Indirect TIMA accesses are similar to direct accesses for 2015 * privilege ring 0. So remove any traces of the hw thread ID from 2016 * the offset in the IC BAR as it could be interpreted as the ring 2017 * privilege when calling the underlying direct access functions. 2018 */ 2019 return offset & ((1ull << xive->ic_shift) - 1); 2020 } 2021 2022 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) 2023 { 2024 PnvChip *chip = xive->chip; 2025 PowerPCCPU *cpu = NULL; 2026 2027 cpu = pnv_chip_find_cpu(chip, pir); 2028 if (!cpu) { 2029 xive2_error(xive, "IC: invalid PIR %x for indirect access", pir); 2030 return NULL; 2031 } 2032 2033 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 2034 xive2_error(xive, "IC: CPU %x is not enabled", pir); 2035 } 2036 2037 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 2038 } 2039 2040 static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset, 2041 unsigned size) 2042 { 2043 PnvXive2 *xive = PNV_XIVE2(opaque); 2044 XivePresenter *xptr = XIVE_PRESENTER(xive); 2045 hwaddr hw_page_offset; 2046 uint32_t pir; 2047 XiveTCTX *tctx; 2048 uint64_t val = -1; 2049 2050 pir = pnv_xive2_ic_tm_get_pir(xive, offset); 2051 hw_page_offset = pnv_xive2_ic_tm_get_hw_page_offset(xive, offset); 2052 tctx = pnv_xive2_get_indirect_tctx(xive, pir); 2053 if (tctx) { 2054 val = xive_tctx_tm_read(xptr, tctx, hw_page_offset, size); 2055 } 2056 2057 return val; 2058 } 2059 2060 static void pnv_xive2_ic_tm_indirect_write(void *opaque, hwaddr offset, 2061 uint64_t val, unsigned size) 2062 { 2063 PnvXive2 *xive = PNV_XIVE2(opaque); 2064 XivePresenter *xptr = XIVE_PRESENTER(xive); 2065 hwaddr hw_page_offset; 2066 uint32_t pir; 2067 XiveTCTX *tctx; 2068 2069 pir = pnv_xive2_ic_tm_get_pir(xive, offset); 2070 hw_page_offset = pnv_xive2_ic_tm_get_hw_page_offset(xive, offset); 2071 tctx = pnv_xive2_get_indirect_tctx(xive, pir); 2072 if (tctx) { 2073 xive_tctx_tm_write(xptr, tctx, hw_page_offset, val, size); 2074 } 2075 } 2076 2077 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = { 2078 .read = pnv_xive2_ic_tm_indirect_read, 2079 .write = pnv_xive2_ic_tm_indirect_write, 2080 .endianness = DEVICE_BIG_ENDIAN, 2081 .valid = { 2082 .min_access_size = 1, 2083 .max_access_size = 8, 2084 }, 2085 .impl = { 2086 .min_access_size = 1, 2087 .max_access_size = 8, 2088 }, 2089 }; 2090 2091 /* 2092 * TIMA ops 2093 */ 2094 static void pnv_xive2_tm_write(void *opaque, hwaddr offset, 2095 uint64_t value, unsigned size) 2096 { 2097 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 2098 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 2099 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 2100 XivePresenter *xptr = XIVE_PRESENTER(xive); 2101 2102 xive_tctx_tm_write(xptr, tctx, offset, value, size); 2103 } 2104 2105 static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) 2106 { 2107 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 2108 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 2109 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 2110 XivePresenter *xptr = XIVE_PRESENTER(xive); 2111 2112 return xive_tctx_tm_read(xptr, tctx, offset, size); 2113 } 2114 2115 static const MemoryRegionOps pnv_xive2_tm_ops = { 2116 .read = pnv_xive2_tm_read, 2117 .write = pnv_xive2_tm_write, 2118 .endianness = DEVICE_BIG_ENDIAN, 2119 .valid = { 2120 .min_access_size = 1, 2121 .max_access_size = 8, 2122 }, 2123 .impl = { 2124 .min_access_size = 1, 2125 .max_access_size = 8, 2126 }, 2127 }; 2128 2129 static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset, 2130 unsigned size) 2131 { 2132 PnvXive2 *xive = PNV_XIVE2(opaque); 2133 2134 xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset); 2135 return -1; 2136 } 2137 2138 static void pnv_xive2_nvc_write(void *opaque, hwaddr offset, 2139 uint64_t val, unsigned size) 2140 { 2141 PnvXive2 *xive = PNV_XIVE2(opaque); 2142 2143 xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset); 2144 } 2145 2146 static const MemoryRegionOps pnv_xive2_nvc_ops = { 2147 .read = pnv_xive2_nvc_read, 2148 .write = pnv_xive2_nvc_write, 2149 .endianness = DEVICE_BIG_ENDIAN, 2150 .valid = { 2151 .min_access_size = 8, 2152 .max_access_size = 8, 2153 }, 2154 .impl = { 2155 .min_access_size = 8, 2156 .max_access_size = 8, 2157 }, 2158 }; 2159 2160 static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset, 2161 unsigned size) 2162 { 2163 PnvXive2 *xive = PNV_XIVE2(opaque); 2164 2165 xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset); 2166 return -1; 2167 } 2168 2169 static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset, 2170 uint64_t val, unsigned size) 2171 { 2172 PnvXive2 *xive = PNV_XIVE2(opaque); 2173 2174 xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset); 2175 } 2176 2177 static const MemoryRegionOps pnv_xive2_nvpg_ops = { 2178 .read = pnv_xive2_nvpg_read, 2179 .write = pnv_xive2_nvpg_write, 2180 .endianness = DEVICE_BIG_ENDIAN, 2181 .valid = { 2182 .min_access_size = 8, 2183 .max_access_size = 8, 2184 }, 2185 .impl = { 2186 .min_access_size = 8, 2187 .max_access_size = 8, 2188 }, 2189 }; 2190 2191 /* 2192 * POWER10 default capabilities: 0x2000120076f000FC 2193 */ 2194 #define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC 2195 2196 /* 2197 * POWER10 default configuration: 0x0030000033000000 2198 * 2199 * 8bits thread id was dropped for P10 2200 */ 2201 #define PNV_XIVE2_CONFIGURATION 0x0030000033000000 2202 2203 static void pnv_xive2_reset(void *dev) 2204 { 2205 PnvXive2 *xive = PNV_XIVE2(dev); 2206 XiveSource *xsrc = &xive->ipi_source; 2207 Xive2EndSource *end_xsrc = &xive->end_source; 2208 2209 xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities; 2210 xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config; 2211 2212 /* HW hardwires the #Topology of the chip in the block field */ 2213 xive->cq_regs[CQ_XIVE_CFG >> 3] |= 2214 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id); 2215 2216 /* VC and PC cache watch assign mechanism */ 2217 xive->vc_regs[VC_ENDC_CFG >> 3] = 2218 SETFIELD(VC_ENDC_CFG_CACHE_WATCH_ASSIGN, 0ull, 0b0111); 2219 xive->pc_regs[PC_NXC_PROC_CONFIG >> 3] = 2220 SETFIELD(PC_NXC_PROC_CONFIG_WATCH_ASSIGN, 0ull, 0b0111); 2221 2222 /* Set default page size to 64k */ 2223 xive->ic_shift = xive->esb_shift = xive->end_shift = 16; 2224 xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16; 2225 2226 /* Clear source MMIOs */ 2227 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 2228 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); 2229 } 2230 2231 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 2232 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); 2233 } 2234 } 2235 2236 /* 2237 * Maximum number of IRQs and ENDs supported by HW. Will be tuned by 2238 * software. 2239 */ 2240 #define PNV_XIVE2_NR_IRQS (PNV10_XIVE2_ESB_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 2241 #define PNV_XIVE2_NR_ENDS (PNV10_XIVE2_END_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 2242 2243 static void pnv_xive2_realize(DeviceState *dev, Error **errp) 2244 { 2245 PnvXive2 *xive = PNV_XIVE2(dev); 2246 PnvXive2Class *pxc = PNV_XIVE2_GET_CLASS(dev); 2247 XiveSource *xsrc = &xive->ipi_source; 2248 Xive2EndSource *end_xsrc = &xive->end_source; 2249 Error *local_err = NULL; 2250 int i; 2251 2252 pxc->parent_realize(dev, &local_err); 2253 if (local_err) { 2254 error_propagate(errp, local_err); 2255 return; 2256 } 2257 2258 assert(xive->chip); 2259 2260 /* 2261 * The XiveSource and Xive2EndSource objects are realized with the 2262 * maximum allowed HW configuration. The ESB MMIO regions will be 2263 * resized dynamically when the controller is configured by the FW 2264 * to limit accesses to resources not provisioned. 2265 */ 2266 object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI, 2267 &error_fatal); 2268 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS, 2269 &error_fatal); 2270 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), 2271 &error_fatal); 2272 qdev_realize(DEVICE(xsrc), NULL, &local_err); 2273 if (local_err) { 2274 error_propagate(errp, local_err); 2275 return; 2276 } 2277 2278 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS, 2279 &error_fatal); 2280 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 2281 &error_abort); 2282 qdev_realize(DEVICE(end_xsrc), NULL, &local_err); 2283 if (local_err) { 2284 error_propagate(errp, local_err); 2285 return; 2286 } 2287 2288 /* XSCOM region, used for initial configuration of the BARs */ 2289 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), 2290 &pnv_xive2_xscom_ops, xive, "xscom-xive", 2291 PNV10_XSCOM_XIVE2_SIZE << 3); 2292 2293 /* Interrupt controller MMIO regions */ 2294 xive->ic_shift = 16; 2295 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 2296 PNV10_XIVE2_IC_SIZE); 2297 2298 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 2299 memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev), 2300 pnv_xive2_ic_regions[i].ops, xive, 2301 pnv_xive2_ic_regions[i].name, 2302 pnv_xive2_ic_regions[i].pgsize << xive->ic_shift); 2303 } 2304 2305 /* 2306 * VC MMIO regions. 2307 */ 2308 xive->esb_shift = 16; 2309 xive->end_shift = 16; 2310 memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb", 2311 PNV10_XIVE2_ESB_SIZE); 2312 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end", 2313 PNV10_XIVE2_END_SIZE); 2314 2315 /* Presenter Controller MMIO region (not modeled) */ 2316 xive->nvc_shift = 16; 2317 xive->nvpg_shift = 16; 2318 memory_region_init_io(&xive->nvc_mmio, OBJECT(dev), 2319 &pnv_xive2_nvc_ops, xive, 2320 "xive-nvc", PNV10_XIVE2_NVC_SIZE); 2321 2322 memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev), 2323 &pnv_xive2_nvpg_ops, xive, 2324 "xive-nvpg", PNV10_XIVE2_NVPG_SIZE); 2325 2326 /* Thread Interrupt Management Area (Direct) */ 2327 xive->tm_shift = 16; 2328 memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops, 2329 xive, "xive-tima", PNV10_XIVE2_TM_SIZE); 2330 2331 qemu_register_reset(pnv_xive2_reset, dev); 2332 } 2333 2334 static Property pnv_xive2_properties[] = { 2335 DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0), 2336 DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0), 2337 DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0), 2338 DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0), 2339 DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0), 2340 DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0), 2341 DEFINE_PROP_UINT64("capabilities", PnvXive2, capabilities, 2342 PNV_XIVE2_CAPABILITIES), 2343 DEFINE_PROP_UINT64("config", PnvXive2, config, 2344 PNV_XIVE2_CONFIGURATION), 2345 DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *), 2346 DEFINE_PROP_END_OF_LIST(), 2347 }; 2348 2349 static void pnv_xive2_instance_init(Object *obj) 2350 { 2351 PnvXive2 *xive = PNV_XIVE2(obj); 2352 2353 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 2354 TYPE_XIVE_SOURCE); 2355 object_initialize_child(obj, "end_source", &xive->end_source, 2356 TYPE_XIVE2_END_SOURCE); 2357 } 2358 2359 static int pnv_xive2_dt_xscom(PnvXScomInterface *dev, void *fdt, 2360 int xscom_offset) 2361 { 2362 const char compat_p10[] = "ibm,power10-xive-x"; 2363 char *name; 2364 int offset; 2365 uint32_t reg[] = { 2366 cpu_to_be32(PNV10_XSCOM_XIVE2_BASE), 2367 cpu_to_be32(PNV10_XSCOM_XIVE2_SIZE) 2368 }; 2369 2370 name = g_strdup_printf("xive@%x", PNV10_XSCOM_XIVE2_BASE); 2371 offset = fdt_add_subnode(fdt, xscom_offset, name); 2372 _FDT(offset); 2373 g_free(name); 2374 2375 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 2376 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, 2377 sizeof(compat_p10))); 2378 return 0; 2379 } 2380 2381 static void pnv_xive2_class_init(ObjectClass *klass, void *data) 2382 { 2383 DeviceClass *dc = DEVICE_CLASS(klass); 2384 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 2385 Xive2RouterClass *xrc = XIVE2_ROUTER_CLASS(klass); 2386 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 2387 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 2388 PnvXive2Class *pxc = PNV_XIVE2_CLASS(klass); 2389 2390 xdc->dt_xscom = pnv_xive2_dt_xscom; 2391 2392 dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)"; 2393 device_class_set_parent_realize(dc, pnv_xive2_realize, 2394 &pxc->parent_realize); 2395 device_class_set_props(dc, pnv_xive2_properties); 2396 2397 xrc->get_eas = pnv_xive2_get_eas; 2398 xrc->get_pq = pnv_xive2_get_pq; 2399 xrc->set_pq = pnv_xive2_set_pq; 2400 xrc->get_end = pnv_xive2_get_end; 2401 xrc->write_end = pnv_xive2_write_end; 2402 xrc->get_nvp = pnv_xive2_get_nvp; 2403 xrc->write_nvp = pnv_xive2_write_nvp; 2404 xrc->get_config = pnv_xive2_get_config; 2405 xrc->get_block_id = pnv_xive2_get_block_id; 2406 2407 xnc->notify = pnv_xive2_notify; 2408 2409 xpc->match_nvt = pnv_xive2_match_nvt; 2410 xpc->get_config = pnv_xive2_presenter_get_config; 2411 }; 2412 2413 static const TypeInfo pnv_xive2_info = { 2414 .name = TYPE_PNV_XIVE2, 2415 .parent = TYPE_XIVE2_ROUTER, 2416 .instance_init = pnv_xive2_instance_init, 2417 .instance_size = sizeof(PnvXive2), 2418 .class_init = pnv_xive2_class_init, 2419 .class_size = sizeof(PnvXive2Class), 2420 .interfaces = (InterfaceInfo[]) { 2421 { TYPE_PNV_XSCOM_INTERFACE }, 2422 { } 2423 } 2424 }; 2425 2426 static void pnv_xive2_register_types(void) 2427 { 2428 type_register_static(&pnv_xive2_info); 2429 } 2430 2431 type_init(pnv_xive2_register_types) 2432 2433 static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, 2434 GString *buf) 2435 { 2436 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 2437 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 2438 2439 if (!xive2_nvp_is_valid(nvp)) { 2440 return; 2441 } 2442 2443 g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x", 2444 nvp_idx, eq_blk, eq_idx, 2445 xive_get_field32(NVP2_W2_IPB, nvp->w2)); 2446 /* 2447 * When the NVP is HW controlled, more fields are updated 2448 */ 2449 if (xive2_nvp_is_hw(nvp)) { 2450 g_string_append_printf(buf, " CPPR:%02x", 2451 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 2452 if (xive2_nvp_is_co(nvp)) { 2453 g_string_append_printf(buf, " CO:%04x", 2454 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 2455 } 2456 } 2457 g_string_append_c(buf, '\n'); 2458 } 2459 2460 /* 2461 * If the table is direct, we can compute the number of PQ entries 2462 * provisioned by FW. 2463 */ 2464 static uint32_t pnv_xive2_nr_esbs(PnvXive2 *xive) 2465 { 2466 uint8_t blk = pnv_xive2_block_id(xive); 2467 uint64_t vsd = xive->vsds[VST_ESB][blk]; 2468 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 2469 2470 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 2471 } 2472 2473 /* 2474 * Compute the number of entries per indirect subpage. 2475 */ 2476 static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type) 2477 { 2478 uint8_t blk = pnv_xive2_block_id(xive); 2479 uint64_t vsd = xive->vsds[type][blk]; 2480 const XiveVstInfo *info = &vst_infos[type]; 2481 uint64_t vsd_addr; 2482 uint32_t page_shift; 2483 2484 /* For direct tables, fake a valid value */ 2485 if (!(VSD_INDIRECT & vsd)) { 2486 return 1; 2487 } 2488 2489 /* Get the page size of the indirect table. */ 2490 vsd_addr = vsd & VSD_ADDRESS_MASK; 2491 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 2492 2493 if (!(vsd & VSD_ADDRESS_MASK)) { 2494 #ifdef XIVE2_DEBUG 2495 xive2_error(xive, "VST: invalid %s entry!?", info->name); 2496 #endif 2497 return 0; 2498 } 2499 2500 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 2501 2502 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 2503 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 2504 page_shift); 2505 return 0; 2506 } 2507 2508 return (1ull << page_shift) / info->size; 2509 } 2510 2511 void pnv_xive2_pic_print_info(PnvXive2 *xive, GString *buf) 2512 { 2513 Xive2Router *xrtr = XIVE2_ROUTER(xive); 2514 uint8_t blk = pnv_xive2_block_id(xive); 2515 uint8_t chip_id = xive->chip->chip_id; 2516 uint32_t srcno0 = XIVE_EAS(blk, 0); 2517 uint32_t nr_esbs = pnv_xive2_nr_esbs(xive); 2518 Xive2Eas eas; 2519 Xive2End end; 2520 Xive2Nvp nvp; 2521 int i; 2522 uint64_t xive_nvp_per_subpage; 2523 2524 g_string_append_printf(buf, "XIVE[%x] Source %08x .. %08x\n", 2525 blk, srcno0, srcno0 + nr_esbs - 1); 2526 xive_source_pic_print_info(&xive->ipi_source, srcno0, buf); 2527 2528 g_string_append_printf(buf, "XIVE[%x] EAT %08x .. %08x\n", 2529 blk, srcno0, srcno0 + nr_esbs - 1); 2530 for (i = 0; i < nr_esbs; i++) { 2531 if (xive2_router_get_eas(xrtr, blk, i, &eas)) { 2532 break; 2533 } 2534 if (!xive2_eas_is_masked(&eas)) { 2535 xive2_eas_pic_print_info(&eas, i, buf); 2536 } 2537 } 2538 2539 g_string_append_printf(buf, "XIVE[%x] #%d END Escalation EAT\n", 2540 chip_id, blk); 2541 i = 0; 2542 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2543 xive2_end_eas_pic_print_info(&end, i++, buf); 2544 } 2545 2546 g_string_append_printf(buf, "XIVE[%x] #%d ENDT\n", chip_id, blk); 2547 i = 0; 2548 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2549 xive2_end_pic_print_info(&end, i++, buf); 2550 } 2551 2552 g_string_append_printf(buf, "XIVE[%x] #%d NVPT %08x .. %08x\n", 2553 chip_id, blk, 0, XIVE2_NVP_COUNT - 1); 2554 xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); 2555 for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) { 2556 while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) { 2557 xive2_nvp_pic_print_info(&nvp, i++, buf); 2558 } 2559 } 2560 } 2561