1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "sysemu/cpus.h" 15 #include "sysemu/dma.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/pnv.h" 19 #include "hw/ppc/pnv_core.h" 20 #include "hw/ppc/pnv_xscom.h" 21 #include "hw/ppc/xive2.h" 22 #include "hw/ppc/pnv_xive.h" 23 #include "hw/ppc/xive_regs.h" 24 #include "hw/ppc/xive2_regs.h" 25 #include "hw/ppc/ppc.h" 26 #include "hw/qdev-properties.h" 27 #include "sysemu/reset.h" 28 29 #include <libfdt.h> 30 31 #include "pnv_xive2_regs.h" 32 33 #undef XIVE2_DEBUG 34 35 /* 36 * Virtual structures table (VST) 37 */ 38 #define SBE_PER_BYTE 4 39 40 typedef struct XiveVstInfo { 41 const char *name; 42 uint32_t size; 43 uint32_t max_blocks; 44 } XiveVstInfo; 45 46 static const XiveVstInfo vst_infos[] = { 47 48 [VST_EAS] = { "EAT", sizeof(Xive2Eas), 16 }, 49 [VST_ESB] = { "ESB", 1, 16 }, 50 [VST_END] = { "ENDT", sizeof(Xive2End), 16 }, 51 52 [VST_NVP] = { "NVPT", sizeof(Xive2Nvp), 16 }, 53 [VST_NVG] = { "NVGT", sizeof(Xive2Nvgc), 16 }, 54 [VST_NVC] = { "NVCT", sizeof(Xive2Nvgc), 16 }, 55 56 [VST_IC] = { "IC", 1 /* ? */ , 16 }, /* Topology # */ 57 [VST_SYNC] = { "SYNC", 1 /* ? */ , 16 }, /* Topology # */ 58 59 /* 60 * This table contains the backing store pages for the interrupt 61 * fifos of the VC sub-engine in case of overflow. 62 * 63 * 0 - IPI, 64 * 1 - HWD, 65 * 2 - NxC, 66 * 3 - INT, 67 * 4 - OS-Queue, 68 * 5 - Pool-Queue, 69 * 6 - Hard-Queue 70 */ 71 [VST_ERQ] = { "ERQ", 1, VC_QUEUE_COUNT }, 72 }; 73 74 #define xive2_error(xive, fmt, ...) \ 75 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 76 (xive)->chip->chip_id, ## __VA_ARGS__); 77 78 /* 79 * QEMU version of the GETFIELD/SETFIELD macros 80 * 81 * TODO: It might be better to use the existing extract64() and 82 * deposit64() but this means that all the register definitions will 83 * change and become incompatible with the ones found in skiboot. 84 * 85 * Keep it as it is for now until we find a common ground. 86 */ 87 static inline uint64_t GETFIELD(uint64_t mask, uint64_t word) 88 { 89 return (word & mask) >> ctz64(mask); 90 } 91 92 static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, 93 uint64_t value) 94 { 95 return (word & ~mask) | ((value << ctz64(mask)) & mask); 96 } 97 98 /* 99 * TODO: Document block id override 100 */ 101 static uint32_t pnv_xive2_block_id(PnvXive2 *xive) 102 { 103 uint8_t blk = xive->chip->chip_id; 104 uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3]; 105 106 if (cfg_val & CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE) { 107 blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val); 108 } 109 110 return blk; 111 } 112 113 /* 114 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 115 * of the chips is good enough. 116 * 117 * TODO: Block scope support 118 */ 119 static PnvXive2 *pnv_xive2_get_remote(uint8_t blk) 120 { 121 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 122 int i; 123 124 for (i = 0; i < pnv->num_chips; i++) { 125 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 126 PnvXive2 *xive = &chip10->xive; 127 128 if (pnv_xive2_block_id(xive) == blk) { 129 return xive; 130 } 131 } 132 return NULL; 133 } 134 135 /* 136 * VST accessors for ESB, EAT, ENDT, NVP 137 * 138 * Indirect VST tables are arrays of VSDs pointing to a page (of same 139 * size). Each page is a direct VST table. 140 */ 141 142 #define XIVE_VSD_SIZE 8 143 144 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 145 static uint64_t pnv_xive2_vst_page_size_allowed(uint32_t page_shift) 146 { 147 return page_shift == 12 || page_shift == 16 || 148 page_shift == 21 || page_shift == 24; 149 } 150 151 static uint64_t pnv_xive2_vst_addr_direct(PnvXive2 *xive, uint32_t type, 152 uint64_t vsd, uint32_t idx) 153 { 154 const XiveVstInfo *info = &vst_infos[type]; 155 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 156 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 157 uint32_t idx_max; 158 159 idx_max = vst_tsize / info->size - 1; 160 if (idx > idx_max) { 161 #ifdef XIVE2_DEBUG 162 xive2_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 163 info->name, idx, idx_max); 164 #endif 165 return 0; 166 } 167 168 return vst_addr + idx * info->size; 169 } 170 171 static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type, 172 uint64_t vsd, uint32_t idx) 173 { 174 const XiveVstInfo *info = &vst_infos[type]; 175 uint64_t vsd_addr; 176 uint32_t vsd_idx; 177 uint32_t page_shift; 178 uint32_t vst_per_page; 179 180 /* Get the page size of the indirect table. */ 181 vsd_addr = vsd & VSD_ADDRESS_MASK; 182 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 183 184 if (!(vsd & VSD_ADDRESS_MASK)) { 185 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 186 return 0; 187 } 188 189 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 190 191 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 192 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 193 page_shift); 194 return 0; 195 } 196 197 vst_per_page = (1ull << page_shift) / info->size; 198 vsd_idx = idx / vst_per_page; 199 200 /* Load the VSD we are looking for, if not already done */ 201 if (vsd_idx) { 202 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 203 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, 204 MEMTXATTRS_UNSPECIFIED); 205 206 if (!(vsd & VSD_ADDRESS_MASK)) { 207 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 208 return 0; 209 } 210 211 /* 212 * Check that the pages have a consistent size across the 213 * indirect table 214 */ 215 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 216 xive2_error(xive, "VST: %s entry %x indirect page size differ !?", 217 info->name, idx); 218 return 0; 219 } 220 } 221 222 return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 223 } 224 225 static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk, 226 uint32_t idx) 227 { 228 const XiveVstInfo *info = &vst_infos[type]; 229 uint64_t vsd; 230 231 if (blk >= info->max_blocks) { 232 xive2_error(xive, "VST: invalid block id %d for VST %s %d !?", 233 blk, info->name, idx); 234 return 0; 235 } 236 237 vsd = xive->vsds[type][blk]; 238 239 /* Remote VST access */ 240 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 241 xive = pnv_xive2_get_remote(blk); 242 243 return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0; 244 } 245 246 if (VSD_INDIRECT & vsd) { 247 return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx); 248 } 249 250 return pnv_xive2_vst_addr_direct(xive, type, vsd, idx); 251 } 252 253 static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk, 254 uint32_t idx, void *data) 255 { 256 const XiveVstInfo *info = &vst_infos[type]; 257 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 258 259 if (!addr) { 260 return -1; 261 } 262 263 cpu_physical_memory_read(addr, data, info->size); 264 return 0; 265 } 266 267 #define XIVE_VST_WORD_ALL -1 268 269 static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk, 270 uint32_t idx, void *data, uint32_t word_number) 271 { 272 const XiveVstInfo *info = &vst_infos[type]; 273 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 274 275 if (!addr) { 276 return -1; 277 } 278 279 if (word_number == XIVE_VST_WORD_ALL) { 280 cpu_physical_memory_write(addr, data, info->size); 281 } else { 282 cpu_physical_memory_write(addr + word_number * 4, 283 data + word_number * 4, 4); 284 } 285 return 0; 286 } 287 288 static int pnv_xive2_get_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 289 uint8_t *pq) 290 { 291 PnvXive2 *xive = PNV_XIVE2(xrtr); 292 293 if (pnv_xive2_block_id(xive) != blk) { 294 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 295 return -1; 296 } 297 298 *pq = xive_source_esb_get(&xive->ipi_source, idx); 299 return 0; 300 } 301 302 static int pnv_xive2_set_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 303 uint8_t *pq) 304 { 305 PnvXive2 *xive = PNV_XIVE2(xrtr); 306 307 if (pnv_xive2_block_id(xive) != blk) { 308 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 309 return -1; 310 } 311 312 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq); 313 return 0; 314 } 315 316 static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 317 Xive2End *end) 318 { 319 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_END, blk, idx, end); 320 } 321 322 static int pnv_xive2_write_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 323 Xive2End *end, uint8_t word_number) 324 { 325 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_END, blk, idx, end, 326 word_number); 327 } 328 329 static int pnv_xive2_end_update(PnvXive2 *xive) 330 { 331 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 332 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 333 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 334 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 335 int i; 336 uint64_t endc_watch[4]; 337 338 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 339 endc_watch[i] = 340 cpu_to_be64(xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i]); 341 } 342 343 return pnv_xive2_vst_write(xive, VST_END, blk, idx, endc_watch, 344 XIVE_VST_WORD_ALL); 345 } 346 347 static void pnv_xive2_end_cache_load(PnvXive2 *xive) 348 { 349 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 350 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 351 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 352 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 353 uint64_t endc_watch[4] = { 0 }; 354 int i; 355 356 if (pnv_xive2_vst_read(xive, VST_END, blk, idx, endc_watch)) { 357 xive2_error(xive, "VST: no END entry %x/%x !?", blk, idx); 358 } 359 360 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 361 xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i] = 362 be64_to_cpu(endc_watch[i]); 363 } 364 } 365 366 static int pnv_xive2_get_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 367 Xive2Nvp *nvp) 368 { 369 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp); 370 } 371 372 static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 373 Xive2Nvp *nvp, uint8_t word_number) 374 { 375 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp, 376 word_number); 377 } 378 379 static int pnv_xive2_nvp_update(PnvXive2 *xive) 380 { 381 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 382 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 383 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 384 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 385 int i; 386 uint64_t nxc_watch[4]; 387 388 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 389 nxc_watch[i] = 390 cpu_to_be64(xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i]); 391 } 392 393 return pnv_xive2_vst_write(xive, VST_NVP, blk, idx, nxc_watch, 394 XIVE_VST_WORD_ALL); 395 } 396 397 static void pnv_xive2_nvp_cache_load(PnvXive2 *xive) 398 { 399 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 400 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 401 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 402 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 403 uint64_t nxc_watch[4] = { 0 }; 404 int i; 405 406 if (pnv_xive2_vst_read(xive, VST_NVP, blk, idx, nxc_watch)) { 407 xive2_error(xive, "VST: no NVP entry %x/%x !?", blk, idx); 408 } 409 410 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 411 xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i] = 412 be64_to_cpu(nxc_watch[i]); 413 } 414 } 415 416 static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 417 Xive2Eas *eas) 418 { 419 PnvXive2 *xive = PNV_XIVE2(xrtr); 420 421 if (pnv_xive2_block_id(xive) != blk) { 422 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 423 return -1; 424 } 425 426 return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas); 427 } 428 429 static uint32_t pnv_xive2_get_config(Xive2Router *xrtr) 430 { 431 PnvXive2 *xive = PNV_XIVE2(xrtr); 432 uint32_t cfg = 0; 433 434 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { 435 cfg |= XIVE2_GEN1_TIMA_OS; 436 } 437 438 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) { 439 cfg |= XIVE2_VP_SAVE_RESTORE; 440 } 441 442 return cfg; 443 } 444 445 static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu) 446 { 447 int pir = ppc_cpu_pir(cpu); 448 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); 449 uint64_t reg = fc < 8 ? TCTXT_EN0 : TCTXT_EN1; 450 uint32_t bit = pir & 0x3f; 451 452 return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit); 453 } 454 455 static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, 456 uint8_t nvt_blk, uint32_t nvt_idx, 457 bool cam_ignore, uint8_t priority, 458 uint32_t logic_serv, XiveTCTXMatch *match) 459 { 460 PnvXive2 *xive = PNV_XIVE2(xptr); 461 PnvChip *chip = xive->chip; 462 int count = 0; 463 int i, j; 464 bool gen1_tima_os = 465 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 466 467 for (i = 0; i < chip->nr_cores; i++) { 468 PnvCore *pc = chip->cores[i]; 469 CPUCore *cc = CPU_CORE(pc); 470 471 for (j = 0; j < cc->nr_threads; j++) { 472 PowerPCCPU *cpu = pc->threads[j]; 473 XiveTCTX *tctx; 474 int ring; 475 476 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 477 continue; 478 } 479 480 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 481 482 if (gen1_tima_os) { 483 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, 484 nvt_idx, cam_ignore, 485 logic_serv); 486 } else { 487 ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk, 488 nvt_idx, cam_ignore, 489 logic_serv); 490 } 491 492 /* 493 * Save the context and follow on to catch duplicates, 494 * that we don't support yet. 495 */ 496 if (ring != -1) { 497 if (match->tctx) { 498 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 499 "thread context NVT %x/%x\n", 500 nvt_blk, nvt_idx); 501 return false; 502 } 503 504 match->ring = ring; 505 match->tctx = tctx; 506 count++; 507 } 508 } 509 } 510 511 return count; 512 } 513 514 static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) 515 { 516 return pnv_xive2_block_id(PNV_XIVE2(xrtr)); 517 } 518 519 /* 520 * The TIMA MMIO space is shared among the chips and to identify the 521 * chip from which the access is being done, we extract the chip id 522 * from the PIR. 523 */ 524 static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu) 525 { 526 int pir = ppc_cpu_pir(cpu); 527 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; 528 PnvXive2 *xive = PNV_XIVE2(xptr); 529 530 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 531 xive2_error(xive, "IC: CPU %x is not enabled", pir); 532 } 533 return xive; 534 } 535 536 /* 537 * The internal sources of the interrupt controller have no knowledge 538 * of the XIVE2 chip on which they reside. Encode the block id in the 539 * source interrupt number before forwarding the source event 540 * notification to the Router. This is required on a multichip system. 541 */ 542 static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked) 543 { 544 PnvXive2 *xive = PNV_XIVE2(xn); 545 uint8_t blk = pnv_xive2_block_id(xive); 546 547 xive2_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked); 548 } 549 550 /* 551 * Set Translation Tables 552 * 553 * TODO add support for multiple sets 554 */ 555 static int pnv_xive2_stt_set_data(PnvXive2 *xive, uint64_t val) 556 { 557 uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]); 558 uint8_t entry = GETFIELD(CQ_TAR_ENTRY_SELECT, 559 xive->cq_regs[CQ_TAR >> 3]); 560 561 switch (tsel) { 562 case CQ_TAR_NVPG: 563 case CQ_TAR_ESB: 564 case CQ_TAR_END: 565 xive->tables[tsel][entry] = val; 566 break; 567 default: 568 xive2_error(xive, "IC: unsupported table %d", tsel); 569 return -1; 570 } 571 572 if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) { 573 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT, 574 xive->cq_regs[CQ_TAR >> 3], ++entry); 575 } 576 577 return 0; 578 } 579 /* 580 * Virtual Structure Tables (VST) configuration 581 */ 582 static void pnv_xive2_vst_set_exclusive(PnvXive2 *xive, uint8_t type, 583 uint8_t blk, uint64_t vsd) 584 { 585 Xive2EndSource *end_xsrc = &xive->end_source; 586 XiveSource *xsrc = &xive->ipi_source; 587 const XiveVstInfo *info = &vst_infos[type]; 588 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 589 uint64_t vst_tsize = 1ull << page_shift; 590 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 591 592 /* Basic checks */ 593 594 if (VSD_INDIRECT & vsd) { 595 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 596 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 597 page_shift); 598 return; 599 } 600 } 601 602 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 603 xive2_error(xive, "VST: %s table address 0x%"PRIx64 604 " is not aligned with page shift %d", 605 info->name, vst_addr, page_shift); 606 return; 607 } 608 609 /* Record the table configuration (in SRAM on HW) */ 610 xive->vsds[type][blk] = vsd; 611 612 /* Now tune the models with the configuration provided by the FW */ 613 614 switch (type) { 615 case VST_ESB: 616 /* 617 * Backing store pages for the source PQ bits. The model does 618 * not use these PQ bits backed in RAM because the XiveSource 619 * model has its own. 620 * 621 * If the table is direct, we can compute the number of PQ 622 * entries provisioned by FW (such as skiboot) and resize the 623 * ESB window accordingly. 624 */ 625 if (!(VSD_INDIRECT & vsd)) { 626 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 627 * (1ull << xsrc->esb_shift)); 628 } 629 630 memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio); 631 break; 632 633 case VST_EAS: /* Nothing to be done */ 634 break; 635 636 case VST_END: 637 /* 638 * Backing store pages for the END. 639 */ 640 if (!(VSD_INDIRECT & vsd)) { 641 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 642 * (1ull << end_xsrc->esb_shift)); 643 } 644 memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio); 645 break; 646 647 case VST_NVP: /* Not modeled */ 648 case VST_NVG: /* Not modeled */ 649 case VST_NVC: /* Not modeled */ 650 case VST_IC: /* Not modeled */ 651 case VST_SYNC: /* Not modeled */ 652 case VST_ERQ: /* Not modeled */ 653 break; 654 655 default: 656 g_assert_not_reached(); 657 } 658 } 659 660 /* 661 * Both PC and VC sub-engines are configured as each use the Virtual 662 * Structure Tables 663 */ 664 static void pnv_xive2_vst_set_data(PnvXive2 *xive, uint64_t vsd) 665 { 666 uint8_t mode = GETFIELD(VSD_MODE, vsd); 667 uint8_t type = GETFIELD(VC_VSD_TABLE_SELECT, 668 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 669 uint8_t blk = GETFIELD(VC_VSD_TABLE_ADDRESS, 670 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 671 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 672 673 if (type > VST_ERQ) { 674 xive2_error(xive, "VST: invalid table type %d", type); 675 return; 676 } 677 678 if (blk >= vst_infos[type].max_blocks) { 679 xive2_error(xive, "VST: invalid block id %d for" 680 " %s table", blk, vst_infos[type].name); 681 return; 682 } 683 684 if (!vst_addr) { 685 xive2_error(xive, "VST: invalid %s table address", 686 vst_infos[type].name); 687 return; 688 } 689 690 switch (mode) { 691 case VSD_MODE_FORWARD: 692 xive->vsds[type][blk] = vsd; 693 break; 694 695 case VSD_MODE_EXCLUSIVE: 696 pnv_xive2_vst_set_exclusive(xive, type, blk, vsd); 697 break; 698 699 default: 700 xive2_error(xive, "VST: unsupported table mode %d", mode); 701 return; 702 } 703 } 704 705 /* 706 * MMIO handlers 707 */ 708 709 710 /* 711 * IC BAR layout 712 * 713 * Page 0: Internal CQ register accesses (reads & writes) 714 * Page 1: Internal PC register accesses (reads & writes) 715 * Page 2: Internal VC register accesses (reads & writes) 716 * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes) 717 * Page 4: Notify Port page (writes only, w/data), 718 * Page 5: Reserved 719 * Page 6: Sync Poll page (writes only, dataless) 720 * Page 7: Sync Inject page (writes only, dataless) 721 * Page 8: LSI Trigger page (writes only, dataless) 722 * Page 9: LSI SB Management page (reads & writes dataless) 723 * Pages 10-255: Reserved 724 * Pages 256-383: Direct mapped Thread Context Area (reads & writes) 725 * covering the 128 threads in P10. 726 * Pages 384-511: Reserved 727 */ 728 typedef struct PnvXive2Region { 729 const char *name; 730 uint32_t pgoff; 731 uint32_t pgsize; 732 const MemoryRegionOps *ops; 733 } PnvXive2Region; 734 735 static const MemoryRegionOps pnv_xive2_ic_cq_ops; 736 static const MemoryRegionOps pnv_xive2_ic_pc_ops; 737 static const MemoryRegionOps pnv_xive2_ic_vc_ops; 738 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops; 739 static const MemoryRegionOps pnv_xive2_ic_notify_ops; 740 static const MemoryRegionOps pnv_xive2_ic_sync_ops; 741 static const MemoryRegionOps pnv_xive2_ic_lsi_ops; 742 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops; 743 744 /* 512 pages. 4K: 2M range, 64K: 32M range */ 745 static const PnvXive2Region pnv_xive2_ic_regions[] = { 746 { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops }, 747 { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops }, 748 { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops }, 749 { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops }, 750 { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops }, 751 /* page 5 reserved */ 752 { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops }, 753 { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops }, 754 /* pages 10-255 reserved */ 755 { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops }, 756 /* pages 384-511 reserved */ 757 }; 758 759 /* 760 * CQ operations 761 */ 762 763 static uint64_t pnv_xive2_ic_cq_read(void *opaque, hwaddr offset, 764 unsigned size) 765 { 766 PnvXive2 *xive = PNV_XIVE2(opaque); 767 uint32_t reg = offset >> 3; 768 uint64_t val = 0; 769 770 switch (offset) { 771 case CQ_XIVE_CAP: /* Set at reset */ 772 case CQ_XIVE_CFG: 773 val = xive->cq_regs[reg]; 774 break; 775 case CQ_MSGSND: /* TODO check the #cores of the machine */ 776 val = 0xffffffff00000000; 777 break; 778 case CQ_CFG_PB_GEN: 779 val = CQ_CFG_PB_GEN_PB_INIT; /* TODO: fix CQ_CFG_PB_GEN default value */ 780 break; 781 default: 782 xive2_error(xive, "CQ: invalid read @%"HWADDR_PRIx, offset); 783 } 784 785 return val; 786 } 787 788 static uint64_t pnv_xive2_bar_size(uint64_t val) 789 { 790 return 1ull << (GETFIELD(CQ_BAR_RANGE, val) + 24); 791 } 792 793 static void pnv_xive2_ic_cq_write(void *opaque, hwaddr offset, 794 uint64_t val, unsigned size) 795 { 796 PnvXive2 *xive = PNV_XIVE2(opaque); 797 MemoryRegion *sysmem = get_system_memory(); 798 uint32_t reg = offset >> 3; 799 int i; 800 801 switch (offset) { 802 case CQ_XIVE_CFG: 803 case CQ_RST_CTL: /* TODO: reset all BARs */ 804 break; 805 806 case CQ_IC_BAR: 807 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 808 if (!(val & CQ_IC_BAR_VALID)) { 809 xive->ic_base = 0; 810 if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) { 811 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 812 memory_region_del_subregion(&xive->ic_mmio, 813 &xive->ic_mmios[i]); 814 } 815 memory_region_del_subregion(sysmem, &xive->ic_mmio); 816 } 817 } else { 818 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 819 if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) { 820 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 821 memory_region_add_subregion(&xive->ic_mmio, 822 pnv_xive2_ic_regions[i].pgoff << xive->ic_shift, 823 &xive->ic_mmios[i]); 824 } 825 memory_region_add_subregion(sysmem, xive->ic_base, 826 &xive->ic_mmio); 827 } 828 } 829 break; 830 831 case CQ_TM_BAR: 832 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 833 if (!(val & CQ_TM_BAR_VALID)) { 834 xive->tm_base = 0; 835 if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) { 836 memory_region_del_subregion(sysmem, &xive->tm_mmio); 837 } 838 } else { 839 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 840 if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) { 841 memory_region_add_subregion(sysmem, xive->tm_base, 842 &xive->tm_mmio); 843 } 844 } 845 break; 846 847 case CQ_ESB_BAR: 848 xive->esb_shift = val & CQ_BAR_64K ? 16 : 12; 849 if (!(val & CQ_BAR_VALID)) { 850 xive->esb_base = 0; 851 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 852 memory_region_del_subregion(sysmem, &xive->esb_mmio); 853 } 854 } else { 855 xive->esb_base = val & CQ_BAR_ADDR; 856 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 857 memory_region_set_size(&xive->esb_mmio, 858 pnv_xive2_bar_size(val)); 859 memory_region_add_subregion(sysmem, xive->esb_base, 860 &xive->esb_mmio); 861 } 862 } 863 break; 864 865 case CQ_END_BAR: 866 xive->end_shift = val & CQ_BAR_64K ? 16 : 12; 867 if (!(val & CQ_BAR_VALID)) { 868 xive->end_base = 0; 869 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 870 memory_region_del_subregion(sysmem, &xive->end_mmio); 871 } 872 } else { 873 xive->end_base = val & CQ_BAR_ADDR; 874 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 875 memory_region_set_size(&xive->end_mmio, 876 pnv_xive2_bar_size(val)); 877 memory_region_add_subregion(sysmem, xive->end_base, 878 &xive->end_mmio); 879 } 880 } 881 break; 882 883 case CQ_NVC_BAR: 884 xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12; 885 if (!(val & CQ_BAR_VALID)) { 886 xive->nvc_base = 0; 887 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 888 memory_region_del_subregion(sysmem, &xive->nvc_mmio); 889 } 890 } else { 891 xive->nvc_base = val & CQ_BAR_ADDR; 892 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 893 memory_region_set_size(&xive->nvc_mmio, 894 pnv_xive2_bar_size(val)); 895 memory_region_add_subregion(sysmem, xive->nvc_base, 896 &xive->nvc_mmio); 897 } 898 } 899 break; 900 901 case CQ_NVPG_BAR: 902 xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12; 903 if (!(val & CQ_BAR_VALID)) { 904 xive->nvpg_base = 0; 905 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 906 memory_region_del_subregion(sysmem, &xive->nvpg_mmio); 907 } 908 } else { 909 xive->nvpg_base = val & CQ_BAR_ADDR; 910 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 911 memory_region_set_size(&xive->nvpg_mmio, 912 pnv_xive2_bar_size(val)); 913 memory_region_add_subregion(sysmem, xive->nvpg_base, 914 &xive->nvpg_mmio); 915 } 916 } 917 break; 918 919 case CQ_TAR: /* Set Translation Table Address */ 920 break; 921 case CQ_TDR: /* Set Translation Table Data */ 922 pnv_xive2_stt_set_data(xive, val); 923 break; 924 case CQ_FIRMASK_OR: /* FIR error reporting */ 925 break; 926 default: 927 xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset); 928 return; 929 } 930 931 xive->cq_regs[reg] = val; 932 } 933 934 static const MemoryRegionOps pnv_xive2_ic_cq_ops = { 935 .read = pnv_xive2_ic_cq_read, 936 .write = pnv_xive2_ic_cq_write, 937 .endianness = DEVICE_BIG_ENDIAN, 938 .valid = { 939 .min_access_size = 8, 940 .max_access_size = 8, 941 }, 942 .impl = { 943 .min_access_size = 8, 944 .max_access_size = 8, 945 }, 946 }; 947 948 static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, 949 unsigned size) 950 { 951 PnvXive2 *xive = PNV_XIVE2(opaque); 952 uint64_t val = 0; 953 uint32_t reg = offset >> 3; 954 955 switch (offset) { 956 /* 957 * VSD table settings. 958 */ 959 case VC_VSD_TABLE_ADDR: 960 case VC_VSD_TABLE_DATA: 961 val = xive->vc_regs[reg]; 962 break; 963 964 /* 965 * ESB cache updates (not modeled) 966 */ 967 case VC_ESBC_FLUSH_CTRL: 968 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID; 969 val = xive->vc_regs[reg]; 970 break; 971 972 /* 973 * EAS cache updates (not modeled) 974 */ 975 case VC_EASC_FLUSH_CTRL: 976 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID; 977 val = xive->vc_regs[reg]; 978 break; 979 980 /* 981 * END cache updates 982 */ 983 case VC_ENDC_WATCH0_SPEC: 984 xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT); 985 val = xive->vc_regs[reg]; 986 break; 987 988 case VC_ENDC_WATCH0_DATA0: 989 /* 990 * Load DATA registers from cache with data requested by the 991 * SPEC register 992 */ 993 pnv_xive2_end_cache_load(xive); 994 val = xive->vc_regs[reg]; 995 break; 996 997 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 998 val = xive->vc_regs[reg]; 999 break; 1000 1001 case VC_ENDC_FLUSH_CTRL: 1002 xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID; 1003 val = xive->vc_regs[reg]; 1004 break; 1005 1006 /* 1007 * Indirect invalidation 1008 */ 1009 case VC_AT_MACRO_KILL_MASK: 1010 val = xive->vc_regs[reg]; 1011 break; 1012 1013 case VC_AT_MACRO_KILL: 1014 xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID; 1015 val = xive->vc_regs[reg]; 1016 break; 1017 1018 /* 1019 * Interrupt fifo overflow in memory backing store (Not modeled) 1020 */ 1021 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1022 val = xive->vc_regs[reg]; 1023 break; 1024 1025 /* 1026 * Synchronisation 1027 */ 1028 case VC_ENDC_SYNC_DONE: 1029 val = VC_ENDC_SYNC_POLL_DONE; 1030 break; 1031 default: 1032 xive2_error(xive, "VC: invalid read @%"HWADDR_PRIx, offset); 1033 } 1034 1035 return val; 1036 } 1037 1038 static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, 1039 uint64_t val, unsigned size) 1040 { 1041 PnvXive2 *xive = PNV_XIVE2(opaque); 1042 uint32_t reg = offset >> 3; 1043 1044 switch (offset) { 1045 /* 1046 * VSD table settings. 1047 */ 1048 case VC_VSD_TABLE_ADDR: 1049 break; 1050 case VC_VSD_TABLE_DATA: 1051 pnv_xive2_vst_set_data(xive, val); 1052 break; 1053 1054 /* 1055 * ESB cache updates (not modeled) 1056 */ 1057 /* case VC_ESBC_FLUSH_CTRL: */ 1058 case VC_ESBC_FLUSH_POLL: 1059 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; 1060 /* ESB update */ 1061 break; 1062 1063 /* 1064 * EAS cache updates (not modeled) 1065 */ 1066 /* case VC_EASC_FLUSH_CTRL: */ 1067 case VC_EASC_FLUSH_POLL: 1068 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; 1069 /* EAS update */ 1070 break; 1071 1072 /* 1073 * END cache updates 1074 */ 1075 case VC_ENDC_WATCH0_SPEC: 1076 val &= ~VC_ENDC_WATCH_CONFLICT; /* HW will set this bit */ 1077 break; 1078 1079 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1080 break; 1081 case VC_ENDC_WATCH0_DATA0: 1082 /* writing to DATA0 triggers the cache write */ 1083 xive->vc_regs[reg] = val; 1084 pnv_xive2_end_update(xive); 1085 break; 1086 1087 1088 /* case VC_ENDC_FLUSH_CTRL: */ 1089 case VC_ENDC_FLUSH_POLL: 1090 xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; 1091 break; 1092 1093 /* 1094 * Indirect invalidation 1095 */ 1096 case VC_AT_MACRO_KILL: 1097 case VC_AT_MACRO_KILL_MASK: 1098 break; 1099 1100 /* 1101 * Interrupt fifo overflow in memory backing store (Not modeled) 1102 */ 1103 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1104 break; 1105 1106 /* 1107 * Synchronisation 1108 */ 1109 case VC_ENDC_SYNC_DONE: 1110 break; 1111 1112 default: 1113 xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset); 1114 return; 1115 } 1116 1117 xive->vc_regs[reg] = val; 1118 } 1119 1120 static const MemoryRegionOps pnv_xive2_ic_vc_ops = { 1121 .read = pnv_xive2_ic_vc_read, 1122 .write = pnv_xive2_ic_vc_write, 1123 .endianness = DEVICE_BIG_ENDIAN, 1124 .valid = { 1125 .min_access_size = 8, 1126 .max_access_size = 8, 1127 }, 1128 .impl = { 1129 .min_access_size = 8, 1130 .max_access_size = 8, 1131 }, 1132 }; 1133 1134 static uint64_t pnv_xive2_ic_pc_read(void *opaque, hwaddr offset, 1135 unsigned size) 1136 { 1137 PnvXive2 *xive = PNV_XIVE2(opaque); 1138 uint64_t val = -1; 1139 uint32_t reg = offset >> 3; 1140 1141 switch (offset) { 1142 /* 1143 * VSD table settings. 1144 */ 1145 case PC_VSD_TABLE_ADDR: 1146 case PC_VSD_TABLE_DATA: 1147 val = xive->pc_regs[reg]; 1148 break; 1149 1150 /* 1151 * cache updates 1152 */ 1153 case PC_NXC_WATCH0_SPEC: 1154 xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT); 1155 val = xive->pc_regs[reg]; 1156 break; 1157 1158 case PC_NXC_WATCH0_DATA0: 1159 /* 1160 * Load DATA registers from cache with data requested by the 1161 * SPEC register 1162 */ 1163 pnv_xive2_nvp_cache_load(xive); 1164 val = xive->pc_regs[reg]; 1165 break; 1166 1167 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1168 val = xive->pc_regs[reg]; 1169 break; 1170 1171 case PC_NXC_FLUSH_CTRL: 1172 xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID; 1173 val = xive->pc_regs[reg]; 1174 break; 1175 1176 /* 1177 * Indirect invalidation 1178 */ 1179 case PC_AT_KILL: 1180 xive->pc_regs[reg] &= ~PC_AT_KILL_VALID; 1181 val = xive->pc_regs[reg]; 1182 break; 1183 1184 default: 1185 xive2_error(xive, "PC: invalid read @%"HWADDR_PRIx, offset); 1186 } 1187 1188 return val; 1189 } 1190 1191 static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset, 1192 uint64_t val, unsigned size) 1193 { 1194 PnvXive2 *xive = PNV_XIVE2(opaque); 1195 uint32_t reg = offset >> 3; 1196 1197 switch (offset) { 1198 1199 /* 1200 * VSD table settings. Only taken into account in the VC 1201 * sub-engine because the Xive2Router model combines both VC and PC 1202 * sub-engines 1203 */ 1204 case PC_VSD_TABLE_ADDR: 1205 case PC_VSD_TABLE_DATA: 1206 break; 1207 1208 /* 1209 * cache updates 1210 */ 1211 case PC_NXC_WATCH0_SPEC: 1212 val &= ~PC_NXC_WATCH_CONFLICT; /* HW will set this bit */ 1213 break; 1214 1215 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1216 break; 1217 case PC_NXC_WATCH0_DATA0: 1218 /* writing to DATA0 triggers the cache write */ 1219 xive->pc_regs[reg] = val; 1220 pnv_xive2_nvp_update(xive); 1221 break; 1222 1223 /* case PC_NXC_FLUSH_CTRL: */ 1224 case PC_NXC_FLUSH_POLL: 1225 xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; 1226 break; 1227 1228 /* 1229 * Indirect invalidation 1230 */ 1231 case PC_AT_KILL: 1232 case PC_AT_KILL_MASK: 1233 break; 1234 1235 default: 1236 xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset); 1237 return; 1238 } 1239 1240 xive->pc_regs[reg] = val; 1241 } 1242 1243 static const MemoryRegionOps pnv_xive2_ic_pc_ops = { 1244 .read = pnv_xive2_ic_pc_read, 1245 .write = pnv_xive2_ic_pc_write, 1246 .endianness = DEVICE_BIG_ENDIAN, 1247 .valid = { 1248 .min_access_size = 8, 1249 .max_access_size = 8, 1250 }, 1251 .impl = { 1252 .min_access_size = 8, 1253 .max_access_size = 8, 1254 }, 1255 }; 1256 1257 1258 static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset, 1259 unsigned size) 1260 { 1261 PnvXive2 *xive = PNV_XIVE2(opaque); 1262 uint64_t val = -1; 1263 uint32_t reg = offset >> 3; 1264 1265 switch (offset) { 1266 /* 1267 * XIVE2 hardware thread enablement 1268 */ 1269 case TCTXT_EN0: 1270 case TCTXT_EN1: 1271 val = xive->tctxt_regs[reg]; 1272 break; 1273 1274 case TCTXT_EN0_SET: 1275 case TCTXT_EN0_RESET: 1276 val = xive->tctxt_regs[TCTXT_EN0 >> 3]; 1277 break; 1278 case TCTXT_EN1_SET: 1279 case TCTXT_EN1_RESET: 1280 val = xive->tctxt_regs[TCTXT_EN1 >> 3]; 1281 break; 1282 default: 1283 xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); 1284 } 1285 1286 return val; 1287 } 1288 1289 static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, 1290 uint64_t val, unsigned size) 1291 { 1292 PnvXive2 *xive = PNV_XIVE2(opaque); 1293 uint32_t reg = offset >> 3; 1294 1295 switch (offset) { 1296 /* 1297 * XIVE2 hardware thread enablement 1298 */ 1299 case TCTXT_EN0: /* Physical Thread Enable */ 1300 case TCTXT_EN1: /* Physical Thread Enable (fused core) */ 1301 break; 1302 1303 case TCTXT_EN0_SET: 1304 xive->tctxt_regs[TCTXT_EN0 >> 3] |= val; 1305 break; 1306 case TCTXT_EN1_SET: 1307 xive->tctxt_regs[TCTXT_EN1 >> 3] |= val; 1308 break; 1309 case TCTXT_EN0_RESET: 1310 xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val; 1311 break; 1312 case TCTXT_EN1_RESET: 1313 xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; 1314 break; 1315 1316 default: 1317 xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); 1318 return; 1319 } 1320 1321 xive->pc_regs[reg] = val; 1322 } 1323 1324 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = { 1325 .read = pnv_xive2_ic_tctxt_read, 1326 .write = pnv_xive2_ic_tctxt_write, 1327 .endianness = DEVICE_BIG_ENDIAN, 1328 .valid = { 1329 .min_access_size = 8, 1330 .max_access_size = 8, 1331 }, 1332 .impl = { 1333 .min_access_size = 8, 1334 .max_access_size = 8, 1335 }, 1336 }; 1337 1338 /* 1339 * Redirect XSCOM to MMIO handlers 1340 */ 1341 static uint64_t pnv_xive2_xscom_read(void *opaque, hwaddr offset, 1342 unsigned size) 1343 { 1344 PnvXive2 *xive = PNV_XIVE2(opaque); 1345 uint64_t val = -1; 1346 uint32_t xscom_reg = offset >> 3; 1347 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1348 1349 switch (xscom_reg) { 1350 case 0x000 ... 0x0FF: 1351 val = pnv_xive2_ic_cq_read(opaque, mmio_offset, size); 1352 break; 1353 case 0x100 ... 0x1FF: 1354 val = pnv_xive2_ic_vc_read(opaque, mmio_offset, size); 1355 break; 1356 case 0x200 ... 0x2FF: 1357 val = pnv_xive2_ic_pc_read(opaque, mmio_offset, size); 1358 break; 1359 case 0x300 ... 0x3FF: 1360 val = pnv_xive2_ic_tctxt_read(opaque, mmio_offset, size); 1361 break; 1362 default: 1363 xive2_error(xive, "XSCOM: invalid read @%"HWADDR_PRIx, offset); 1364 } 1365 1366 return val; 1367 } 1368 1369 static void pnv_xive2_xscom_write(void *opaque, hwaddr offset, 1370 uint64_t val, unsigned size) 1371 { 1372 PnvXive2 *xive = PNV_XIVE2(opaque); 1373 uint32_t xscom_reg = offset >> 3; 1374 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1375 1376 switch (xscom_reg) { 1377 case 0x000 ... 0x0FF: 1378 pnv_xive2_ic_cq_write(opaque, mmio_offset, val, size); 1379 break; 1380 case 0x100 ... 0x1FF: 1381 pnv_xive2_ic_vc_write(opaque, mmio_offset, val, size); 1382 break; 1383 case 0x200 ... 0x2FF: 1384 pnv_xive2_ic_pc_write(opaque, mmio_offset, val, size); 1385 break; 1386 case 0x300 ... 0x3FF: 1387 pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size); 1388 break; 1389 default: 1390 xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset); 1391 } 1392 } 1393 1394 static const MemoryRegionOps pnv_xive2_xscom_ops = { 1395 .read = pnv_xive2_xscom_read, 1396 .write = pnv_xive2_xscom_write, 1397 .endianness = DEVICE_BIG_ENDIAN, 1398 .valid = { 1399 .min_access_size = 8, 1400 .max_access_size = 8, 1401 }, 1402 .impl = { 1403 .min_access_size = 8, 1404 .max_access_size = 8, 1405 }, 1406 }; 1407 1408 /* 1409 * Notify port page. The layout is compatible between 4K and 64K pages : 1410 * 1411 * Page 1 Notify page (writes only) 1412 * 0x000 - 0x7FF IPI interrupt (NPU) 1413 * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB) 1414 */ 1415 1416 static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr, 1417 uint64_t val) 1418 { 1419 uint8_t blk; 1420 uint32_t idx; 1421 1422 if (val & XIVE_TRIGGER_END) { 1423 xive2_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1424 addr, val); 1425 return; 1426 } 1427 1428 /* 1429 * Forward the source event notification directly to the Router. 1430 * The source interrupt number should already be correctly encoded 1431 * with the chip block id by the sending device (PHB, PSI). 1432 */ 1433 blk = XIVE_EAS_BLOCK(val); 1434 idx = XIVE_EAS_INDEX(val); 1435 1436 xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx), 1437 !!(val & XIVE_TRIGGER_PQ)); 1438 } 1439 1440 static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset, 1441 uint64_t val, unsigned size) 1442 { 1443 PnvXive2 *xive = PNV_XIVE2(opaque); 1444 1445 /* VC: IPI triggers */ 1446 switch (offset) { 1447 case 0x000 ... 0x7FF: 1448 /* TODO: check IPI notify sub-page routing */ 1449 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1450 break; 1451 1452 /* VC: HW triggers */ 1453 case 0x800 ... 0xFFF: 1454 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1455 break; 1456 1457 default: 1458 xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset); 1459 } 1460 } 1461 1462 static uint64_t pnv_xive2_ic_notify_read(void *opaque, hwaddr offset, 1463 unsigned size) 1464 { 1465 PnvXive2 *xive = PNV_XIVE2(opaque); 1466 1467 /* loads are invalid */ 1468 xive2_error(xive, "NOTIFY: invalid read @%"HWADDR_PRIx, offset); 1469 return -1; 1470 } 1471 1472 static const MemoryRegionOps pnv_xive2_ic_notify_ops = { 1473 .read = pnv_xive2_ic_notify_read, 1474 .write = pnv_xive2_ic_notify_write, 1475 .endianness = DEVICE_BIG_ENDIAN, 1476 .valid = { 1477 .min_access_size = 8, 1478 .max_access_size = 8, 1479 }, 1480 .impl = { 1481 .min_access_size = 8, 1482 .max_access_size = 8, 1483 }, 1484 }; 1485 1486 static uint64_t pnv_xive2_ic_lsi_read(void *opaque, hwaddr offset, 1487 unsigned size) 1488 { 1489 PnvXive2 *xive = PNV_XIVE2(opaque); 1490 1491 xive2_error(xive, "LSI: invalid read @%"HWADDR_PRIx, offset); 1492 return -1; 1493 } 1494 1495 static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset, 1496 uint64_t val, unsigned size) 1497 { 1498 PnvXive2 *xive = PNV_XIVE2(opaque); 1499 1500 xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset); 1501 } 1502 1503 static const MemoryRegionOps pnv_xive2_ic_lsi_ops = { 1504 .read = pnv_xive2_ic_lsi_read, 1505 .write = pnv_xive2_ic_lsi_write, 1506 .endianness = DEVICE_BIG_ENDIAN, 1507 .valid = { 1508 .min_access_size = 8, 1509 .max_access_size = 8, 1510 }, 1511 .impl = { 1512 .min_access_size = 8, 1513 .max_access_size = 8, 1514 }, 1515 }; 1516 1517 /* 1518 * Sync MMIO page (write only) 1519 */ 1520 #define PNV_XIVE2_SYNC_IPI 0x000 1521 #define PNV_XIVE2_SYNC_HW 0x080 1522 #define PNV_XIVE2_SYNC_NxC 0x100 1523 #define PNV_XIVE2_SYNC_INT 0x180 1524 #define PNV_XIVE2_SYNC_OS_ESC 0x200 1525 #define PNV_XIVE2_SYNC_POOL_ESC 0x280 1526 #define PNV_XIVE2_SYNC_HARD_ESC 0x300 1527 1528 static uint64_t pnv_xive2_ic_sync_read(void *opaque, hwaddr offset, 1529 unsigned size) 1530 { 1531 PnvXive2 *xive = PNV_XIVE2(opaque); 1532 1533 /* loads are invalid */ 1534 xive2_error(xive, "SYNC: invalid read @%"HWADDR_PRIx, offset); 1535 return -1; 1536 } 1537 1538 static void pnv_xive2_ic_sync_write(void *opaque, hwaddr offset, 1539 uint64_t val, unsigned size) 1540 { 1541 PnvXive2 *xive = PNV_XIVE2(opaque); 1542 1543 switch (offset) { 1544 case PNV_XIVE2_SYNC_IPI: 1545 case PNV_XIVE2_SYNC_HW: 1546 case PNV_XIVE2_SYNC_NxC: 1547 case PNV_XIVE2_SYNC_INT: 1548 case PNV_XIVE2_SYNC_OS_ESC: 1549 case PNV_XIVE2_SYNC_POOL_ESC: 1550 case PNV_XIVE2_SYNC_HARD_ESC: 1551 break; 1552 default: 1553 xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset); 1554 } 1555 } 1556 1557 static const MemoryRegionOps pnv_xive2_ic_sync_ops = { 1558 .read = pnv_xive2_ic_sync_read, 1559 .write = pnv_xive2_ic_sync_write, 1560 .endianness = DEVICE_BIG_ENDIAN, 1561 .valid = { 1562 .min_access_size = 8, 1563 .max_access_size = 8, 1564 }, 1565 .impl = { 1566 .min_access_size = 8, 1567 .max_access_size = 8, 1568 }, 1569 }; 1570 1571 /* 1572 * When the TM direct pages of the IC controller are accessed, the 1573 * target HW thread is deduced from the page offset. 1574 */ 1575 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) 1576 { 1577 PnvChip *chip = xive->chip; 1578 PowerPCCPU *cpu = NULL; 1579 1580 cpu = pnv_chip_find_cpu(chip, pir); 1581 if (!cpu) { 1582 xive2_error(xive, "IC: invalid PIR %x for indirect access", pir); 1583 return NULL; 1584 } 1585 1586 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 1587 xive2_error(xive, "IC: CPU %x is not enabled", pir); 1588 } 1589 1590 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1591 } 1592 1593 static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset, 1594 unsigned size) 1595 { 1596 PnvXive2 *xive = PNV_XIVE2(opaque); 1597 uint32_t pir = offset >> xive->ic_shift; 1598 XiveTCTX *tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1599 uint64_t val = -1; 1600 1601 if (tctx) { 1602 val = xive_tctx_tm_read(NULL, tctx, offset, size); 1603 } 1604 1605 return val; 1606 } 1607 1608 static void pnv_xive2_ic_tm_indirect_write(void *opaque, hwaddr offset, 1609 uint64_t val, unsigned size) 1610 { 1611 PnvXive2 *xive = PNV_XIVE2(opaque); 1612 uint32_t pir = offset >> xive->ic_shift; 1613 XiveTCTX *tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1614 1615 if (tctx) { 1616 xive_tctx_tm_write(NULL, tctx, offset, val, size); 1617 } 1618 } 1619 1620 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = { 1621 .read = pnv_xive2_ic_tm_indirect_read, 1622 .write = pnv_xive2_ic_tm_indirect_write, 1623 .endianness = DEVICE_BIG_ENDIAN, 1624 .valid = { 1625 .min_access_size = 8, 1626 .max_access_size = 8, 1627 }, 1628 .impl = { 1629 .min_access_size = 8, 1630 .max_access_size = 8, 1631 }, 1632 }; 1633 1634 /* 1635 * TIMA ops 1636 */ 1637 1638 /* 1639 * Special TIMA offsets to handle accesses in a POWER10 way. 1640 * 1641 * Only the CAM line updates done by the hypervisor should be handled 1642 * specifically. 1643 */ 1644 #define HV_PAGE_OFFSET (XIVE_TM_HV_PAGE << TM_SHIFT) 1645 #define HV_PUSH_OS_CTX_OFFSET (HV_PAGE_OFFSET | (TM_QW1_OS + TM_WORD2)) 1646 #define HV_PULL_OS_CTX_OFFSET (HV_PAGE_OFFSET | TM_SPC_PULL_OS_CTX) 1647 1648 static void pnv_xive2_tm_write(void *opaque, hwaddr offset, 1649 uint64_t value, unsigned size) 1650 { 1651 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1652 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1653 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1654 XivePresenter *xptr = XIVE_PRESENTER(xive); 1655 bool gen1_tima_os = 1656 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 1657 1658 /* TODO: should we switch the TM ops table instead ? */ 1659 if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) { 1660 xive2_tm_push_os_ctx(xptr, tctx, offset, value, size); 1661 return; 1662 } 1663 1664 /* Other TM ops are the same as XIVE1 */ 1665 xive_tctx_tm_write(xptr, tctx, offset, value, size); 1666 } 1667 1668 static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) 1669 { 1670 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1671 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1672 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1673 XivePresenter *xptr = XIVE_PRESENTER(xive); 1674 bool gen1_tima_os = 1675 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 1676 1677 /* TODO: should we switch the TM ops table instead ? */ 1678 if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) { 1679 return xive2_tm_pull_os_ctx(xptr, tctx, offset, size); 1680 } 1681 1682 /* Other TM ops are the same as XIVE1 */ 1683 return xive_tctx_tm_read(xptr, tctx, offset, size); 1684 } 1685 1686 static const MemoryRegionOps pnv_xive2_tm_ops = { 1687 .read = pnv_xive2_tm_read, 1688 .write = pnv_xive2_tm_write, 1689 .endianness = DEVICE_BIG_ENDIAN, 1690 .valid = { 1691 .min_access_size = 1, 1692 .max_access_size = 8, 1693 }, 1694 .impl = { 1695 .min_access_size = 1, 1696 .max_access_size = 8, 1697 }, 1698 }; 1699 1700 static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset, 1701 unsigned size) 1702 { 1703 PnvXive2 *xive = PNV_XIVE2(opaque); 1704 1705 xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset); 1706 return -1; 1707 } 1708 1709 static void pnv_xive2_nvc_write(void *opaque, hwaddr offset, 1710 uint64_t val, unsigned size) 1711 { 1712 PnvXive2 *xive = PNV_XIVE2(opaque); 1713 1714 xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset); 1715 } 1716 1717 static const MemoryRegionOps pnv_xive2_nvc_ops = { 1718 .read = pnv_xive2_nvc_read, 1719 .write = pnv_xive2_nvc_write, 1720 .endianness = DEVICE_BIG_ENDIAN, 1721 .valid = { 1722 .min_access_size = 8, 1723 .max_access_size = 8, 1724 }, 1725 .impl = { 1726 .min_access_size = 8, 1727 .max_access_size = 8, 1728 }, 1729 }; 1730 1731 static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset, 1732 unsigned size) 1733 { 1734 PnvXive2 *xive = PNV_XIVE2(opaque); 1735 1736 xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset); 1737 return -1; 1738 } 1739 1740 static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset, 1741 uint64_t val, unsigned size) 1742 { 1743 PnvXive2 *xive = PNV_XIVE2(opaque); 1744 1745 xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset); 1746 } 1747 1748 static const MemoryRegionOps pnv_xive2_nvpg_ops = { 1749 .read = pnv_xive2_nvpg_read, 1750 .write = pnv_xive2_nvpg_write, 1751 .endianness = DEVICE_BIG_ENDIAN, 1752 .valid = { 1753 .min_access_size = 8, 1754 .max_access_size = 8, 1755 }, 1756 .impl = { 1757 .min_access_size = 8, 1758 .max_access_size = 8, 1759 }, 1760 }; 1761 1762 /* 1763 * POWER10 default capabilities: 0x2000120076f000FC 1764 */ 1765 #define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC 1766 1767 /* 1768 * POWER10 default configuration: 0x0030000033000000 1769 * 1770 * 8bits thread id was dropped for P10 1771 */ 1772 #define PNV_XIVE2_CONFIGURATION 0x0030000033000000 1773 1774 static void pnv_xive2_reset(void *dev) 1775 { 1776 PnvXive2 *xive = PNV_XIVE2(dev); 1777 XiveSource *xsrc = &xive->ipi_source; 1778 Xive2EndSource *end_xsrc = &xive->end_source; 1779 1780 xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities; 1781 xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config; 1782 1783 /* HW hardwires the #Topology of the chip in the block field */ 1784 xive->cq_regs[CQ_XIVE_CFG >> 3] |= 1785 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id); 1786 1787 /* Set default page size to 64k */ 1788 xive->ic_shift = xive->esb_shift = xive->end_shift = 16; 1789 xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16; 1790 1791 /* Clear source MMIOs */ 1792 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 1793 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); 1794 } 1795 1796 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 1797 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); 1798 } 1799 } 1800 1801 /* 1802 * Maximum number of IRQs and ENDs supported by HW. Will be tuned by 1803 * software. 1804 */ 1805 #define PNV_XIVE2_NR_IRQS (PNV10_XIVE2_ESB_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1806 #define PNV_XIVE2_NR_ENDS (PNV10_XIVE2_END_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1807 1808 static void pnv_xive2_realize(DeviceState *dev, Error **errp) 1809 { 1810 PnvXive2 *xive = PNV_XIVE2(dev); 1811 PnvXive2Class *pxc = PNV_XIVE2_GET_CLASS(dev); 1812 XiveSource *xsrc = &xive->ipi_source; 1813 Xive2EndSource *end_xsrc = &xive->end_source; 1814 Error *local_err = NULL; 1815 int i; 1816 1817 pxc->parent_realize(dev, &local_err); 1818 if (local_err) { 1819 error_propagate(errp, local_err); 1820 return; 1821 } 1822 1823 assert(xive->chip); 1824 1825 /* 1826 * The XiveSource and Xive2EndSource objects are realized with the 1827 * maximum allowed HW configuration. The ESB MMIO regions will be 1828 * resized dynamically when the controller is configured by the FW 1829 * to limit accesses to resources not provisioned. 1830 */ 1831 object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI, 1832 &error_fatal); 1833 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS, 1834 &error_fatal); 1835 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), 1836 &error_fatal); 1837 qdev_realize(DEVICE(xsrc), NULL, &local_err); 1838 if (local_err) { 1839 error_propagate(errp, local_err); 1840 return; 1841 } 1842 1843 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS, 1844 &error_fatal); 1845 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 1846 &error_abort); 1847 qdev_realize(DEVICE(end_xsrc), NULL, &local_err); 1848 if (local_err) { 1849 error_propagate(errp, local_err); 1850 return; 1851 } 1852 1853 /* XSCOM region, used for initial configuration of the BARs */ 1854 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), 1855 &pnv_xive2_xscom_ops, xive, "xscom-xive", 1856 PNV10_XSCOM_XIVE2_SIZE << 3); 1857 1858 /* Interrupt controller MMIO regions */ 1859 xive->ic_shift = 16; 1860 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 1861 PNV10_XIVE2_IC_SIZE); 1862 1863 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 1864 memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev), 1865 pnv_xive2_ic_regions[i].ops, xive, 1866 pnv_xive2_ic_regions[i].name, 1867 pnv_xive2_ic_regions[i].pgsize << xive->ic_shift); 1868 } 1869 1870 /* 1871 * VC MMIO regions. 1872 */ 1873 xive->esb_shift = 16; 1874 xive->end_shift = 16; 1875 memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb", 1876 PNV10_XIVE2_ESB_SIZE); 1877 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end", 1878 PNV10_XIVE2_END_SIZE); 1879 1880 /* Presenter Controller MMIO region (not modeled) */ 1881 xive->nvc_shift = 16; 1882 xive->nvpg_shift = 16; 1883 memory_region_init_io(&xive->nvc_mmio, OBJECT(dev), 1884 &pnv_xive2_nvc_ops, xive, 1885 "xive-nvc", PNV10_XIVE2_NVC_SIZE); 1886 1887 memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev), 1888 &pnv_xive2_nvpg_ops, xive, 1889 "xive-nvpg", PNV10_XIVE2_NVPG_SIZE); 1890 1891 /* Thread Interrupt Management Area (Direct) */ 1892 xive->tm_shift = 16; 1893 memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops, 1894 xive, "xive-tima", PNV10_XIVE2_TM_SIZE); 1895 1896 qemu_register_reset(pnv_xive2_reset, dev); 1897 } 1898 1899 static Property pnv_xive2_properties[] = { 1900 DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0), 1901 DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0), 1902 DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0), 1903 DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0), 1904 DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0), 1905 DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0), 1906 DEFINE_PROP_UINT64("capabilities", PnvXive2, capabilities, 1907 PNV_XIVE2_CAPABILITIES), 1908 DEFINE_PROP_UINT64("config", PnvXive2, config, 1909 PNV_XIVE2_CONFIGURATION), 1910 DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *), 1911 DEFINE_PROP_END_OF_LIST(), 1912 }; 1913 1914 static void pnv_xive2_instance_init(Object *obj) 1915 { 1916 PnvXive2 *xive = PNV_XIVE2(obj); 1917 1918 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 1919 TYPE_XIVE_SOURCE); 1920 object_initialize_child(obj, "end_source", &xive->end_source, 1921 TYPE_XIVE2_END_SOURCE); 1922 } 1923 1924 static int pnv_xive2_dt_xscom(PnvXScomInterface *dev, void *fdt, 1925 int xscom_offset) 1926 { 1927 const char compat_p10[] = "ibm,power10-xive-x"; 1928 char *name; 1929 int offset; 1930 uint32_t reg[] = { 1931 cpu_to_be32(PNV10_XSCOM_XIVE2_BASE), 1932 cpu_to_be32(PNV10_XSCOM_XIVE2_SIZE) 1933 }; 1934 1935 name = g_strdup_printf("xive@%x", PNV10_XSCOM_XIVE2_BASE); 1936 offset = fdt_add_subnode(fdt, xscom_offset, name); 1937 _FDT(offset); 1938 g_free(name); 1939 1940 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 1941 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, 1942 sizeof(compat_p10))); 1943 return 0; 1944 } 1945 1946 static void pnv_xive2_class_init(ObjectClass *klass, void *data) 1947 { 1948 DeviceClass *dc = DEVICE_CLASS(klass); 1949 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 1950 Xive2RouterClass *xrc = XIVE2_ROUTER_CLASS(klass); 1951 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1952 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 1953 PnvXive2Class *pxc = PNV_XIVE2_CLASS(klass); 1954 1955 xdc->dt_xscom = pnv_xive2_dt_xscom; 1956 1957 dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)"; 1958 device_class_set_parent_realize(dc, pnv_xive2_realize, 1959 &pxc->parent_realize); 1960 device_class_set_props(dc, pnv_xive2_properties); 1961 1962 xrc->get_eas = pnv_xive2_get_eas; 1963 xrc->get_pq = pnv_xive2_get_pq; 1964 xrc->set_pq = pnv_xive2_set_pq; 1965 xrc->get_end = pnv_xive2_get_end; 1966 xrc->write_end = pnv_xive2_write_end; 1967 xrc->get_nvp = pnv_xive2_get_nvp; 1968 xrc->write_nvp = pnv_xive2_write_nvp; 1969 xrc->get_config = pnv_xive2_get_config; 1970 xrc->get_block_id = pnv_xive2_get_block_id; 1971 1972 xnc->notify = pnv_xive2_notify; 1973 1974 xpc->match_nvt = pnv_xive2_match_nvt; 1975 }; 1976 1977 static const TypeInfo pnv_xive2_info = { 1978 .name = TYPE_PNV_XIVE2, 1979 .parent = TYPE_XIVE2_ROUTER, 1980 .instance_init = pnv_xive2_instance_init, 1981 .instance_size = sizeof(PnvXive2), 1982 .class_init = pnv_xive2_class_init, 1983 .class_size = sizeof(PnvXive2Class), 1984 .interfaces = (InterfaceInfo[]) { 1985 { TYPE_PNV_XSCOM_INTERFACE }, 1986 { } 1987 } 1988 }; 1989 1990 static void pnv_xive2_register_types(void) 1991 { 1992 type_register_static(&pnv_xive2_info); 1993 } 1994 1995 type_init(pnv_xive2_register_types) 1996 1997 static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, 1998 Monitor *mon) 1999 { 2000 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 2001 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 2002 2003 if (!xive2_nvp_is_valid(nvp)) { 2004 return; 2005 } 2006 2007 monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x", 2008 nvp_idx, eq_blk, eq_idx, 2009 xive_get_field32(NVP2_W2_IPB, nvp->w2)); 2010 /* 2011 * When the NVP is HW controlled, more fields are updated 2012 */ 2013 if (xive2_nvp_is_hw(nvp)) { 2014 monitor_printf(mon, " CPPR:%02x", 2015 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 2016 if (xive2_nvp_is_co(nvp)) { 2017 monitor_printf(mon, " CO:%04x", 2018 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 2019 } 2020 } 2021 monitor_printf(mon, "\n"); 2022 } 2023 2024 /* 2025 * If the table is direct, we can compute the number of PQ entries 2026 * provisioned by FW. 2027 */ 2028 static uint32_t pnv_xive2_nr_esbs(PnvXive2 *xive) 2029 { 2030 uint8_t blk = pnv_xive2_block_id(xive); 2031 uint64_t vsd = xive->vsds[VST_ESB][blk]; 2032 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 2033 2034 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 2035 } 2036 2037 /* 2038 * Compute the number of entries per indirect subpage. 2039 */ 2040 static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type) 2041 { 2042 uint8_t blk = pnv_xive2_block_id(xive); 2043 uint64_t vsd = xive->vsds[type][blk]; 2044 const XiveVstInfo *info = &vst_infos[type]; 2045 uint64_t vsd_addr; 2046 uint32_t page_shift; 2047 2048 /* For direct tables, fake a valid value */ 2049 if (!(VSD_INDIRECT & vsd)) { 2050 return 1; 2051 } 2052 2053 /* Get the page size of the indirect table. */ 2054 vsd_addr = vsd & VSD_ADDRESS_MASK; 2055 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 2056 2057 if (!(vsd & VSD_ADDRESS_MASK)) { 2058 #ifdef XIVE2_DEBUG 2059 xive2_error(xive, "VST: invalid %s entry!?", info->name); 2060 #endif 2061 return 0; 2062 } 2063 2064 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 2065 2066 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 2067 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 2068 page_shift); 2069 return 0; 2070 } 2071 2072 return (1ull << page_shift) / info->size; 2073 } 2074 2075 void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon) 2076 { 2077 Xive2Router *xrtr = XIVE2_ROUTER(xive); 2078 uint8_t blk = pnv_xive2_block_id(xive); 2079 uint8_t chip_id = xive->chip->chip_id; 2080 uint32_t srcno0 = XIVE_EAS(blk, 0); 2081 uint32_t nr_esbs = pnv_xive2_nr_esbs(xive); 2082 Xive2Eas eas; 2083 Xive2End end; 2084 Xive2Nvp nvp; 2085 int i; 2086 uint64_t xive_nvp_per_subpage; 2087 2088 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, 2089 srcno0 + nr_esbs - 1); 2090 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); 2091 2092 monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, 2093 srcno0 + nr_esbs - 1); 2094 for (i = 0; i < nr_esbs; i++) { 2095 if (xive2_router_get_eas(xrtr, blk, i, &eas)) { 2096 break; 2097 } 2098 if (!xive2_eas_is_masked(&eas)) { 2099 xive2_eas_pic_print_info(&eas, i, mon); 2100 } 2101 } 2102 2103 monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); 2104 i = 0; 2105 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2106 xive2_end_eas_pic_print_info(&end, i++, mon); 2107 } 2108 2109 monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); 2110 i = 0; 2111 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2112 xive2_end_pic_print_info(&end, i++, mon); 2113 } 2114 2115 monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk, 2116 0, XIVE2_NVP_COUNT - 1); 2117 xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); 2118 for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) { 2119 while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) { 2120 xive2_nvp_pic_print_info(&nvp, i++, mon); 2121 } 2122 } 2123 } 2124