1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "sysemu/cpus.h" 15 #include "sysemu/dma.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/pnv.h" 19 #include "hw/ppc/pnv_core.h" 20 #include "hw/ppc/pnv_xscom.h" 21 #include "hw/ppc/xive2.h" 22 #include "hw/ppc/pnv_xive.h" 23 #include "hw/ppc/xive_regs.h" 24 #include "hw/ppc/xive2_regs.h" 25 #include "hw/ppc/ppc.h" 26 #include "hw/qdev-properties.h" 27 #include "sysemu/reset.h" 28 29 #include <libfdt.h> 30 31 #include "pnv_xive2_regs.h" 32 33 #undef XIVE2_DEBUG 34 35 /* 36 * Virtual structures table (VST) 37 */ 38 #define SBE_PER_BYTE 4 39 40 typedef struct XiveVstInfo { 41 const char *name; 42 uint32_t size; 43 uint32_t max_blocks; 44 } XiveVstInfo; 45 46 static const XiveVstInfo vst_infos[] = { 47 48 [VST_EAS] = { "EAT", sizeof(Xive2Eas), 16 }, 49 [VST_ESB] = { "ESB", 1, 16 }, 50 [VST_END] = { "ENDT", sizeof(Xive2End), 16 }, 51 52 [VST_NVP] = { "NVPT", sizeof(Xive2Nvp), 16 }, 53 [VST_NVG] = { "NVGT", sizeof(Xive2Nvgc), 16 }, 54 [VST_NVC] = { "NVCT", sizeof(Xive2Nvgc), 16 }, 55 56 [VST_IC] = { "IC", 1 /* ? */ , 16 }, /* Topology # */ 57 [VST_SYNC] = { "SYNC", 1 /* ? */ , 16 }, /* Topology # */ 58 59 /* 60 * This table contains the backing store pages for the interrupt 61 * fifos of the VC sub-engine in case of overflow. 62 * 63 * 0 - IPI, 64 * 1 - HWD, 65 * 2 - NxC, 66 * 3 - INT, 67 * 4 - OS-Queue, 68 * 5 - Pool-Queue, 69 * 6 - Hard-Queue 70 */ 71 [VST_ERQ] = { "ERQ", 1, VC_QUEUE_COUNT }, 72 }; 73 74 #define xive2_error(xive, fmt, ...) \ 75 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 76 (xive)->chip->chip_id, ## __VA_ARGS__); 77 78 /* 79 * QEMU version of the GETFIELD/SETFIELD macros 80 * 81 * TODO: It might be better to use the existing extract64() and 82 * deposit64() but this means that all the register definitions will 83 * change and become incompatible with the ones found in skiboot. 84 * 85 * Keep it as it is for now until we find a common ground. 86 */ 87 static inline uint64_t GETFIELD(uint64_t mask, uint64_t word) 88 { 89 return (word & mask) >> ctz64(mask); 90 } 91 92 static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, 93 uint64_t value) 94 { 95 return (word & ~mask) | ((value << ctz64(mask)) & mask); 96 } 97 98 /* 99 * TODO: Document block id override 100 */ 101 static uint32_t pnv_xive2_block_id(PnvXive2 *xive) 102 { 103 uint8_t blk = xive->chip->chip_id; 104 uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3]; 105 106 if (cfg_val & CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE) { 107 blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val); 108 } 109 110 return blk; 111 } 112 113 /* 114 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 115 * of the chips is good enough. 116 * 117 * TODO: Block scope support 118 */ 119 static PnvXive2 *pnv_xive2_get_remote(uint8_t blk) 120 { 121 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 122 int i; 123 124 for (i = 0; i < pnv->num_chips; i++) { 125 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 126 PnvXive2 *xive = &chip10->xive; 127 128 if (pnv_xive2_block_id(xive) == blk) { 129 return xive; 130 } 131 } 132 return NULL; 133 } 134 135 /* 136 * VST accessors for ESB, EAT, ENDT, NVP 137 * 138 * Indirect VST tables are arrays of VSDs pointing to a page (of same 139 * size). Each page is a direct VST table. 140 */ 141 142 #define XIVE_VSD_SIZE 8 143 144 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 145 static uint64_t pnv_xive2_vst_page_size_allowed(uint32_t page_shift) 146 { 147 return page_shift == 12 || page_shift == 16 || 148 page_shift == 21 || page_shift == 24; 149 } 150 151 static uint64_t pnv_xive2_vst_addr_direct(PnvXive2 *xive, uint32_t type, 152 uint64_t vsd, uint32_t idx) 153 { 154 const XiveVstInfo *info = &vst_infos[type]; 155 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 156 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 157 uint32_t idx_max; 158 159 idx_max = vst_tsize / info->size - 1; 160 if (idx > idx_max) { 161 #ifdef XIVE2_DEBUG 162 xive2_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 163 info->name, idx, idx_max); 164 #endif 165 return 0; 166 } 167 168 return vst_addr + idx * info->size; 169 } 170 171 static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type, 172 uint64_t vsd, uint32_t idx) 173 { 174 const XiveVstInfo *info = &vst_infos[type]; 175 uint64_t vsd_addr; 176 uint32_t vsd_idx; 177 uint32_t page_shift; 178 uint32_t vst_per_page; 179 180 /* Get the page size of the indirect table. */ 181 vsd_addr = vsd & VSD_ADDRESS_MASK; 182 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 183 184 if (!(vsd & VSD_ADDRESS_MASK)) { 185 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 186 return 0; 187 } 188 189 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 190 191 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 192 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 193 page_shift); 194 return 0; 195 } 196 197 vst_per_page = (1ull << page_shift) / info->size; 198 vsd_idx = idx / vst_per_page; 199 200 /* Load the VSD we are looking for, if not already done */ 201 if (vsd_idx) { 202 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 203 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, 204 MEMTXATTRS_UNSPECIFIED); 205 206 if (!(vsd & VSD_ADDRESS_MASK)) { 207 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 208 return 0; 209 } 210 211 /* 212 * Check that the pages have a consistent size across the 213 * indirect table 214 */ 215 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 216 xive2_error(xive, "VST: %s entry %x indirect page size differ !?", 217 info->name, idx); 218 return 0; 219 } 220 } 221 222 return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 223 } 224 225 static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk, 226 uint32_t idx) 227 { 228 const XiveVstInfo *info = &vst_infos[type]; 229 uint64_t vsd; 230 231 if (blk >= info->max_blocks) { 232 xive2_error(xive, "VST: invalid block id %d for VST %s %d !?", 233 blk, info->name, idx); 234 return 0; 235 } 236 237 vsd = xive->vsds[type][blk]; 238 239 /* Remote VST access */ 240 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 241 xive = pnv_xive2_get_remote(blk); 242 243 return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0; 244 } 245 246 if (VSD_INDIRECT & vsd) { 247 return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx); 248 } 249 250 return pnv_xive2_vst_addr_direct(xive, type, vsd, idx); 251 } 252 253 static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk, 254 uint32_t idx, void *data) 255 { 256 const XiveVstInfo *info = &vst_infos[type]; 257 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 258 259 if (!addr) { 260 return -1; 261 } 262 263 cpu_physical_memory_read(addr, data, info->size); 264 return 0; 265 } 266 267 #define XIVE_VST_WORD_ALL -1 268 269 static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk, 270 uint32_t idx, void *data, uint32_t word_number) 271 { 272 const XiveVstInfo *info = &vst_infos[type]; 273 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 274 275 if (!addr) { 276 return -1; 277 } 278 279 if (word_number == XIVE_VST_WORD_ALL) { 280 cpu_physical_memory_write(addr, data, info->size); 281 } else { 282 cpu_physical_memory_write(addr + word_number * 4, 283 data + word_number * 4, 4); 284 } 285 return 0; 286 } 287 288 static int pnv_xive2_get_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 289 uint8_t *pq) 290 { 291 PnvXive2 *xive = PNV_XIVE2(xrtr); 292 293 if (pnv_xive2_block_id(xive) != blk) { 294 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 295 return -1; 296 } 297 298 *pq = xive_source_esb_get(&xive->ipi_source, idx); 299 return 0; 300 } 301 302 static int pnv_xive2_set_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 303 uint8_t *pq) 304 { 305 PnvXive2 *xive = PNV_XIVE2(xrtr); 306 307 if (pnv_xive2_block_id(xive) != blk) { 308 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 309 return -1; 310 } 311 312 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq); 313 return 0; 314 } 315 316 static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 317 Xive2End *end) 318 { 319 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_END, blk, idx, end); 320 } 321 322 static int pnv_xive2_write_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 323 Xive2End *end, uint8_t word_number) 324 { 325 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_END, blk, idx, end, 326 word_number); 327 } 328 329 static int pnv_xive2_end_update(PnvXive2 *xive) 330 { 331 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 332 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 333 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 334 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 335 int i; 336 uint64_t endc_watch[4]; 337 338 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 339 endc_watch[i] = 340 cpu_to_be64(xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i]); 341 } 342 343 return pnv_xive2_vst_write(xive, VST_END, blk, idx, endc_watch, 344 XIVE_VST_WORD_ALL); 345 } 346 347 static void pnv_xive2_end_cache_load(PnvXive2 *xive) 348 { 349 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 350 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 351 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 352 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 353 uint64_t endc_watch[4] = { 0 }; 354 int i; 355 356 if (pnv_xive2_vst_read(xive, VST_END, blk, idx, endc_watch)) { 357 xive2_error(xive, "VST: no END entry %x/%x !?", blk, idx); 358 } 359 360 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 361 xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i] = 362 be64_to_cpu(endc_watch[i]); 363 } 364 } 365 366 static int pnv_xive2_get_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 367 Xive2Nvp *nvp) 368 { 369 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp); 370 } 371 372 static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 373 Xive2Nvp *nvp, uint8_t word_number) 374 { 375 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp, 376 word_number); 377 } 378 379 static int pnv_xive2_nvp_update(PnvXive2 *xive) 380 { 381 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 382 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 383 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 384 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 385 int i; 386 uint64_t nxc_watch[4]; 387 388 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 389 nxc_watch[i] = 390 cpu_to_be64(xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i]); 391 } 392 393 return pnv_xive2_vst_write(xive, VST_NVP, blk, idx, nxc_watch, 394 XIVE_VST_WORD_ALL); 395 } 396 397 static void pnv_xive2_nvp_cache_load(PnvXive2 *xive) 398 { 399 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 400 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 401 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 402 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 403 uint64_t nxc_watch[4] = { 0 }; 404 int i; 405 406 if (pnv_xive2_vst_read(xive, VST_NVP, blk, idx, nxc_watch)) { 407 xive2_error(xive, "VST: no NVP entry %x/%x !?", blk, idx); 408 } 409 410 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 411 xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i] = 412 be64_to_cpu(nxc_watch[i]); 413 } 414 } 415 416 static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 417 Xive2Eas *eas) 418 { 419 PnvXive2 *xive = PNV_XIVE2(xrtr); 420 421 if (pnv_xive2_block_id(xive) != blk) { 422 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 423 return -1; 424 } 425 426 return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas); 427 } 428 429 static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu) 430 { 431 int pir = ppc_cpu_pir(cpu); 432 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); 433 uint64_t reg = fc < 8 ? TCTXT_EN0 : TCTXT_EN1; 434 uint32_t bit = pir & 0x3f; 435 436 return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit); 437 } 438 439 static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, 440 uint8_t nvt_blk, uint32_t nvt_idx, 441 bool cam_ignore, uint8_t priority, 442 uint32_t logic_serv, XiveTCTXMatch *match) 443 { 444 PnvXive2 *xive = PNV_XIVE2(xptr); 445 PnvChip *chip = xive->chip; 446 int count = 0; 447 int i, j; 448 449 for (i = 0; i < chip->nr_cores; i++) { 450 PnvCore *pc = chip->cores[i]; 451 CPUCore *cc = CPU_CORE(pc); 452 453 for (j = 0; j < cc->nr_threads; j++) { 454 PowerPCCPU *cpu = pc->threads[j]; 455 XiveTCTX *tctx; 456 int ring; 457 458 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 459 continue; 460 } 461 462 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 463 464 ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk, 465 nvt_idx, cam_ignore, 466 logic_serv); 467 468 /* 469 * Save the context and follow on to catch duplicates, 470 * that we don't support yet. 471 */ 472 if (ring != -1) { 473 if (match->tctx) { 474 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 475 "thread context NVT %x/%x\n", 476 nvt_blk, nvt_idx); 477 return false; 478 } 479 480 match->ring = ring; 481 match->tctx = tctx; 482 count++; 483 } 484 } 485 } 486 487 return count; 488 } 489 490 static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) 491 { 492 return pnv_xive2_block_id(PNV_XIVE2(xrtr)); 493 } 494 495 /* 496 * The TIMA MMIO space is shared among the chips and to identify the 497 * chip from which the access is being done, we extract the chip id 498 * from the PIR. 499 */ 500 static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu) 501 { 502 int pir = ppc_cpu_pir(cpu); 503 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; 504 PnvXive2 *xive = PNV_XIVE2(xptr); 505 506 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 507 xive2_error(xive, "IC: CPU %x is not enabled", pir); 508 } 509 return xive; 510 } 511 512 /* 513 * The internal sources of the interrupt controller have no knowledge 514 * of the XIVE2 chip on which they reside. Encode the block id in the 515 * source interrupt number before forwarding the source event 516 * notification to the Router. This is required on a multichip system. 517 */ 518 static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked) 519 { 520 PnvXive2 *xive = PNV_XIVE2(xn); 521 uint8_t blk = pnv_xive2_block_id(xive); 522 523 xive2_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked); 524 } 525 526 /* 527 * Set Translation Tables 528 * 529 * TODO add support for multiple sets 530 */ 531 static int pnv_xive2_stt_set_data(PnvXive2 *xive, uint64_t val) 532 { 533 uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]); 534 uint8_t entry = GETFIELD(CQ_TAR_ENTRY_SELECT, 535 xive->cq_regs[CQ_TAR >> 3]); 536 537 switch (tsel) { 538 case CQ_TAR_NVPG: 539 case CQ_TAR_ESB: 540 case CQ_TAR_END: 541 xive->tables[tsel][entry] = val; 542 break; 543 default: 544 xive2_error(xive, "IC: unsupported table %d", tsel); 545 return -1; 546 } 547 548 if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) { 549 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT, 550 xive->cq_regs[CQ_TAR >> 3], ++entry); 551 } 552 553 return 0; 554 } 555 /* 556 * Virtual Structure Tables (VST) configuration 557 */ 558 static void pnv_xive2_vst_set_exclusive(PnvXive2 *xive, uint8_t type, 559 uint8_t blk, uint64_t vsd) 560 { 561 Xive2EndSource *end_xsrc = &xive->end_source; 562 XiveSource *xsrc = &xive->ipi_source; 563 const XiveVstInfo *info = &vst_infos[type]; 564 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 565 uint64_t vst_tsize = 1ull << page_shift; 566 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 567 568 /* Basic checks */ 569 570 if (VSD_INDIRECT & vsd) { 571 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 572 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 573 page_shift); 574 return; 575 } 576 } 577 578 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 579 xive2_error(xive, "VST: %s table address 0x%"PRIx64 580 " is not aligned with page shift %d", 581 info->name, vst_addr, page_shift); 582 return; 583 } 584 585 /* Record the table configuration (in SRAM on HW) */ 586 xive->vsds[type][blk] = vsd; 587 588 /* Now tune the models with the configuration provided by the FW */ 589 590 switch (type) { 591 case VST_ESB: 592 /* 593 * Backing store pages for the source PQ bits. The model does 594 * not use these PQ bits backed in RAM because the XiveSource 595 * model has its own. 596 * 597 * If the table is direct, we can compute the number of PQ 598 * entries provisioned by FW (such as skiboot) and resize the 599 * ESB window accordingly. 600 */ 601 if (!(VSD_INDIRECT & vsd)) { 602 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 603 * (1ull << xsrc->esb_shift)); 604 } 605 606 memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio); 607 break; 608 609 case VST_EAS: /* Nothing to be done */ 610 break; 611 612 case VST_END: 613 /* 614 * Backing store pages for the END. 615 */ 616 if (!(VSD_INDIRECT & vsd)) { 617 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 618 * (1ull << end_xsrc->esb_shift)); 619 } 620 memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio); 621 break; 622 623 case VST_NVP: /* Not modeled */ 624 case VST_NVG: /* Not modeled */ 625 case VST_NVC: /* Not modeled */ 626 case VST_IC: /* Not modeled */ 627 case VST_SYNC: /* Not modeled */ 628 case VST_ERQ: /* Not modeled */ 629 break; 630 631 default: 632 g_assert_not_reached(); 633 } 634 } 635 636 /* 637 * Both PC and VC sub-engines are configured as each use the Virtual 638 * Structure Tables 639 */ 640 static void pnv_xive2_vst_set_data(PnvXive2 *xive, uint64_t vsd) 641 { 642 uint8_t mode = GETFIELD(VSD_MODE, vsd); 643 uint8_t type = GETFIELD(VC_VSD_TABLE_SELECT, 644 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 645 uint8_t blk = GETFIELD(VC_VSD_TABLE_ADDRESS, 646 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 647 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 648 649 if (type > VST_ERQ) { 650 xive2_error(xive, "VST: invalid table type %d", type); 651 return; 652 } 653 654 if (blk >= vst_infos[type].max_blocks) { 655 xive2_error(xive, "VST: invalid block id %d for" 656 " %s table", blk, vst_infos[type].name); 657 return; 658 } 659 660 if (!vst_addr) { 661 xive2_error(xive, "VST: invalid %s table address", 662 vst_infos[type].name); 663 return; 664 } 665 666 switch (mode) { 667 case VSD_MODE_FORWARD: 668 xive->vsds[type][blk] = vsd; 669 break; 670 671 case VSD_MODE_EXCLUSIVE: 672 pnv_xive2_vst_set_exclusive(xive, type, blk, vsd); 673 break; 674 675 default: 676 xive2_error(xive, "VST: unsupported table mode %d", mode); 677 return; 678 } 679 } 680 681 /* 682 * MMIO handlers 683 */ 684 685 686 /* 687 * IC BAR layout 688 * 689 * Page 0: Internal CQ register accesses (reads & writes) 690 * Page 1: Internal PC register accesses (reads & writes) 691 * Page 2: Internal VC register accesses (reads & writes) 692 * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes) 693 * Page 4: Notify Port page (writes only, w/data), 694 * Page 5: Reserved 695 * Page 6: Sync Poll page (writes only, dataless) 696 * Page 7: Sync Inject page (writes only, dataless) 697 * Page 8: LSI Trigger page (writes only, dataless) 698 * Page 9: LSI SB Management page (reads & writes dataless) 699 * Pages 10-255: Reserved 700 * Pages 256-383: Direct mapped Thread Context Area (reads & writes) 701 * covering the 128 threads in P10. 702 * Pages 384-511: Reserved 703 */ 704 typedef struct PnvXive2Region { 705 const char *name; 706 uint32_t pgoff; 707 uint32_t pgsize; 708 const MemoryRegionOps *ops; 709 } PnvXive2Region; 710 711 static const MemoryRegionOps pnv_xive2_ic_cq_ops; 712 static const MemoryRegionOps pnv_xive2_ic_pc_ops; 713 static const MemoryRegionOps pnv_xive2_ic_vc_ops; 714 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops; 715 static const MemoryRegionOps pnv_xive2_ic_notify_ops; 716 static const MemoryRegionOps pnv_xive2_ic_sync_ops; 717 static const MemoryRegionOps pnv_xive2_ic_lsi_ops; 718 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops; 719 720 /* 512 pages. 4K: 2M range, 64K: 32M range */ 721 static const PnvXive2Region pnv_xive2_ic_regions[] = { 722 { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops }, 723 { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops }, 724 { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops }, 725 { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops }, 726 { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops }, 727 /* page 5 reserved */ 728 { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops }, 729 { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops }, 730 /* pages 10-255 reserved */ 731 { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops }, 732 /* pages 384-511 reserved */ 733 }; 734 735 /* 736 * CQ operations 737 */ 738 739 static uint64_t pnv_xive2_ic_cq_read(void *opaque, hwaddr offset, 740 unsigned size) 741 { 742 PnvXive2 *xive = PNV_XIVE2(opaque); 743 uint32_t reg = offset >> 3; 744 uint64_t val = 0; 745 746 switch (offset) { 747 case CQ_XIVE_CAP: /* Set at reset */ 748 case CQ_XIVE_CFG: 749 val = xive->cq_regs[reg]; 750 break; 751 case CQ_MSGSND: /* TODO check the #cores of the machine */ 752 val = 0xffffffff00000000; 753 break; 754 case CQ_CFG_PB_GEN: 755 val = CQ_CFG_PB_GEN_PB_INIT; /* TODO: fix CQ_CFG_PB_GEN default value */ 756 break; 757 default: 758 xive2_error(xive, "CQ: invalid read @%"HWADDR_PRIx, offset); 759 } 760 761 return val; 762 } 763 764 static uint64_t pnv_xive2_bar_size(uint64_t val) 765 { 766 return 1ull << (GETFIELD(CQ_BAR_RANGE, val) + 24); 767 } 768 769 static void pnv_xive2_ic_cq_write(void *opaque, hwaddr offset, 770 uint64_t val, unsigned size) 771 { 772 PnvXive2 *xive = PNV_XIVE2(opaque); 773 MemoryRegion *sysmem = get_system_memory(); 774 uint32_t reg = offset >> 3; 775 int i; 776 777 switch (offset) { 778 case CQ_XIVE_CFG: 779 case CQ_RST_CTL: /* TODO: reset all BARs */ 780 break; 781 782 case CQ_IC_BAR: 783 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 784 if (!(val & CQ_IC_BAR_VALID)) { 785 xive->ic_base = 0; 786 if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) { 787 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 788 memory_region_del_subregion(&xive->ic_mmio, 789 &xive->ic_mmios[i]); 790 } 791 memory_region_del_subregion(sysmem, &xive->ic_mmio); 792 } 793 } else { 794 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 795 if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) { 796 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 797 memory_region_add_subregion(&xive->ic_mmio, 798 pnv_xive2_ic_regions[i].pgoff << xive->ic_shift, 799 &xive->ic_mmios[i]); 800 } 801 memory_region_add_subregion(sysmem, xive->ic_base, 802 &xive->ic_mmio); 803 } 804 } 805 break; 806 807 case CQ_TM_BAR: 808 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 809 if (!(val & CQ_TM_BAR_VALID)) { 810 xive->tm_base = 0; 811 if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) { 812 memory_region_del_subregion(sysmem, &xive->tm_mmio); 813 } 814 } else { 815 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 816 if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) { 817 memory_region_add_subregion(sysmem, xive->tm_base, 818 &xive->tm_mmio); 819 } 820 } 821 break; 822 823 case CQ_ESB_BAR: 824 xive->esb_shift = val & CQ_BAR_64K ? 16 : 12; 825 if (!(val & CQ_BAR_VALID)) { 826 xive->esb_base = 0; 827 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 828 memory_region_del_subregion(sysmem, &xive->esb_mmio); 829 } 830 } else { 831 xive->esb_base = val & CQ_BAR_ADDR; 832 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 833 memory_region_set_size(&xive->esb_mmio, 834 pnv_xive2_bar_size(val)); 835 memory_region_add_subregion(sysmem, xive->esb_base, 836 &xive->esb_mmio); 837 } 838 } 839 break; 840 841 case CQ_END_BAR: 842 xive->end_shift = val & CQ_BAR_64K ? 16 : 12; 843 if (!(val & CQ_BAR_VALID)) { 844 xive->end_base = 0; 845 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 846 memory_region_del_subregion(sysmem, &xive->end_mmio); 847 } 848 } else { 849 xive->end_base = val & CQ_BAR_ADDR; 850 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 851 memory_region_set_size(&xive->end_mmio, 852 pnv_xive2_bar_size(val)); 853 memory_region_add_subregion(sysmem, xive->end_base, 854 &xive->end_mmio); 855 } 856 } 857 break; 858 859 case CQ_NVC_BAR: 860 xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12; 861 if (!(val & CQ_BAR_VALID)) { 862 xive->nvc_base = 0; 863 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 864 memory_region_del_subregion(sysmem, &xive->nvc_mmio); 865 } 866 } else { 867 xive->nvc_base = val & CQ_BAR_ADDR; 868 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 869 memory_region_set_size(&xive->nvc_mmio, 870 pnv_xive2_bar_size(val)); 871 memory_region_add_subregion(sysmem, xive->nvc_base, 872 &xive->nvc_mmio); 873 } 874 } 875 break; 876 877 case CQ_NVPG_BAR: 878 xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12; 879 if (!(val & CQ_BAR_VALID)) { 880 xive->nvpg_base = 0; 881 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 882 memory_region_del_subregion(sysmem, &xive->nvpg_mmio); 883 } 884 } else { 885 xive->nvpg_base = val & CQ_BAR_ADDR; 886 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 887 memory_region_set_size(&xive->nvpg_mmio, 888 pnv_xive2_bar_size(val)); 889 memory_region_add_subregion(sysmem, xive->nvpg_base, 890 &xive->nvpg_mmio); 891 } 892 } 893 break; 894 895 case CQ_TAR: /* Set Translation Table Address */ 896 break; 897 case CQ_TDR: /* Set Translation Table Data */ 898 pnv_xive2_stt_set_data(xive, val); 899 break; 900 case CQ_FIRMASK_OR: /* FIR error reporting */ 901 break; 902 default: 903 xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset); 904 return; 905 } 906 907 xive->cq_regs[reg] = val; 908 } 909 910 static const MemoryRegionOps pnv_xive2_ic_cq_ops = { 911 .read = pnv_xive2_ic_cq_read, 912 .write = pnv_xive2_ic_cq_write, 913 .endianness = DEVICE_BIG_ENDIAN, 914 .valid = { 915 .min_access_size = 8, 916 .max_access_size = 8, 917 }, 918 .impl = { 919 .min_access_size = 8, 920 .max_access_size = 8, 921 }, 922 }; 923 924 static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, 925 unsigned size) 926 { 927 PnvXive2 *xive = PNV_XIVE2(opaque); 928 uint64_t val = 0; 929 uint32_t reg = offset >> 3; 930 931 switch (offset) { 932 /* 933 * VSD table settings. 934 */ 935 case VC_VSD_TABLE_ADDR: 936 case VC_VSD_TABLE_DATA: 937 val = xive->vc_regs[reg]; 938 break; 939 940 /* 941 * ESB cache updates (not modeled) 942 */ 943 case VC_ESBC_FLUSH_CTRL: 944 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID; 945 val = xive->vc_regs[reg]; 946 break; 947 948 /* 949 * EAS cache updates (not modeled) 950 */ 951 case VC_EASC_FLUSH_CTRL: 952 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID; 953 val = xive->vc_regs[reg]; 954 break; 955 956 /* 957 * END cache updates 958 */ 959 case VC_ENDC_WATCH0_SPEC: 960 xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT); 961 val = xive->vc_regs[reg]; 962 break; 963 964 case VC_ENDC_WATCH0_DATA0: 965 /* 966 * Load DATA registers from cache with data requested by the 967 * SPEC register 968 */ 969 pnv_xive2_end_cache_load(xive); 970 val = xive->vc_regs[reg]; 971 break; 972 973 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 974 val = xive->vc_regs[reg]; 975 break; 976 977 case VC_ENDC_FLUSH_CTRL: 978 xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID; 979 val = xive->vc_regs[reg]; 980 break; 981 982 /* 983 * Indirect invalidation 984 */ 985 case VC_AT_MACRO_KILL_MASK: 986 val = xive->vc_regs[reg]; 987 break; 988 989 case VC_AT_MACRO_KILL: 990 xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID; 991 val = xive->vc_regs[reg]; 992 break; 993 994 /* 995 * Interrupt fifo overflow in memory backing store (Not modeled) 996 */ 997 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 998 val = xive->vc_regs[reg]; 999 break; 1000 1001 /* 1002 * Synchronisation 1003 */ 1004 case VC_ENDC_SYNC_DONE: 1005 val = VC_ENDC_SYNC_POLL_DONE; 1006 break; 1007 default: 1008 xive2_error(xive, "VC: invalid read @%"HWADDR_PRIx, offset); 1009 } 1010 1011 return val; 1012 } 1013 1014 static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, 1015 uint64_t val, unsigned size) 1016 { 1017 PnvXive2 *xive = PNV_XIVE2(opaque); 1018 uint32_t reg = offset >> 3; 1019 1020 switch (offset) { 1021 /* 1022 * VSD table settings. 1023 */ 1024 case VC_VSD_TABLE_ADDR: 1025 break; 1026 case VC_VSD_TABLE_DATA: 1027 pnv_xive2_vst_set_data(xive, val); 1028 break; 1029 1030 /* 1031 * ESB cache updates (not modeled) 1032 */ 1033 /* case VC_ESBC_FLUSH_CTRL: */ 1034 case VC_ESBC_FLUSH_POLL: 1035 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; 1036 /* ESB update */ 1037 break; 1038 1039 /* 1040 * EAS cache updates (not modeled) 1041 */ 1042 /* case VC_EASC_FLUSH_CTRL: */ 1043 case VC_EASC_FLUSH_POLL: 1044 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; 1045 /* EAS update */ 1046 break; 1047 1048 /* 1049 * END cache updates 1050 */ 1051 case VC_ENDC_WATCH0_SPEC: 1052 val &= ~VC_ENDC_WATCH_CONFLICT; /* HW will set this bit */ 1053 break; 1054 1055 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1056 break; 1057 case VC_ENDC_WATCH0_DATA0: 1058 /* writing to DATA0 triggers the cache write */ 1059 xive->vc_regs[reg] = val; 1060 pnv_xive2_end_update(xive); 1061 break; 1062 1063 1064 /* case VC_ENDC_FLUSH_CTRL: */ 1065 case VC_ENDC_FLUSH_POLL: 1066 xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; 1067 break; 1068 1069 /* 1070 * Indirect invalidation 1071 */ 1072 case VC_AT_MACRO_KILL: 1073 case VC_AT_MACRO_KILL_MASK: 1074 break; 1075 1076 /* 1077 * Interrupt fifo overflow in memory backing store (Not modeled) 1078 */ 1079 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1080 break; 1081 1082 /* 1083 * Synchronisation 1084 */ 1085 case VC_ENDC_SYNC_DONE: 1086 break; 1087 1088 default: 1089 xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset); 1090 return; 1091 } 1092 1093 xive->vc_regs[reg] = val; 1094 } 1095 1096 static const MemoryRegionOps pnv_xive2_ic_vc_ops = { 1097 .read = pnv_xive2_ic_vc_read, 1098 .write = pnv_xive2_ic_vc_write, 1099 .endianness = DEVICE_BIG_ENDIAN, 1100 .valid = { 1101 .min_access_size = 8, 1102 .max_access_size = 8, 1103 }, 1104 .impl = { 1105 .min_access_size = 8, 1106 .max_access_size = 8, 1107 }, 1108 }; 1109 1110 static uint64_t pnv_xive2_ic_pc_read(void *opaque, hwaddr offset, 1111 unsigned size) 1112 { 1113 PnvXive2 *xive = PNV_XIVE2(opaque); 1114 uint64_t val = -1; 1115 uint32_t reg = offset >> 3; 1116 1117 switch (offset) { 1118 /* 1119 * VSD table settings. 1120 */ 1121 case PC_VSD_TABLE_ADDR: 1122 case PC_VSD_TABLE_DATA: 1123 val = xive->pc_regs[reg]; 1124 break; 1125 1126 /* 1127 * cache updates 1128 */ 1129 case PC_NXC_WATCH0_SPEC: 1130 xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT); 1131 val = xive->pc_regs[reg]; 1132 break; 1133 1134 case PC_NXC_WATCH0_DATA0: 1135 /* 1136 * Load DATA registers from cache with data requested by the 1137 * SPEC register 1138 */ 1139 pnv_xive2_nvp_cache_load(xive); 1140 val = xive->pc_regs[reg]; 1141 break; 1142 1143 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1144 val = xive->pc_regs[reg]; 1145 break; 1146 1147 case PC_NXC_FLUSH_CTRL: 1148 xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID; 1149 val = xive->pc_regs[reg]; 1150 break; 1151 1152 /* 1153 * Indirect invalidation 1154 */ 1155 case PC_AT_KILL: 1156 xive->pc_regs[reg] &= ~PC_AT_KILL_VALID; 1157 val = xive->pc_regs[reg]; 1158 break; 1159 1160 default: 1161 xive2_error(xive, "PC: invalid read @%"HWADDR_PRIx, offset); 1162 } 1163 1164 return val; 1165 } 1166 1167 static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset, 1168 uint64_t val, unsigned size) 1169 { 1170 PnvXive2 *xive = PNV_XIVE2(opaque); 1171 uint32_t reg = offset >> 3; 1172 1173 switch (offset) { 1174 1175 /* 1176 * VSD table settings. Only taken into account in the VC 1177 * sub-engine because the Xive2Router model combines both VC and PC 1178 * sub-engines 1179 */ 1180 case PC_VSD_TABLE_ADDR: 1181 case PC_VSD_TABLE_DATA: 1182 break; 1183 1184 /* 1185 * cache updates 1186 */ 1187 case PC_NXC_WATCH0_SPEC: 1188 val &= ~PC_NXC_WATCH_CONFLICT; /* HW will set this bit */ 1189 break; 1190 1191 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1192 break; 1193 case PC_NXC_WATCH0_DATA0: 1194 /* writing to DATA0 triggers the cache write */ 1195 xive->pc_regs[reg] = val; 1196 pnv_xive2_nvp_update(xive); 1197 break; 1198 1199 /* case PC_NXC_FLUSH_CTRL: */ 1200 case PC_NXC_FLUSH_POLL: 1201 xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; 1202 break; 1203 1204 /* 1205 * Indirect invalidation 1206 */ 1207 case PC_AT_KILL: 1208 case PC_AT_KILL_MASK: 1209 break; 1210 1211 default: 1212 xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset); 1213 return; 1214 } 1215 1216 xive->pc_regs[reg] = val; 1217 } 1218 1219 static const MemoryRegionOps pnv_xive2_ic_pc_ops = { 1220 .read = pnv_xive2_ic_pc_read, 1221 .write = pnv_xive2_ic_pc_write, 1222 .endianness = DEVICE_BIG_ENDIAN, 1223 .valid = { 1224 .min_access_size = 8, 1225 .max_access_size = 8, 1226 }, 1227 .impl = { 1228 .min_access_size = 8, 1229 .max_access_size = 8, 1230 }, 1231 }; 1232 1233 1234 static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset, 1235 unsigned size) 1236 { 1237 PnvXive2 *xive = PNV_XIVE2(opaque); 1238 uint64_t val = -1; 1239 uint32_t reg = offset >> 3; 1240 1241 switch (offset) { 1242 /* 1243 * XIVE2 hardware thread enablement 1244 */ 1245 case TCTXT_EN0: 1246 case TCTXT_EN1: 1247 val = xive->tctxt_regs[reg]; 1248 break; 1249 1250 case TCTXT_EN0_SET: 1251 case TCTXT_EN0_RESET: 1252 val = xive->tctxt_regs[TCTXT_EN0 >> 3]; 1253 break; 1254 case TCTXT_EN1_SET: 1255 case TCTXT_EN1_RESET: 1256 val = xive->tctxt_regs[TCTXT_EN1 >> 3]; 1257 break; 1258 default: 1259 xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); 1260 } 1261 1262 return val; 1263 } 1264 1265 static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, 1266 uint64_t val, unsigned size) 1267 { 1268 PnvXive2 *xive = PNV_XIVE2(opaque); 1269 uint32_t reg = offset >> 3; 1270 1271 switch (offset) { 1272 /* 1273 * XIVE2 hardware thread enablement 1274 */ 1275 case TCTXT_EN0: /* Physical Thread Enable */ 1276 case TCTXT_EN1: /* Physical Thread Enable (fused core) */ 1277 break; 1278 1279 case TCTXT_EN0_SET: 1280 xive->tctxt_regs[TCTXT_EN0 >> 3] |= val; 1281 break; 1282 case TCTXT_EN1_SET: 1283 xive->tctxt_regs[TCTXT_EN1 >> 3] |= val; 1284 break; 1285 case TCTXT_EN0_RESET: 1286 xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val; 1287 break; 1288 case TCTXT_EN1_RESET: 1289 xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; 1290 break; 1291 1292 default: 1293 xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); 1294 return; 1295 } 1296 1297 xive->pc_regs[reg] = val; 1298 } 1299 1300 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = { 1301 .read = pnv_xive2_ic_tctxt_read, 1302 .write = pnv_xive2_ic_tctxt_write, 1303 .endianness = DEVICE_BIG_ENDIAN, 1304 .valid = { 1305 .min_access_size = 8, 1306 .max_access_size = 8, 1307 }, 1308 .impl = { 1309 .min_access_size = 8, 1310 .max_access_size = 8, 1311 }, 1312 }; 1313 1314 /* 1315 * Redirect XSCOM to MMIO handlers 1316 */ 1317 static uint64_t pnv_xive2_xscom_read(void *opaque, hwaddr offset, 1318 unsigned size) 1319 { 1320 PnvXive2 *xive = PNV_XIVE2(opaque); 1321 uint64_t val = -1; 1322 uint32_t xscom_reg = offset >> 3; 1323 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1324 1325 switch (xscom_reg) { 1326 case 0x000 ... 0x0FF: 1327 val = pnv_xive2_ic_cq_read(opaque, mmio_offset, size); 1328 break; 1329 case 0x100 ... 0x1FF: 1330 val = pnv_xive2_ic_vc_read(opaque, mmio_offset, size); 1331 break; 1332 case 0x200 ... 0x2FF: 1333 val = pnv_xive2_ic_pc_read(opaque, mmio_offset, size); 1334 break; 1335 case 0x300 ... 0x3FF: 1336 val = pnv_xive2_ic_tctxt_read(opaque, mmio_offset, size); 1337 break; 1338 default: 1339 xive2_error(xive, "XSCOM: invalid read @%"HWADDR_PRIx, offset); 1340 } 1341 1342 return val; 1343 } 1344 1345 static void pnv_xive2_xscom_write(void *opaque, hwaddr offset, 1346 uint64_t val, unsigned size) 1347 { 1348 PnvXive2 *xive = PNV_XIVE2(opaque); 1349 uint32_t xscom_reg = offset >> 3; 1350 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1351 1352 switch (xscom_reg) { 1353 case 0x000 ... 0x0FF: 1354 pnv_xive2_ic_cq_write(opaque, mmio_offset, val, size); 1355 break; 1356 case 0x100 ... 0x1FF: 1357 pnv_xive2_ic_vc_write(opaque, mmio_offset, val, size); 1358 break; 1359 case 0x200 ... 0x2FF: 1360 pnv_xive2_ic_pc_write(opaque, mmio_offset, val, size); 1361 break; 1362 case 0x300 ... 0x3FF: 1363 pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size); 1364 break; 1365 default: 1366 xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset); 1367 } 1368 } 1369 1370 static const MemoryRegionOps pnv_xive2_xscom_ops = { 1371 .read = pnv_xive2_xscom_read, 1372 .write = pnv_xive2_xscom_write, 1373 .endianness = DEVICE_BIG_ENDIAN, 1374 .valid = { 1375 .min_access_size = 8, 1376 .max_access_size = 8, 1377 }, 1378 .impl = { 1379 .min_access_size = 8, 1380 .max_access_size = 8, 1381 }, 1382 }; 1383 1384 /* 1385 * Notify port page. The layout is compatible between 4K and 64K pages : 1386 * 1387 * Page 1 Notify page (writes only) 1388 * 0x000 - 0x7FF IPI interrupt (NPU) 1389 * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB) 1390 */ 1391 1392 static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr, 1393 uint64_t val) 1394 { 1395 uint8_t blk; 1396 uint32_t idx; 1397 1398 if (val & XIVE_TRIGGER_END) { 1399 xive2_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1400 addr, val); 1401 return; 1402 } 1403 1404 /* 1405 * Forward the source event notification directly to the Router. 1406 * The source interrupt number should already be correctly encoded 1407 * with the chip block id by the sending device (PHB, PSI). 1408 */ 1409 blk = XIVE_EAS_BLOCK(val); 1410 idx = XIVE_EAS_INDEX(val); 1411 1412 xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx), 1413 !!(val & XIVE_TRIGGER_PQ)); 1414 } 1415 1416 static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset, 1417 uint64_t val, unsigned size) 1418 { 1419 PnvXive2 *xive = PNV_XIVE2(opaque); 1420 1421 /* VC: IPI triggers */ 1422 switch (offset) { 1423 case 0x000 ... 0x7FF: 1424 /* TODO: check IPI notify sub-page routing */ 1425 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1426 break; 1427 1428 /* VC: HW triggers */ 1429 case 0x800 ... 0xFFF: 1430 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1431 break; 1432 1433 default: 1434 xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset); 1435 } 1436 } 1437 1438 static uint64_t pnv_xive2_ic_notify_read(void *opaque, hwaddr offset, 1439 unsigned size) 1440 { 1441 PnvXive2 *xive = PNV_XIVE2(opaque); 1442 1443 /* loads are invalid */ 1444 xive2_error(xive, "NOTIFY: invalid read @%"HWADDR_PRIx, offset); 1445 return -1; 1446 } 1447 1448 static const MemoryRegionOps pnv_xive2_ic_notify_ops = { 1449 .read = pnv_xive2_ic_notify_read, 1450 .write = pnv_xive2_ic_notify_write, 1451 .endianness = DEVICE_BIG_ENDIAN, 1452 .valid = { 1453 .min_access_size = 8, 1454 .max_access_size = 8, 1455 }, 1456 .impl = { 1457 .min_access_size = 8, 1458 .max_access_size = 8, 1459 }, 1460 }; 1461 1462 static uint64_t pnv_xive2_ic_lsi_read(void *opaque, hwaddr offset, 1463 unsigned size) 1464 { 1465 PnvXive2 *xive = PNV_XIVE2(opaque); 1466 1467 xive2_error(xive, "LSI: invalid read @%"HWADDR_PRIx, offset); 1468 return -1; 1469 } 1470 1471 static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset, 1472 uint64_t val, unsigned size) 1473 { 1474 PnvXive2 *xive = PNV_XIVE2(opaque); 1475 1476 xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset); 1477 } 1478 1479 static const MemoryRegionOps pnv_xive2_ic_lsi_ops = { 1480 .read = pnv_xive2_ic_lsi_read, 1481 .write = pnv_xive2_ic_lsi_write, 1482 .endianness = DEVICE_BIG_ENDIAN, 1483 .valid = { 1484 .min_access_size = 8, 1485 .max_access_size = 8, 1486 }, 1487 .impl = { 1488 .min_access_size = 8, 1489 .max_access_size = 8, 1490 }, 1491 }; 1492 1493 /* 1494 * Sync MMIO page (write only) 1495 */ 1496 #define PNV_XIVE2_SYNC_IPI 0x000 1497 #define PNV_XIVE2_SYNC_HW 0x080 1498 #define PNV_XIVE2_SYNC_NxC 0x100 1499 #define PNV_XIVE2_SYNC_INT 0x180 1500 #define PNV_XIVE2_SYNC_OS_ESC 0x200 1501 #define PNV_XIVE2_SYNC_POOL_ESC 0x280 1502 #define PNV_XIVE2_SYNC_HARD_ESC 0x300 1503 1504 static uint64_t pnv_xive2_ic_sync_read(void *opaque, hwaddr offset, 1505 unsigned size) 1506 { 1507 PnvXive2 *xive = PNV_XIVE2(opaque); 1508 1509 /* loads are invalid */ 1510 xive2_error(xive, "SYNC: invalid read @%"HWADDR_PRIx, offset); 1511 return -1; 1512 } 1513 1514 static void pnv_xive2_ic_sync_write(void *opaque, hwaddr offset, 1515 uint64_t val, unsigned size) 1516 { 1517 PnvXive2 *xive = PNV_XIVE2(opaque); 1518 1519 switch (offset) { 1520 case PNV_XIVE2_SYNC_IPI: 1521 case PNV_XIVE2_SYNC_HW: 1522 case PNV_XIVE2_SYNC_NxC: 1523 case PNV_XIVE2_SYNC_INT: 1524 case PNV_XIVE2_SYNC_OS_ESC: 1525 case PNV_XIVE2_SYNC_POOL_ESC: 1526 case PNV_XIVE2_SYNC_HARD_ESC: 1527 break; 1528 default: 1529 xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset); 1530 } 1531 } 1532 1533 static const MemoryRegionOps pnv_xive2_ic_sync_ops = { 1534 .read = pnv_xive2_ic_sync_read, 1535 .write = pnv_xive2_ic_sync_write, 1536 .endianness = DEVICE_BIG_ENDIAN, 1537 .valid = { 1538 .min_access_size = 8, 1539 .max_access_size = 8, 1540 }, 1541 .impl = { 1542 .min_access_size = 8, 1543 .max_access_size = 8, 1544 }, 1545 }; 1546 1547 /* 1548 * When the TM direct pages of the IC controller are accessed, the 1549 * target HW thread is deduced from the page offset. 1550 */ 1551 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) 1552 { 1553 PnvChip *chip = xive->chip; 1554 PowerPCCPU *cpu = NULL; 1555 1556 cpu = pnv_chip_find_cpu(chip, pir); 1557 if (!cpu) { 1558 xive2_error(xive, "IC: invalid PIR %x for indirect access", pir); 1559 return NULL; 1560 } 1561 1562 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 1563 xive2_error(xive, "IC: CPU %x is not enabled", pir); 1564 } 1565 1566 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1567 } 1568 1569 static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset, 1570 unsigned size) 1571 { 1572 PnvXive2 *xive = PNV_XIVE2(opaque); 1573 uint32_t pir = offset >> xive->ic_shift; 1574 XiveTCTX *tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1575 uint64_t val = -1; 1576 1577 if (tctx) { 1578 val = xive_tctx_tm_read(NULL, tctx, offset, size); 1579 } 1580 1581 return val; 1582 } 1583 1584 static void pnv_xive2_ic_tm_indirect_write(void *opaque, hwaddr offset, 1585 uint64_t val, unsigned size) 1586 { 1587 PnvXive2 *xive = PNV_XIVE2(opaque); 1588 uint32_t pir = offset >> xive->ic_shift; 1589 XiveTCTX *tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1590 1591 if (tctx) { 1592 xive_tctx_tm_write(NULL, tctx, offset, val, size); 1593 } 1594 } 1595 1596 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = { 1597 .read = pnv_xive2_ic_tm_indirect_read, 1598 .write = pnv_xive2_ic_tm_indirect_write, 1599 .endianness = DEVICE_BIG_ENDIAN, 1600 .valid = { 1601 .min_access_size = 8, 1602 .max_access_size = 8, 1603 }, 1604 .impl = { 1605 .min_access_size = 8, 1606 .max_access_size = 8, 1607 }, 1608 }; 1609 1610 /* 1611 * TIMA ops 1612 */ 1613 1614 static void pnv_xive2_tm_write(void *opaque, hwaddr offset, 1615 uint64_t value, unsigned size) 1616 { 1617 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1618 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1619 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1620 1621 /* Other TM ops are the same as XIVE1 */ 1622 xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size); 1623 } 1624 1625 static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) 1626 { 1627 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1628 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1629 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1630 1631 /* Other TM ops are the same as XIVE1 */ 1632 return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size); 1633 } 1634 1635 static const MemoryRegionOps pnv_xive2_tm_ops = { 1636 .read = pnv_xive2_tm_read, 1637 .write = pnv_xive2_tm_write, 1638 .endianness = DEVICE_BIG_ENDIAN, 1639 .valid = { 1640 .min_access_size = 1, 1641 .max_access_size = 8, 1642 }, 1643 .impl = { 1644 .min_access_size = 1, 1645 .max_access_size = 8, 1646 }, 1647 }; 1648 1649 static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset, 1650 unsigned size) 1651 { 1652 PnvXive2 *xive = PNV_XIVE2(opaque); 1653 1654 xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset); 1655 return -1; 1656 } 1657 1658 static void pnv_xive2_nvc_write(void *opaque, hwaddr offset, 1659 uint64_t val, unsigned size) 1660 { 1661 PnvXive2 *xive = PNV_XIVE2(opaque); 1662 1663 xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset); 1664 } 1665 1666 static const MemoryRegionOps pnv_xive2_nvc_ops = { 1667 .read = pnv_xive2_nvc_read, 1668 .write = pnv_xive2_nvc_write, 1669 .endianness = DEVICE_BIG_ENDIAN, 1670 .valid = { 1671 .min_access_size = 8, 1672 .max_access_size = 8, 1673 }, 1674 .impl = { 1675 .min_access_size = 8, 1676 .max_access_size = 8, 1677 }, 1678 }; 1679 1680 static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset, 1681 unsigned size) 1682 { 1683 PnvXive2 *xive = PNV_XIVE2(opaque); 1684 1685 xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset); 1686 return -1; 1687 } 1688 1689 static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset, 1690 uint64_t val, unsigned size) 1691 { 1692 PnvXive2 *xive = PNV_XIVE2(opaque); 1693 1694 xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset); 1695 } 1696 1697 static const MemoryRegionOps pnv_xive2_nvpg_ops = { 1698 .read = pnv_xive2_nvpg_read, 1699 .write = pnv_xive2_nvpg_write, 1700 .endianness = DEVICE_BIG_ENDIAN, 1701 .valid = { 1702 .min_access_size = 8, 1703 .max_access_size = 8, 1704 }, 1705 .impl = { 1706 .min_access_size = 8, 1707 .max_access_size = 8, 1708 }, 1709 }; 1710 1711 /* 1712 * POWER10 default capabilities: 0x2000120076f000FC 1713 */ 1714 #define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC 1715 1716 /* 1717 * POWER10 default configuration: 0x0030000033000000 1718 * 1719 * 8bits thread id was dropped for P10 1720 */ 1721 #define PNV_XIVE2_CONFIGURATION 0x0030000033000000 1722 1723 static void pnv_xive2_reset(void *dev) 1724 { 1725 PnvXive2 *xive = PNV_XIVE2(dev); 1726 XiveSource *xsrc = &xive->ipi_source; 1727 Xive2EndSource *end_xsrc = &xive->end_source; 1728 1729 xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities; 1730 xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config; 1731 1732 /* HW hardwires the #Topology of the chip in the block field */ 1733 xive->cq_regs[CQ_XIVE_CFG >> 3] |= 1734 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id); 1735 1736 /* Set default page size to 64k */ 1737 xive->ic_shift = xive->esb_shift = xive->end_shift = 16; 1738 xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16; 1739 1740 /* Clear source MMIOs */ 1741 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 1742 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); 1743 } 1744 1745 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 1746 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); 1747 } 1748 } 1749 1750 /* 1751 * Maximum number of IRQs and ENDs supported by HW. Will be tuned by 1752 * software. 1753 */ 1754 #define PNV_XIVE2_NR_IRQS (PNV10_XIVE2_ESB_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1755 #define PNV_XIVE2_NR_ENDS (PNV10_XIVE2_END_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1756 1757 static void pnv_xive2_realize(DeviceState *dev, Error **errp) 1758 { 1759 PnvXive2 *xive = PNV_XIVE2(dev); 1760 PnvXive2Class *pxc = PNV_XIVE2_GET_CLASS(dev); 1761 XiveSource *xsrc = &xive->ipi_source; 1762 Xive2EndSource *end_xsrc = &xive->end_source; 1763 Error *local_err = NULL; 1764 int i; 1765 1766 pxc->parent_realize(dev, &local_err); 1767 if (local_err) { 1768 error_propagate(errp, local_err); 1769 return; 1770 } 1771 1772 assert(xive->chip); 1773 1774 /* 1775 * The XiveSource and Xive2EndSource objects are realized with the 1776 * maximum allowed HW configuration. The ESB MMIO regions will be 1777 * resized dynamically when the controller is configured by the FW 1778 * to limit accesses to resources not provisioned. 1779 */ 1780 object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI, 1781 &error_fatal); 1782 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS, 1783 &error_fatal); 1784 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), 1785 &error_fatal); 1786 qdev_realize(DEVICE(xsrc), NULL, &local_err); 1787 if (local_err) { 1788 error_propagate(errp, local_err); 1789 return; 1790 } 1791 1792 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS, 1793 &error_fatal); 1794 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 1795 &error_abort); 1796 qdev_realize(DEVICE(end_xsrc), NULL, &local_err); 1797 if (local_err) { 1798 error_propagate(errp, local_err); 1799 return; 1800 } 1801 1802 /* XSCOM region, used for initial configuration of the BARs */ 1803 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), 1804 &pnv_xive2_xscom_ops, xive, "xscom-xive", 1805 PNV10_XSCOM_XIVE2_SIZE << 3); 1806 1807 /* Interrupt controller MMIO regions */ 1808 xive->ic_shift = 16; 1809 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 1810 PNV10_XIVE2_IC_SIZE); 1811 1812 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 1813 memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev), 1814 pnv_xive2_ic_regions[i].ops, xive, 1815 pnv_xive2_ic_regions[i].name, 1816 pnv_xive2_ic_regions[i].pgsize << xive->ic_shift); 1817 } 1818 1819 /* 1820 * VC MMIO regions. 1821 */ 1822 xive->esb_shift = 16; 1823 xive->end_shift = 16; 1824 memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb", 1825 PNV10_XIVE2_ESB_SIZE); 1826 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end", 1827 PNV10_XIVE2_END_SIZE); 1828 1829 /* Presenter Controller MMIO region (not modeled) */ 1830 xive->nvc_shift = 16; 1831 xive->nvpg_shift = 16; 1832 memory_region_init_io(&xive->nvc_mmio, OBJECT(dev), 1833 &pnv_xive2_nvc_ops, xive, 1834 "xive-nvc", PNV10_XIVE2_NVC_SIZE); 1835 1836 memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev), 1837 &pnv_xive2_nvpg_ops, xive, 1838 "xive-nvpg", PNV10_XIVE2_NVPG_SIZE); 1839 1840 /* Thread Interrupt Management Area (Direct) */ 1841 xive->tm_shift = 16; 1842 memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops, 1843 xive, "xive-tima", PNV10_XIVE2_TM_SIZE); 1844 1845 qemu_register_reset(pnv_xive2_reset, dev); 1846 } 1847 1848 static Property pnv_xive2_properties[] = { 1849 DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0), 1850 DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0), 1851 DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0), 1852 DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0), 1853 DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0), 1854 DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0), 1855 DEFINE_PROP_UINT64("capabilities", PnvXive2, capabilities, 1856 PNV_XIVE2_CAPABILITIES), 1857 DEFINE_PROP_UINT64("config", PnvXive2, config, 1858 PNV_XIVE2_CONFIGURATION), 1859 DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *), 1860 DEFINE_PROP_END_OF_LIST(), 1861 }; 1862 1863 static void pnv_xive2_instance_init(Object *obj) 1864 { 1865 PnvXive2 *xive = PNV_XIVE2(obj); 1866 1867 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 1868 TYPE_XIVE_SOURCE); 1869 object_initialize_child(obj, "end_source", &xive->end_source, 1870 TYPE_XIVE2_END_SOURCE); 1871 } 1872 1873 static int pnv_xive2_dt_xscom(PnvXScomInterface *dev, void *fdt, 1874 int xscom_offset) 1875 { 1876 const char compat_p10[] = "ibm,power10-xive-x"; 1877 char *name; 1878 int offset; 1879 uint32_t reg[] = { 1880 cpu_to_be32(PNV10_XSCOM_XIVE2_BASE), 1881 cpu_to_be32(PNV10_XSCOM_XIVE2_SIZE) 1882 }; 1883 1884 name = g_strdup_printf("xive@%x", PNV10_XSCOM_XIVE2_BASE); 1885 offset = fdt_add_subnode(fdt, xscom_offset, name); 1886 _FDT(offset); 1887 g_free(name); 1888 1889 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 1890 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, 1891 sizeof(compat_p10))); 1892 return 0; 1893 } 1894 1895 static void pnv_xive2_class_init(ObjectClass *klass, void *data) 1896 { 1897 DeviceClass *dc = DEVICE_CLASS(klass); 1898 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 1899 Xive2RouterClass *xrc = XIVE2_ROUTER_CLASS(klass); 1900 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1901 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 1902 PnvXive2Class *pxc = PNV_XIVE2_CLASS(klass); 1903 1904 xdc->dt_xscom = pnv_xive2_dt_xscom; 1905 1906 dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)"; 1907 device_class_set_parent_realize(dc, pnv_xive2_realize, 1908 &pxc->parent_realize); 1909 device_class_set_props(dc, pnv_xive2_properties); 1910 1911 xrc->get_eas = pnv_xive2_get_eas; 1912 xrc->get_pq = pnv_xive2_get_pq; 1913 xrc->set_pq = pnv_xive2_set_pq; 1914 xrc->get_end = pnv_xive2_get_end; 1915 xrc->write_end = pnv_xive2_write_end; 1916 xrc->get_nvp = pnv_xive2_get_nvp; 1917 xrc->write_nvp = pnv_xive2_write_nvp; 1918 xrc->get_block_id = pnv_xive2_get_block_id; 1919 1920 xnc->notify = pnv_xive2_notify; 1921 1922 xpc->match_nvt = pnv_xive2_match_nvt; 1923 }; 1924 1925 static const TypeInfo pnv_xive2_info = { 1926 .name = TYPE_PNV_XIVE2, 1927 .parent = TYPE_XIVE2_ROUTER, 1928 .instance_init = pnv_xive2_instance_init, 1929 .instance_size = sizeof(PnvXive2), 1930 .class_init = pnv_xive2_class_init, 1931 .class_size = sizeof(PnvXive2Class), 1932 .interfaces = (InterfaceInfo[]) { 1933 { TYPE_PNV_XSCOM_INTERFACE }, 1934 { } 1935 } 1936 }; 1937 1938 static void pnv_xive2_register_types(void) 1939 { 1940 type_register_static(&pnv_xive2_info); 1941 } 1942 1943 type_init(pnv_xive2_register_types) 1944 1945 static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, 1946 Monitor *mon) 1947 { 1948 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 1949 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 1950 1951 if (!xive2_nvp_is_valid(nvp)) { 1952 return; 1953 } 1954 1955 monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", 1956 nvp_idx, eq_blk, eq_idx, 1957 xive_get_field32(NVP2_W2_IPB, nvp->w2)); 1958 } 1959 1960 /* 1961 * If the table is direct, we can compute the number of PQ entries 1962 * provisioned by FW. 1963 */ 1964 static uint32_t pnv_xive2_nr_esbs(PnvXive2 *xive) 1965 { 1966 uint8_t blk = pnv_xive2_block_id(xive); 1967 uint64_t vsd = xive->vsds[VST_ESB][blk]; 1968 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 1969 1970 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 1971 } 1972 1973 /* 1974 * Compute the number of entries per indirect subpage. 1975 */ 1976 static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type) 1977 { 1978 uint8_t blk = pnv_xive2_block_id(xive); 1979 uint64_t vsd = xive->vsds[type][blk]; 1980 const XiveVstInfo *info = &vst_infos[type]; 1981 uint64_t vsd_addr; 1982 uint32_t page_shift; 1983 1984 /* For direct tables, fake a valid value */ 1985 if (!(VSD_INDIRECT & vsd)) { 1986 return 1; 1987 } 1988 1989 /* Get the page size of the indirect table. */ 1990 vsd_addr = vsd & VSD_ADDRESS_MASK; 1991 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 1992 1993 if (!(vsd & VSD_ADDRESS_MASK)) { 1994 #ifdef XIVE2_DEBUG 1995 xive2_error(xive, "VST: invalid %s entry!?", info->name); 1996 #endif 1997 return 0; 1998 } 1999 2000 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 2001 2002 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 2003 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 2004 page_shift); 2005 return 0; 2006 } 2007 2008 return (1ull << page_shift) / info->size; 2009 } 2010 2011 void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon) 2012 { 2013 Xive2Router *xrtr = XIVE2_ROUTER(xive); 2014 uint8_t blk = pnv_xive2_block_id(xive); 2015 uint8_t chip_id = xive->chip->chip_id; 2016 uint32_t srcno0 = XIVE_EAS(blk, 0); 2017 uint32_t nr_esbs = pnv_xive2_nr_esbs(xive); 2018 Xive2Eas eas; 2019 Xive2End end; 2020 Xive2Nvp nvp; 2021 int i; 2022 uint64_t xive_nvp_per_subpage; 2023 2024 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, 2025 srcno0 + nr_esbs - 1); 2026 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); 2027 2028 monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, 2029 srcno0 + nr_esbs - 1); 2030 for (i = 0; i < nr_esbs; i++) { 2031 if (xive2_router_get_eas(xrtr, blk, i, &eas)) { 2032 break; 2033 } 2034 if (!xive2_eas_is_masked(&eas)) { 2035 xive2_eas_pic_print_info(&eas, i, mon); 2036 } 2037 } 2038 2039 monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); 2040 i = 0; 2041 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2042 xive2_end_eas_pic_print_info(&end, i++, mon); 2043 } 2044 2045 monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); 2046 i = 0; 2047 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2048 xive2_end_pic_print_info(&end, i++, mon); 2049 } 2050 2051 monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk, 2052 0, XIVE2_NVP_COUNT - 1); 2053 xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); 2054 for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) { 2055 while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) { 2056 xive2_nvp_pic_print_info(&nvp, i++, mon); 2057 } 2058 } 2059 } 2060