1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "sysemu/cpus.h" 15 #include "sysemu/dma.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/pnv.h" 19 #include "hw/ppc/pnv_chip.h" 20 #include "hw/ppc/pnv_core.h" 21 #include "hw/ppc/pnv_xscom.h" 22 #include "hw/ppc/xive2.h" 23 #include "hw/ppc/pnv_xive.h" 24 #include "hw/ppc/xive_regs.h" 25 #include "hw/ppc/xive2_regs.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/qdev-properties.h" 28 #include "sysemu/reset.h" 29 30 #include <libfdt.h> 31 32 #include "pnv_xive2_regs.h" 33 34 #undef XIVE2_DEBUG 35 36 /* 37 * Virtual structures table (VST) 38 */ 39 #define SBE_PER_BYTE 4 40 41 typedef struct XiveVstInfo { 42 const char *name; 43 uint32_t size; 44 uint32_t max_blocks; 45 } XiveVstInfo; 46 47 static const XiveVstInfo vst_infos[] = { 48 49 [VST_EAS] = { "EAT", sizeof(Xive2Eas), 16 }, 50 [VST_ESB] = { "ESB", 1, 16 }, 51 [VST_END] = { "ENDT", sizeof(Xive2End), 16 }, 52 53 [VST_NVP] = { "NVPT", sizeof(Xive2Nvp), 16 }, 54 [VST_NVG] = { "NVGT", sizeof(Xive2Nvgc), 16 }, 55 [VST_NVC] = { "NVCT", sizeof(Xive2Nvgc), 16 }, 56 57 [VST_IC] = { "IC", 1 /* ? */ , 16 }, /* Topology # */ 58 [VST_SYNC] = { "SYNC", 1 /* ? */ , 16 }, /* Topology # */ 59 60 /* 61 * This table contains the backing store pages for the interrupt 62 * fifos of the VC sub-engine in case of overflow. 63 * 64 * 0 - IPI, 65 * 1 - HWD, 66 * 2 - NxC, 67 * 3 - INT, 68 * 4 - OS-Queue, 69 * 5 - Pool-Queue, 70 * 6 - Hard-Queue 71 */ 72 [VST_ERQ] = { "ERQ", 1, VC_QUEUE_COUNT }, 73 }; 74 75 #define xive2_error(xive, fmt, ...) \ 76 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 77 (xive)->chip->chip_id, ## __VA_ARGS__); 78 79 /* 80 * TODO: Document block id override 81 */ 82 static uint32_t pnv_xive2_block_id(PnvXive2 *xive) 83 { 84 uint8_t blk = xive->chip->chip_id; 85 uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3]; 86 87 if (cfg_val & CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE) { 88 blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val); 89 } 90 91 return blk; 92 } 93 94 /* 95 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 96 * of the chips is good enough. 97 * 98 * TODO: Block scope support 99 */ 100 static PnvXive2 *pnv_xive2_get_remote(uint8_t blk) 101 { 102 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 103 int i; 104 105 for (i = 0; i < pnv->num_chips; i++) { 106 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 107 PnvXive2 *xive = &chip10->xive; 108 109 if (pnv_xive2_block_id(xive) == blk) { 110 return xive; 111 } 112 } 113 return NULL; 114 } 115 116 /* 117 * VST accessors for ESB, EAT, ENDT, NVP 118 * 119 * Indirect VST tables are arrays of VSDs pointing to a page (of same 120 * size). Each page is a direct VST table. 121 */ 122 123 #define XIVE_VSD_SIZE 8 124 125 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 126 static uint64_t pnv_xive2_vst_page_size_allowed(uint32_t page_shift) 127 { 128 return page_shift == 12 || page_shift == 16 || 129 page_shift == 21 || page_shift == 24; 130 } 131 132 static uint64_t pnv_xive2_vst_addr_direct(PnvXive2 *xive, uint32_t type, 133 uint64_t vsd, uint32_t idx) 134 { 135 const XiveVstInfo *info = &vst_infos[type]; 136 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 137 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 138 uint32_t idx_max; 139 140 idx_max = vst_tsize / info->size - 1; 141 if (idx > idx_max) { 142 #ifdef XIVE2_DEBUG 143 xive2_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 144 info->name, idx, idx_max); 145 #endif 146 return 0; 147 } 148 149 return vst_addr + idx * info->size; 150 } 151 152 static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type, 153 uint64_t vsd, uint32_t idx) 154 { 155 const XiveVstInfo *info = &vst_infos[type]; 156 uint64_t vsd_addr; 157 uint32_t vsd_idx; 158 uint32_t page_shift; 159 uint32_t vst_per_page; 160 161 /* Get the page size of the indirect table. */ 162 vsd_addr = vsd & VSD_ADDRESS_MASK; 163 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 164 165 if (!(vsd & VSD_ADDRESS_MASK)) { 166 #ifdef XIVE2_DEBUG 167 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 168 #endif 169 return 0; 170 } 171 172 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 173 174 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 175 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 176 page_shift); 177 return 0; 178 } 179 180 vst_per_page = (1ull << page_shift) / info->size; 181 vsd_idx = idx / vst_per_page; 182 183 /* Load the VSD we are looking for, if not already done */ 184 if (vsd_idx) { 185 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 186 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, 187 MEMTXATTRS_UNSPECIFIED); 188 189 if (!(vsd & VSD_ADDRESS_MASK)) { 190 #ifdef XIVE2_DEBUG 191 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 192 #endif 193 return 0; 194 } 195 196 /* 197 * Check that the pages have a consistent size across the 198 * indirect table 199 */ 200 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 201 xive2_error(xive, "VST: %s entry %x indirect page size differ !?", 202 info->name, idx); 203 return 0; 204 } 205 } 206 207 return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 208 } 209 210 static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk, 211 uint32_t idx) 212 { 213 const XiveVstInfo *info = &vst_infos[type]; 214 uint64_t vsd; 215 216 if (blk >= info->max_blocks) { 217 xive2_error(xive, "VST: invalid block id %d for VST %s %d !?", 218 blk, info->name, idx); 219 return 0; 220 } 221 222 vsd = xive->vsds[type][blk]; 223 224 /* Remote VST access */ 225 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 226 xive = pnv_xive2_get_remote(blk); 227 228 return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0; 229 } 230 231 if (VSD_INDIRECT & vsd) { 232 return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx); 233 } 234 235 return pnv_xive2_vst_addr_direct(xive, type, vsd, idx); 236 } 237 238 static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk, 239 uint32_t idx, void *data) 240 { 241 const XiveVstInfo *info = &vst_infos[type]; 242 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 243 244 if (!addr) { 245 return -1; 246 } 247 248 cpu_physical_memory_read(addr, data, info->size); 249 return 0; 250 } 251 252 #define XIVE_VST_WORD_ALL -1 253 254 static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk, 255 uint32_t idx, void *data, uint32_t word_number) 256 { 257 const XiveVstInfo *info = &vst_infos[type]; 258 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 259 260 if (!addr) { 261 return -1; 262 } 263 264 if (word_number == XIVE_VST_WORD_ALL) { 265 cpu_physical_memory_write(addr, data, info->size); 266 } else { 267 cpu_physical_memory_write(addr + word_number * 4, 268 data + word_number * 4, 4); 269 } 270 return 0; 271 } 272 273 static int pnv_xive2_get_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 274 uint8_t *pq) 275 { 276 PnvXive2 *xive = PNV_XIVE2(xrtr); 277 278 if (pnv_xive2_block_id(xive) != blk) { 279 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 280 return -1; 281 } 282 283 *pq = xive_source_esb_get(&xive->ipi_source, idx); 284 return 0; 285 } 286 287 static int pnv_xive2_set_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 288 uint8_t *pq) 289 { 290 PnvXive2 *xive = PNV_XIVE2(xrtr); 291 292 if (pnv_xive2_block_id(xive) != blk) { 293 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 294 return -1; 295 } 296 297 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq); 298 return 0; 299 } 300 301 static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 302 Xive2End *end) 303 { 304 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_END, blk, idx, end); 305 } 306 307 static int pnv_xive2_write_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 308 Xive2End *end, uint8_t word_number) 309 { 310 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_END, blk, idx, end, 311 word_number); 312 } 313 314 static int pnv_xive2_end_update(PnvXive2 *xive) 315 { 316 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 317 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 318 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 319 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 320 int i; 321 uint64_t endc_watch[4]; 322 323 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 324 endc_watch[i] = 325 cpu_to_be64(xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i]); 326 } 327 328 return pnv_xive2_vst_write(xive, VST_END, blk, idx, endc_watch, 329 XIVE_VST_WORD_ALL); 330 } 331 332 static void pnv_xive2_end_cache_load(PnvXive2 *xive) 333 { 334 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 335 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 336 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 337 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 338 uint64_t endc_watch[4] = { 0 }; 339 int i; 340 341 if (pnv_xive2_vst_read(xive, VST_END, blk, idx, endc_watch)) { 342 xive2_error(xive, "VST: no END entry %x/%x !?", blk, idx); 343 } 344 345 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 346 xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i] = 347 be64_to_cpu(endc_watch[i]); 348 } 349 } 350 351 static int pnv_xive2_get_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 352 Xive2Nvp *nvp) 353 { 354 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp); 355 } 356 357 static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 358 Xive2Nvp *nvp, uint8_t word_number) 359 { 360 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp, 361 word_number); 362 } 363 364 static int pnv_xive2_nvp_update(PnvXive2 *xive) 365 { 366 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 367 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 368 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 369 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 370 int i; 371 uint64_t nxc_watch[4]; 372 373 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 374 nxc_watch[i] = 375 cpu_to_be64(xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i]); 376 } 377 378 return pnv_xive2_vst_write(xive, VST_NVP, blk, idx, nxc_watch, 379 XIVE_VST_WORD_ALL); 380 } 381 382 static void pnv_xive2_nvp_cache_load(PnvXive2 *xive) 383 { 384 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 385 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 386 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 387 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 388 uint64_t nxc_watch[4] = { 0 }; 389 int i; 390 391 if (pnv_xive2_vst_read(xive, VST_NVP, blk, idx, nxc_watch)) { 392 xive2_error(xive, "VST: no NVP entry %x/%x !?", blk, idx); 393 } 394 395 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 396 xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i] = 397 be64_to_cpu(nxc_watch[i]); 398 } 399 } 400 401 static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 402 Xive2Eas *eas) 403 { 404 PnvXive2 *xive = PNV_XIVE2(xrtr); 405 406 if (pnv_xive2_block_id(xive) != blk) { 407 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 408 return -1; 409 } 410 411 return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas); 412 } 413 414 static uint32_t pnv_xive2_get_config(Xive2Router *xrtr) 415 { 416 PnvXive2 *xive = PNV_XIVE2(xrtr); 417 uint32_t cfg = 0; 418 419 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { 420 cfg |= XIVE2_GEN1_TIMA_OS; 421 } 422 423 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) { 424 cfg |= XIVE2_VP_SAVE_RESTORE; 425 } 426 427 if (GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, 428 xive->cq_regs[CQ_XIVE_CFG >> 3]) == CQ_XIVE_CFG_THREADID_8BITS) { 429 cfg |= XIVE2_THREADID_8BITS; 430 } 431 432 return cfg; 433 } 434 435 static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu) 436 { 437 int pir = ppc_cpu_pir(cpu); 438 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); 439 uint64_t reg = fc < 8 ? TCTXT_EN0 : TCTXT_EN1; 440 uint32_t bit = pir & 0x3f; 441 442 return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit); 443 } 444 445 static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, 446 uint8_t nvt_blk, uint32_t nvt_idx, 447 bool cam_ignore, uint8_t priority, 448 uint32_t logic_serv, XiveTCTXMatch *match) 449 { 450 PnvXive2 *xive = PNV_XIVE2(xptr); 451 PnvChip *chip = xive->chip; 452 int count = 0; 453 int i, j; 454 bool gen1_tima_os = 455 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 456 457 for (i = 0; i < chip->nr_cores; i++) { 458 PnvCore *pc = chip->cores[i]; 459 CPUCore *cc = CPU_CORE(pc); 460 461 for (j = 0; j < cc->nr_threads; j++) { 462 PowerPCCPU *cpu = pc->threads[j]; 463 XiveTCTX *tctx; 464 int ring; 465 466 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 467 continue; 468 } 469 470 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 471 472 if (gen1_tima_os) { 473 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, 474 nvt_idx, cam_ignore, 475 logic_serv); 476 } else { 477 ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk, 478 nvt_idx, cam_ignore, 479 logic_serv); 480 } 481 482 /* 483 * Save the context and follow on to catch duplicates, 484 * that we don't support yet. 485 */ 486 if (ring != -1) { 487 if (match->tctx) { 488 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 489 "thread context NVT %x/%x\n", 490 nvt_blk, nvt_idx); 491 return false; 492 } 493 494 match->ring = ring; 495 match->tctx = tctx; 496 count++; 497 } 498 } 499 } 500 501 return count; 502 } 503 504 static uint32_t pnv_xive2_presenter_get_config(XivePresenter *xptr) 505 { 506 PnvXive2 *xive = PNV_XIVE2(xptr); 507 uint32_t cfg = 0; 508 509 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { 510 cfg |= XIVE_PRESENTER_GEN1_TIMA_OS; 511 } 512 return cfg; 513 } 514 515 static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) 516 { 517 return pnv_xive2_block_id(PNV_XIVE2(xrtr)); 518 } 519 520 /* 521 * The TIMA MMIO space is shared among the chips and to identify the 522 * chip from which the access is being done, we extract the chip id 523 * from the PIR. 524 */ 525 static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu) 526 { 527 int pir = ppc_cpu_pir(cpu); 528 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; 529 PnvXive2 *xive = PNV_XIVE2(xptr); 530 531 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 532 xive2_error(xive, "IC: CPU %x is not enabled", pir); 533 } 534 return xive; 535 } 536 537 /* 538 * The internal sources of the interrupt controller have no knowledge 539 * of the XIVE2 chip on which they reside. Encode the block id in the 540 * source interrupt number before forwarding the source event 541 * notification to the Router. This is required on a multichip system. 542 */ 543 static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked) 544 { 545 PnvXive2 *xive = PNV_XIVE2(xn); 546 uint8_t blk = pnv_xive2_block_id(xive); 547 548 xive2_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked); 549 } 550 551 /* 552 * Set Translation Tables 553 * 554 * TODO add support for multiple sets 555 */ 556 static int pnv_xive2_stt_set_data(PnvXive2 *xive, uint64_t val) 557 { 558 uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]); 559 uint8_t entry = GETFIELD(CQ_TAR_ENTRY_SELECT, 560 xive->cq_regs[CQ_TAR >> 3]); 561 562 switch (tsel) { 563 case CQ_TAR_NVPG: 564 case CQ_TAR_ESB: 565 case CQ_TAR_END: 566 xive->tables[tsel][entry] = val; 567 break; 568 default: 569 xive2_error(xive, "IC: unsupported table %d", tsel); 570 return -1; 571 } 572 573 if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) { 574 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT, 575 xive->cq_regs[CQ_TAR >> 3], ++entry); 576 } 577 578 return 0; 579 } 580 /* 581 * Virtual Structure Tables (VST) configuration 582 */ 583 static void pnv_xive2_vst_set_exclusive(PnvXive2 *xive, uint8_t type, 584 uint8_t blk, uint64_t vsd) 585 { 586 Xive2EndSource *end_xsrc = &xive->end_source; 587 XiveSource *xsrc = &xive->ipi_source; 588 const XiveVstInfo *info = &vst_infos[type]; 589 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 590 uint64_t vst_tsize = 1ull << page_shift; 591 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 592 593 /* Basic checks */ 594 595 if (VSD_INDIRECT & vsd) { 596 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 597 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 598 page_shift); 599 return; 600 } 601 } 602 603 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 604 xive2_error(xive, "VST: %s table address 0x%"PRIx64 605 " is not aligned with page shift %d", 606 info->name, vst_addr, page_shift); 607 return; 608 } 609 610 /* Record the table configuration (in SRAM on HW) */ 611 xive->vsds[type][blk] = vsd; 612 613 /* Now tune the models with the configuration provided by the FW */ 614 615 switch (type) { 616 case VST_ESB: 617 /* 618 * Backing store pages for the source PQ bits. The model does 619 * not use these PQ bits backed in RAM because the XiveSource 620 * model has its own. 621 * 622 * If the table is direct, we can compute the number of PQ 623 * entries provisioned by FW (such as skiboot) and resize the 624 * ESB window accordingly. 625 */ 626 if (!(VSD_INDIRECT & vsd)) { 627 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 628 * (1ull << xsrc->esb_shift)); 629 } 630 631 memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio); 632 break; 633 634 case VST_EAS: /* Nothing to be done */ 635 break; 636 637 case VST_END: 638 /* 639 * Backing store pages for the END. 640 */ 641 if (!(VSD_INDIRECT & vsd)) { 642 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 643 * (1ull << end_xsrc->esb_shift)); 644 } 645 memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio); 646 break; 647 648 case VST_NVP: /* Not modeled */ 649 case VST_NVG: /* Not modeled */ 650 case VST_NVC: /* Not modeled */ 651 case VST_IC: /* Not modeled */ 652 case VST_SYNC: /* Not modeled */ 653 case VST_ERQ: /* Not modeled */ 654 break; 655 656 default: 657 g_assert_not_reached(); 658 } 659 } 660 661 /* 662 * Both PC and VC sub-engines are configured as each use the Virtual 663 * Structure Tables 664 */ 665 static void pnv_xive2_vst_set_data(PnvXive2 *xive, uint64_t vsd) 666 { 667 uint8_t mode = GETFIELD(VSD_MODE, vsd); 668 uint8_t type = GETFIELD(VC_VSD_TABLE_SELECT, 669 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 670 uint8_t blk = GETFIELD(VC_VSD_TABLE_ADDRESS, 671 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 672 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 673 674 if (type > VST_ERQ) { 675 xive2_error(xive, "VST: invalid table type %d", type); 676 return; 677 } 678 679 if (blk >= vst_infos[type].max_blocks) { 680 xive2_error(xive, "VST: invalid block id %d for" 681 " %s table", blk, vst_infos[type].name); 682 return; 683 } 684 685 if (!vst_addr) { 686 xive2_error(xive, "VST: invalid %s table address", 687 vst_infos[type].name); 688 return; 689 } 690 691 switch (mode) { 692 case VSD_MODE_FORWARD: 693 xive->vsds[type][blk] = vsd; 694 break; 695 696 case VSD_MODE_EXCLUSIVE: 697 pnv_xive2_vst_set_exclusive(xive, type, blk, vsd); 698 break; 699 700 default: 701 xive2_error(xive, "VST: unsupported table mode %d", mode); 702 return; 703 } 704 } 705 706 /* 707 * MMIO handlers 708 */ 709 710 711 /* 712 * IC BAR layout 713 * 714 * Page 0: Internal CQ register accesses (reads & writes) 715 * Page 1: Internal PC register accesses (reads & writes) 716 * Page 2: Internal VC register accesses (reads & writes) 717 * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes) 718 * Page 4: Notify Port page (writes only, w/data), 719 * Page 5: Reserved 720 * Page 6: Sync Poll page (writes only, dataless) 721 * Page 7: Sync Inject page (writes only, dataless) 722 * Page 8: LSI Trigger page (writes only, dataless) 723 * Page 9: LSI SB Management page (reads & writes dataless) 724 * Pages 10-255: Reserved 725 * Pages 256-383: Direct mapped Thread Context Area (reads & writes) 726 * covering the 128 threads in P10. 727 * Pages 384-511: Reserved 728 */ 729 typedef struct PnvXive2Region { 730 const char *name; 731 uint32_t pgoff; 732 uint32_t pgsize; 733 const MemoryRegionOps *ops; 734 } PnvXive2Region; 735 736 static const MemoryRegionOps pnv_xive2_ic_cq_ops; 737 static const MemoryRegionOps pnv_xive2_ic_pc_ops; 738 static const MemoryRegionOps pnv_xive2_ic_vc_ops; 739 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops; 740 static const MemoryRegionOps pnv_xive2_ic_notify_ops; 741 static const MemoryRegionOps pnv_xive2_ic_sync_ops; 742 static const MemoryRegionOps pnv_xive2_ic_lsi_ops; 743 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops; 744 745 /* 512 pages. 4K: 2M range, 64K: 32M range */ 746 static const PnvXive2Region pnv_xive2_ic_regions[] = { 747 { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops }, 748 { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops }, 749 { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops }, 750 { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops }, 751 { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops }, 752 /* page 5 reserved */ 753 { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops }, 754 { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops }, 755 /* pages 10-255 reserved */ 756 { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops }, 757 /* pages 384-511 reserved */ 758 }; 759 760 /* 761 * CQ operations 762 */ 763 764 static uint64_t pnv_xive2_ic_cq_read(void *opaque, hwaddr offset, 765 unsigned size) 766 { 767 PnvXive2 *xive = PNV_XIVE2(opaque); 768 uint32_t reg = offset >> 3; 769 uint64_t val = 0; 770 771 switch (offset) { 772 case CQ_XIVE_CAP: /* Set at reset */ 773 case CQ_XIVE_CFG: 774 val = xive->cq_regs[reg]; 775 break; 776 case CQ_MSGSND: /* TODO check the #cores of the machine */ 777 val = 0xffffffff00000000; 778 break; 779 case CQ_CFG_PB_GEN: 780 val = CQ_CFG_PB_GEN_PB_INIT; /* TODO: fix CQ_CFG_PB_GEN default value */ 781 break; 782 default: 783 xive2_error(xive, "CQ: invalid read @%"HWADDR_PRIx, offset); 784 } 785 786 return val; 787 } 788 789 static uint64_t pnv_xive2_bar_size(uint64_t val) 790 { 791 return 1ull << (GETFIELD(CQ_BAR_RANGE, val) + 24); 792 } 793 794 static void pnv_xive2_ic_cq_write(void *opaque, hwaddr offset, 795 uint64_t val, unsigned size) 796 { 797 PnvXive2 *xive = PNV_XIVE2(opaque); 798 MemoryRegion *sysmem = get_system_memory(); 799 uint32_t reg = offset >> 3; 800 int i; 801 802 switch (offset) { 803 case CQ_XIVE_CFG: 804 case CQ_RST_CTL: /* TODO: reset all BARs */ 805 break; 806 807 case CQ_IC_BAR: 808 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 809 if (!(val & CQ_IC_BAR_VALID)) { 810 xive->ic_base = 0; 811 if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) { 812 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 813 memory_region_del_subregion(&xive->ic_mmio, 814 &xive->ic_mmios[i]); 815 } 816 memory_region_del_subregion(sysmem, &xive->ic_mmio); 817 } 818 } else { 819 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 820 if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) { 821 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 822 memory_region_add_subregion(&xive->ic_mmio, 823 pnv_xive2_ic_regions[i].pgoff << xive->ic_shift, 824 &xive->ic_mmios[i]); 825 } 826 memory_region_add_subregion(sysmem, xive->ic_base, 827 &xive->ic_mmio); 828 } 829 } 830 break; 831 832 case CQ_TM_BAR: 833 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 834 if (!(val & CQ_TM_BAR_VALID)) { 835 xive->tm_base = 0; 836 if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) { 837 memory_region_del_subregion(sysmem, &xive->tm_mmio); 838 } 839 } else { 840 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 841 if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) { 842 memory_region_add_subregion(sysmem, xive->tm_base, 843 &xive->tm_mmio); 844 } 845 } 846 break; 847 848 case CQ_ESB_BAR: 849 xive->esb_shift = val & CQ_BAR_64K ? 16 : 12; 850 if (!(val & CQ_BAR_VALID)) { 851 xive->esb_base = 0; 852 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 853 memory_region_del_subregion(sysmem, &xive->esb_mmio); 854 } 855 } else { 856 xive->esb_base = val & CQ_BAR_ADDR; 857 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 858 memory_region_set_size(&xive->esb_mmio, 859 pnv_xive2_bar_size(val)); 860 memory_region_add_subregion(sysmem, xive->esb_base, 861 &xive->esb_mmio); 862 } 863 } 864 break; 865 866 case CQ_END_BAR: 867 xive->end_shift = val & CQ_BAR_64K ? 16 : 12; 868 if (!(val & CQ_BAR_VALID)) { 869 xive->end_base = 0; 870 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 871 memory_region_del_subregion(sysmem, &xive->end_mmio); 872 } 873 } else { 874 xive->end_base = val & CQ_BAR_ADDR; 875 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 876 memory_region_set_size(&xive->end_mmio, 877 pnv_xive2_bar_size(val)); 878 memory_region_add_subregion(sysmem, xive->end_base, 879 &xive->end_mmio); 880 } 881 } 882 break; 883 884 case CQ_NVC_BAR: 885 xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12; 886 if (!(val & CQ_BAR_VALID)) { 887 xive->nvc_base = 0; 888 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 889 memory_region_del_subregion(sysmem, &xive->nvc_mmio); 890 } 891 } else { 892 xive->nvc_base = val & CQ_BAR_ADDR; 893 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 894 memory_region_set_size(&xive->nvc_mmio, 895 pnv_xive2_bar_size(val)); 896 memory_region_add_subregion(sysmem, xive->nvc_base, 897 &xive->nvc_mmio); 898 } 899 } 900 break; 901 902 case CQ_NVPG_BAR: 903 xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12; 904 if (!(val & CQ_BAR_VALID)) { 905 xive->nvpg_base = 0; 906 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 907 memory_region_del_subregion(sysmem, &xive->nvpg_mmio); 908 } 909 } else { 910 xive->nvpg_base = val & CQ_BAR_ADDR; 911 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 912 memory_region_set_size(&xive->nvpg_mmio, 913 pnv_xive2_bar_size(val)); 914 memory_region_add_subregion(sysmem, xive->nvpg_base, 915 &xive->nvpg_mmio); 916 } 917 } 918 break; 919 920 case CQ_TAR: /* Set Translation Table Address */ 921 break; 922 case CQ_TDR: /* Set Translation Table Data */ 923 pnv_xive2_stt_set_data(xive, val); 924 break; 925 case CQ_FIRMASK_OR: /* FIR error reporting */ 926 break; 927 default: 928 xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset); 929 return; 930 } 931 932 xive->cq_regs[reg] = val; 933 } 934 935 static const MemoryRegionOps pnv_xive2_ic_cq_ops = { 936 .read = pnv_xive2_ic_cq_read, 937 .write = pnv_xive2_ic_cq_write, 938 .endianness = DEVICE_BIG_ENDIAN, 939 .valid = { 940 .min_access_size = 8, 941 .max_access_size = 8, 942 }, 943 .impl = { 944 .min_access_size = 8, 945 .max_access_size = 8, 946 }, 947 }; 948 949 static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, 950 unsigned size) 951 { 952 PnvXive2 *xive = PNV_XIVE2(opaque); 953 uint64_t val = 0; 954 uint32_t reg = offset >> 3; 955 956 switch (offset) { 957 /* 958 * VSD table settings. 959 */ 960 case VC_VSD_TABLE_ADDR: 961 case VC_VSD_TABLE_DATA: 962 val = xive->vc_regs[reg]; 963 break; 964 965 /* 966 * ESB cache updates (not modeled) 967 */ 968 case VC_ESBC_FLUSH_CTRL: 969 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID; 970 val = xive->vc_regs[reg]; 971 break; 972 973 case VC_ESBC_CFG: 974 val = xive->vc_regs[reg]; 975 break; 976 977 /* 978 * EAS cache updates (not modeled) 979 */ 980 case VC_EASC_FLUSH_CTRL: 981 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID; 982 val = xive->vc_regs[reg]; 983 break; 984 985 /* 986 * END cache updates 987 */ 988 case VC_ENDC_WATCH0_SPEC: 989 xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT); 990 val = xive->vc_regs[reg]; 991 break; 992 993 case VC_ENDC_WATCH0_DATA0: 994 /* 995 * Load DATA registers from cache with data requested by the 996 * SPEC register 997 */ 998 pnv_xive2_end_cache_load(xive); 999 val = xive->vc_regs[reg]; 1000 break; 1001 1002 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1003 val = xive->vc_regs[reg]; 1004 break; 1005 1006 case VC_ENDC_FLUSH_CTRL: 1007 xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID; 1008 val = xive->vc_regs[reg]; 1009 break; 1010 1011 /* 1012 * Indirect invalidation 1013 */ 1014 case VC_AT_MACRO_KILL_MASK: 1015 val = xive->vc_regs[reg]; 1016 break; 1017 1018 case VC_AT_MACRO_KILL: 1019 xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID; 1020 val = xive->vc_regs[reg]; 1021 break; 1022 1023 /* 1024 * Interrupt fifo overflow in memory backing store (Not modeled) 1025 */ 1026 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1027 val = xive->vc_regs[reg]; 1028 break; 1029 1030 /* 1031 * Synchronisation 1032 */ 1033 case VC_ENDC_SYNC_DONE: 1034 val = VC_ENDC_SYNC_POLL_DONE; 1035 break; 1036 default: 1037 xive2_error(xive, "VC: invalid read @%"HWADDR_PRIx, offset); 1038 } 1039 1040 return val; 1041 } 1042 1043 static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, 1044 uint64_t val, unsigned size) 1045 { 1046 PnvXive2 *xive = PNV_XIVE2(opaque); 1047 uint32_t reg = offset >> 3; 1048 1049 switch (offset) { 1050 /* 1051 * VSD table settings. 1052 */ 1053 case VC_VSD_TABLE_ADDR: 1054 break; 1055 case VC_VSD_TABLE_DATA: 1056 pnv_xive2_vst_set_data(xive, val); 1057 break; 1058 1059 /* 1060 * ESB cache updates (not modeled) 1061 */ 1062 /* case VC_ESBC_FLUSH_CTRL: */ 1063 case VC_ESBC_FLUSH_POLL: 1064 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; 1065 /* ESB update */ 1066 break; 1067 1068 case VC_ESBC_CFG: 1069 break; 1070 1071 /* 1072 * EAS cache updates (not modeled) 1073 */ 1074 /* case VC_EASC_FLUSH_CTRL: */ 1075 case VC_EASC_FLUSH_POLL: 1076 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; 1077 /* EAS update */ 1078 break; 1079 1080 /* 1081 * END cache updates 1082 */ 1083 case VC_ENDC_WATCH0_SPEC: 1084 val &= ~VC_ENDC_WATCH_CONFLICT; /* HW will set this bit */ 1085 break; 1086 1087 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1088 break; 1089 case VC_ENDC_WATCH0_DATA0: 1090 /* writing to DATA0 triggers the cache write */ 1091 xive->vc_regs[reg] = val; 1092 pnv_xive2_end_update(xive); 1093 break; 1094 1095 1096 /* case VC_ENDC_FLUSH_CTRL: */ 1097 case VC_ENDC_FLUSH_POLL: 1098 xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; 1099 break; 1100 1101 /* 1102 * Indirect invalidation 1103 */ 1104 case VC_AT_MACRO_KILL: 1105 case VC_AT_MACRO_KILL_MASK: 1106 break; 1107 1108 /* 1109 * Interrupt fifo overflow in memory backing store (Not modeled) 1110 */ 1111 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1112 break; 1113 1114 /* 1115 * Synchronisation 1116 */ 1117 case VC_ENDC_SYNC_DONE: 1118 break; 1119 1120 default: 1121 xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset); 1122 return; 1123 } 1124 1125 xive->vc_regs[reg] = val; 1126 } 1127 1128 static const MemoryRegionOps pnv_xive2_ic_vc_ops = { 1129 .read = pnv_xive2_ic_vc_read, 1130 .write = pnv_xive2_ic_vc_write, 1131 .endianness = DEVICE_BIG_ENDIAN, 1132 .valid = { 1133 .min_access_size = 8, 1134 .max_access_size = 8, 1135 }, 1136 .impl = { 1137 .min_access_size = 8, 1138 .max_access_size = 8, 1139 }, 1140 }; 1141 1142 static uint64_t pnv_xive2_ic_pc_read(void *opaque, hwaddr offset, 1143 unsigned size) 1144 { 1145 PnvXive2 *xive = PNV_XIVE2(opaque); 1146 uint64_t val = -1; 1147 uint32_t reg = offset >> 3; 1148 1149 switch (offset) { 1150 /* 1151 * VSD table settings. 1152 */ 1153 case PC_VSD_TABLE_ADDR: 1154 case PC_VSD_TABLE_DATA: 1155 val = xive->pc_regs[reg]; 1156 break; 1157 1158 /* 1159 * cache updates 1160 */ 1161 case PC_NXC_WATCH0_SPEC: 1162 xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT); 1163 val = xive->pc_regs[reg]; 1164 break; 1165 1166 case PC_NXC_WATCH0_DATA0: 1167 /* 1168 * Load DATA registers from cache with data requested by the 1169 * SPEC register 1170 */ 1171 pnv_xive2_nvp_cache_load(xive); 1172 val = xive->pc_regs[reg]; 1173 break; 1174 1175 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1176 val = xive->pc_regs[reg]; 1177 break; 1178 1179 case PC_NXC_FLUSH_CTRL: 1180 xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID; 1181 val = xive->pc_regs[reg]; 1182 break; 1183 1184 /* 1185 * Indirect invalidation 1186 */ 1187 case PC_AT_KILL: 1188 xive->pc_regs[reg] &= ~PC_AT_KILL_VALID; 1189 val = xive->pc_regs[reg]; 1190 break; 1191 1192 default: 1193 xive2_error(xive, "PC: invalid read @%"HWADDR_PRIx, offset); 1194 } 1195 1196 return val; 1197 } 1198 1199 static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset, 1200 uint64_t val, unsigned size) 1201 { 1202 PnvXive2 *xive = PNV_XIVE2(opaque); 1203 uint32_t reg = offset >> 3; 1204 1205 switch (offset) { 1206 1207 /* 1208 * VSD table settings. Only taken into account in the VC 1209 * sub-engine because the Xive2Router model combines both VC and PC 1210 * sub-engines 1211 */ 1212 case PC_VSD_TABLE_ADDR: 1213 case PC_VSD_TABLE_DATA: 1214 break; 1215 1216 /* 1217 * cache updates 1218 */ 1219 case PC_NXC_WATCH0_SPEC: 1220 val &= ~PC_NXC_WATCH_CONFLICT; /* HW will set this bit */ 1221 break; 1222 1223 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1224 break; 1225 case PC_NXC_WATCH0_DATA0: 1226 /* writing to DATA0 triggers the cache write */ 1227 xive->pc_regs[reg] = val; 1228 pnv_xive2_nvp_update(xive); 1229 break; 1230 1231 /* case PC_NXC_FLUSH_CTRL: */ 1232 case PC_NXC_FLUSH_POLL: 1233 xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; 1234 break; 1235 1236 /* 1237 * Indirect invalidation 1238 */ 1239 case PC_AT_KILL: 1240 case PC_AT_KILL_MASK: 1241 break; 1242 1243 default: 1244 xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset); 1245 return; 1246 } 1247 1248 xive->pc_regs[reg] = val; 1249 } 1250 1251 static const MemoryRegionOps pnv_xive2_ic_pc_ops = { 1252 .read = pnv_xive2_ic_pc_read, 1253 .write = pnv_xive2_ic_pc_write, 1254 .endianness = DEVICE_BIG_ENDIAN, 1255 .valid = { 1256 .min_access_size = 8, 1257 .max_access_size = 8, 1258 }, 1259 .impl = { 1260 .min_access_size = 8, 1261 .max_access_size = 8, 1262 }, 1263 }; 1264 1265 1266 static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset, 1267 unsigned size) 1268 { 1269 PnvXive2 *xive = PNV_XIVE2(opaque); 1270 uint64_t val = -1; 1271 uint32_t reg = offset >> 3; 1272 1273 switch (offset) { 1274 /* 1275 * XIVE2 hardware thread enablement 1276 */ 1277 case TCTXT_EN0: 1278 case TCTXT_EN1: 1279 val = xive->tctxt_regs[reg]; 1280 break; 1281 1282 case TCTXT_EN0_SET: 1283 case TCTXT_EN0_RESET: 1284 val = xive->tctxt_regs[TCTXT_EN0 >> 3]; 1285 break; 1286 case TCTXT_EN1_SET: 1287 case TCTXT_EN1_RESET: 1288 val = xive->tctxt_regs[TCTXT_EN1 >> 3]; 1289 break; 1290 case TCTXT_CFG: 1291 val = xive->tctxt_regs[reg]; 1292 break; 1293 default: 1294 xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); 1295 } 1296 1297 return val; 1298 } 1299 1300 static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, 1301 uint64_t val, unsigned size) 1302 { 1303 PnvXive2 *xive = PNV_XIVE2(opaque); 1304 uint32_t reg = offset >> 3; 1305 1306 switch (offset) { 1307 /* 1308 * XIVE2 hardware thread enablement 1309 */ 1310 case TCTXT_EN0: /* Physical Thread Enable */ 1311 case TCTXT_EN1: /* Physical Thread Enable (fused core) */ 1312 xive->tctxt_regs[reg] = val; 1313 break; 1314 1315 case TCTXT_EN0_SET: 1316 xive->tctxt_regs[TCTXT_EN0 >> 3] |= val; 1317 break; 1318 case TCTXT_EN1_SET: 1319 xive->tctxt_regs[TCTXT_EN1 >> 3] |= val; 1320 break; 1321 case TCTXT_EN0_RESET: 1322 xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val; 1323 break; 1324 case TCTXT_EN1_RESET: 1325 xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; 1326 break; 1327 case TCTXT_CFG: 1328 xive->tctxt_regs[reg] = val; 1329 break; 1330 default: 1331 xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); 1332 return; 1333 } 1334 } 1335 1336 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = { 1337 .read = pnv_xive2_ic_tctxt_read, 1338 .write = pnv_xive2_ic_tctxt_write, 1339 .endianness = DEVICE_BIG_ENDIAN, 1340 .valid = { 1341 .min_access_size = 8, 1342 .max_access_size = 8, 1343 }, 1344 .impl = { 1345 .min_access_size = 8, 1346 .max_access_size = 8, 1347 }, 1348 }; 1349 1350 /* 1351 * Redirect XSCOM to MMIO handlers 1352 */ 1353 static uint64_t pnv_xive2_xscom_read(void *opaque, hwaddr offset, 1354 unsigned size) 1355 { 1356 PnvXive2 *xive = PNV_XIVE2(opaque); 1357 uint64_t val = -1; 1358 uint32_t xscom_reg = offset >> 3; 1359 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1360 1361 switch (xscom_reg) { 1362 case 0x000 ... 0x0FF: 1363 val = pnv_xive2_ic_cq_read(opaque, mmio_offset, size); 1364 break; 1365 case 0x100 ... 0x1FF: 1366 val = pnv_xive2_ic_vc_read(opaque, mmio_offset, size); 1367 break; 1368 case 0x200 ... 0x2FF: 1369 val = pnv_xive2_ic_pc_read(opaque, mmio_offset, size); 1370 break; 1371 case 0x300 ... 0x3FF: 1372 val = pnv_xive2_ic_tctxt_read(opaque, mmio_offset, size); 1373 break; 1374 default: 1375 xive2_error(xive, "XSCOM: invalid read @%"HWADDR_PRIx, offset); 1376 } 1377 1378 return val; 1379 } 1380 1381 static void pnv_xive2_xscom_write(void *opaque, hwaddr offset, 1382 uint64_t val, unsigned size) 1383 { 1384 PnvXive2 *xive = PNV_XIVE2(opaque); 1385 uint32_t xscom_reg = offset >> 3; 1386 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1387 1388 switch (xscom_reg) { 1389 case 0x000 ... 0x0FF: 1390 pnv_xive2_ic_cq_write(opaque, mmio_offset, val, size); 1391 break; 1392 case 0x100 ... 0x1FF: 1393 pnv_xive2_ic_vc_write(opaque, mmio_offset, val, size); 1394 break; 1395 case 0x200 ... 0x2FF: 1396 pnv_xive2_ic_pc_write(opaque, mmio_offset, val, size); 1397 break; 1398 case 0x300 ... 0x3FF: 1399 pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size); 1400 break; 1401 default: 1402 xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset); 1403 } 1404 } 1405 1406 static const MemoryRegionOps pnv_xive2_xscom_ops = { 1407 .read = pnv_xive2_xscom_read, 1408 .write = pnv_xive2_xscom_write, 1409 .endianness = DEVICE_BIG_ENDIAN, 1410 .valid = { 1411 .min_access_size = 8, 1412 .max_access_size = 8, 1413 }, 1414 .impl = { 1415 .min_access_size = 8, 1416 .max_access_size = 8, 1417 }, 1418 }; 1419 1420 /* 1421 * Notify port page. The layout is compatible between 4K and 64K pages : 1422 * 1423 * Page 1 Notify page (writes only) 1424 * 0x000 - 0x7FF IPI interrupt (NPU) 1425 * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB) 1426 */ 1427 1428 static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr, 1429 uint64_t val) 1430 { 1431 uint8_t blk; 1432 uint32_t idx; 1433 1434 if (val & XIVE_TRIGGER_END) { 1435 xive2_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1436 addr, val); 1437 return; 1438 } 1439 1440 /* 1441 * Forward the source event notification directly to the Router. 1442 * The source interrupt number should already be correctly encoded 1443 * with the chip block id by the sending device (PHB, PSI). 1444 */ 1445 blk = XIVE_EAS_BLOCK(val); 1446 idx = XIVE_EAS_INDEX(val); 1447 1448 xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx), 1449 !!(val & XIVE_TRIGGER_PQ)); 1450 } 1451 1452 static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset, 1453 uint64_t val, unsigned size) 1454 { 1455 PnvXive2 *xive = PNV_XIVE2(opaque); 1456 1457 /* VC: IPI triggers */ 1458 switch (offset) { 1459 case 0x000 ... 0x7FF: 1460 /* TODO: check IPI notify sub-page routing */ 1461 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1462 break; 1463 1464 /* VC: HW triggers */ 1465 case 0x800 ... 0xFFF: 1466 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1467 break; 1468 1469 default: 1470 xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset); 1471 } 1472 } 1473 1474 static uint64_t pnv_xive2_ic_notify_read(void *opaque, hwaddr offset, 1475 unsigned size) 1476 { 1477 PnvXive2 *xive = PNV_XIVE2(opaque); 1478 1479 /* loads are invalid */ 1480 xive2_error(xive, "NOTIFY: invalid read @%"HWADDR_PRIx, offset); 1481 return -1; 1482 } 1483 1484 static const MemoryRegionOps pnv_xive2_ic_notify_ops = { 1485 .read = pnv_xive2_ic_notify_read, 1486 .write = pnv_xive2_ic_notify_write, 1487 .endianness = DEVICE_BIG_ENDIAN, 1488 .valid = { 1489 .min_access_size = 8, 1490 .max_access_size = 8, 1491 }, 1492 .impl = { 1493 .min_access_size = 8, 1494 .max_access_size = 8, 1495 }, 1496 }; 1497 1498 static uint64_t pnv_xive2_ic_lsi_read(void *opaque, hwaddr offset, 1499 unsigned size) 1500 { 1501 PnvXive2 *xive = PNV_XIVE2(opaque); 1502 1503 xive2_error(xive, "LSI: invalid read @%"HWADDR_PRIx, offset); 1504 return -1; 1505 } 1506 1507 static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset, 1508 uint64_t val, unsigned size) 1509 { 1510 PnvXive2 *xive = PNV_XIVE2(opaque); 1511 1512 xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset); 1513 } 1514 1515 static const MemoryRegionOps pnv_xive2_ic_lsi_ops = { 1516 .read = pnv_xive2_ic_lsi_read, 1517 .write = pnv_xive2_ic_lsi_write, 1518 .endianness = DEVICE_BIG_ENDIAN, 1519 .valid = { 1520 .min_access_size = 8, 1521 .max_access_size = 8, 1522 }, 1523 .impl = { 1524 .min_access_size = 8, 1525 .max_access_size = 8, 1526 }, 1527 }; 1528 1529 /* 1530 * Sync MMIO page (write only) 1531 */ 1532 #define PNV_XIVE2_SYNC_IPI 0x000 1533 #define PNV_XIVE2_SYNC_HW 0x080 1534 #define PNV_XIVE2_SYNC_NxC 0x100 1535 #define PNV_XIVE2_SYNC_INT 0x180 1536 #define PNV_XIVE2_SYNC_OS_ESC 0x200 1537 #define PNV_XIVE2_SYNC_POOL_ESC 0x280 1538 #define PNV_XIVE2_SYNC_HARD_ESC 0x300 1539 1540 static uint64_t pnv_xive2_ic_sync_read(void *opaque, hwaddr offset, 1541 unsigned size) 1542 { 1543 PnvXive2 *xive = PNV_XIVE2(opaque); 1544 1545 /* loads are invalid */ 1546 xive2_error(xive, "SYNC: invalid read @%"HWADDR_PRIx, offset); 1547 return -1; 1548 } 1549 1550 static void pnv_xive2_ic_sync_write(void *opaque, hwaddr offset, 1551 uint64_t val, unsigned size) 1552 { 1553 PnvXive2 *xive = PNV_XIVE2(opaque); 1554 1555 switch (offset) { 1556 case PNV_XIVE2_SYNC_IPI: 1557 case PNV_XIVE2_SYNC_HW: 1558 case PNV_XIVE2_SYNC_NxC: 1559 case PNV_XIVE2_SYNC_INT: 1560 case PNV_XIVE2_SYNC_OS_ESC: 1561 case PNV_XIVE2_SYNC_POOL_ESC: 1562 case PNV_XIVE2_SYNC_HARD_ESC: 1563 break; 1564 default: 1565 xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset); 1566 } 1567 } 1568 1569 static const MemoryRegionOps pnv_xive2_ic_sync_ops = { 1570 .read = pnv_xive2_ic_sync_read, 1571 .write = pnv_xive2_ic_sync_write, 1572 .endianness = DEVICE_BIG_ENDIAN, 1573 .valid = { 1574 .min_access_size = 8, 1575 .max_access_size = 8, 1576 }, 1577 .impl = { 1578 .min_access_size = 8, 1579 .max_access_size = 8, 1580 }, 1581 }; 1582 1583 /* 1584 * When the TM direct pages of the IC controller are accessed, the 1585 * target HW thread is deduced from the page offset. 1586 */ 1587 static uint32_t pnv_xive2_ic_tm_get_pir(PnvXive2 *xive, hwaddr offset) 1588 { 1589 /* On P10, the node ID shift in the PIR register is 8 bits */ 1590 return xive->chip->chip_id << 8 | offset >> xive->ic_shift; 1591 } 1592 1593 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) 1594 { 1595 PnvChip *chip = xive->chip; 1596 PowerPCCPU *cpu = NULL; 1597 1598 cpu = pnv_chip_find_cpu(chip, pir); 1599 if (!cpu) { 1600 xive2_error(xive, "IC: invalid PIR %x for indirect access", pir); 1601 return NULL; 1602 } 1603 1604 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 1605 xive2_error(xive, "IC: CPU %x is not enabled", pir); 1606 } 1607 1608 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1609 } 1610 1611 static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset, 1612 unsigned size) 1613 { 1614 PnvXive2 *xive = PNV_XIVE2(opaque); 1615 uint32_t pir; 1616 XiveTCTX *tctx; 1617 uint64_t val = -1; 1618 1619 pir = pnv_xive2_ic_tm_get_pir(xive, offset); 1620 tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1621 if (tctx) { 1622 val = xive_tctx_tm_read(NULL, tctx, offset, size); 1623 } 1624 1625 return val; 1626 } 1627 1628 static void pnv_xive2_ic_tm_indirect_write(void *opaque, hwaddr offset, 1629 uint64_t val, unsigned size) 1630 { 1631 PnvXive2 *xive = PNV_XIVE2(opaque); 1632 uint32_t pir; 1633 XiveTCTX *tctx; 1634 1635 pir = pnv_xive2_ic_tm_get_pir(xive, offset); 1636 tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1637 if (tctx) { 1638 xive_tctx_tm_write(NULL, tctx, offset, val, size); 1639 } 1640 } 1641 1642 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = { 1643 .read = pnv_xive2_ic_tm_indirect_read, 1644 .write = pnv_xive2_ic_tm_indirect_write, 1645 .endianness = DEVICE_BIG_ENDIAN, 1646 .valid = { 1647 .min_access_size = 8, 1648 .max_access_size = 8, 1649 }, 1650 .impl = { 1651 .min_access_size = 8, 1652 .max_access_size = 8, 1653 }, 1654 }; 1655 1656 /* 1657 * TIMA ops 1658 */ 1659 static void pnv_xive2_tm_write(void *opaque, hwaddr offset, 1660 uint64_t value, unsigned size) 1661 { 1662 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1663 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1664 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1665 XivePresenter *xptr = XIVE_PRESENTER(xive); 1666 1667 xive_tctx_tm_write(xptr, tctx, offset, value, size); 1668 } 1669 1670 static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) 1671 { 1672 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1673 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1674 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1675 XivePresenter *xptr = XIVE_PRESENTER(xive); 1676 1677 return xive_tctx_tm_read(xptr, tctx, offset, size); 1678 } 1679 1680 static const MemoryRegionOps pnv_xive2_tm_ops = { 1681 .read = pnv_xive2_tm_read, 1682 .write = pnv_xive2_tm_write, 1683 .endianness = DEVICE_BIG_ENDIAN, 1684 .valid = { 1685 .min_access_size = 1, 1686 .max_access_size = 8, 1687 }, 1688 .impl = { 1689 .min_access_size = 1, 1690 .max_access_size = 8, 1691 }, 1692 }; 1693 1694 static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset, 1695 unsigned size) 1696 { 1697 PnvXive2 *xive = PNV_XIVE2(opaque); 1698 1699 xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset); 1700 return -1; 1701 } 1702 1703 static void pnv_xive2_nvc_write(void *opaque, hwaddr offset, 1704 uint64_t val, unsigned size) 1705 { 1706 PnvXive2 *xive = PNV_XIVE2(opaque); 1707 1708 xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset); 1709 } 1710 1711 static const MemoryRegionOps pnv_xive2_nvc_ops = { 1712 .read = pnv_xive2_nvc_read, 1713 .write = pnv_xive2_nvc_write, 1714 .endianness = DEVICE_BIG_ENDIAN, 1715 .valid = { 1716 .min_access_size = 8, 1717 .max_access_size = 8, 1718 }, 1719 .impl = { 1720 .min_access_size = 8, 1721 .max_access_size = 8, 1722 }, 1723 }; 1724 1725 static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset, 1726 unsigned size) 1727 { 1728 PnvXive2 *xive = PNV_XIVE2(opaque); 1729 1730 xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset); 1731 return -1; 1732 } 1733 1734 static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset, 1735 uint64_t val, unsigned size) 1736 { 1737 PnvXive2 *xive = PNV_XIVE2(opaque); 1738 1739 xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset); 1740 } 1741 1742 static const MemoryRegionOps pnv_xive2_nvpg_ops = { 1743 .read = pnv_xive2_nvpg_read, 1744 .write = pnv_xive2_nvpg_write, 1745 .endianness = DEVICE_BIG_ENDIAN, 1746 .valid = { 1747 .min_access_size = 8, 1748 .max_access_size = 8, 1749 }, 1750 .impl = { 1751 .min_access_size = 8, 1752 .max_access_size = 8, 1753 }, 1754 }; 1755 1756 /* 1757 * POWER10 default capabilities: 0x2000120076f000FC 1758 */ 1759 #define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC 1760 1761 /* 1762 * POWER10 default configuration: 0x0030000033000000 1763 * 1764 * 8bits thread id was dropped for P10 1765 */ 1766 #define PNV_XIVE2_CONFIGURATION 0x0030000033000000 1767 1768 static void pnv_xive2_reset(void *dev) 1769 { 1770 PnvXive2 *xive = PNV_XIVE2(dev); 1771 XiveSource *xsrc = &xive->ipi_source; 1772 Xive2EndSource *end_xsrc = &xive->end_source; 1773 1774 xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities; 1775 xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config; 1776 1777 /* HW hardwires the #Topology of the chip in the block field */ 1778 xive->cq_regs[CQ_XIVE_CFG >> 3] |= 1779 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id); 1780 1781 /* Set default page size to 64k */ 1782 xive->ic_shift = xive->esb_shift = xive->end_shift = 16; 1783 xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16; 1784 1785 /* Clear source MMIOs */ 1786 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 1787 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); 1788 } 1789 1790 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 1791 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); 1792 } 1793 } 1794 1795 /* 1796 * Maximum number of IRQs and ENDs supported by HW. Will be tuned by 1797 * software. 1798 */ 1799 #define PNV_XIVE2_NR_IRQS (PNV10_XIVE2_ESB_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1800 #define PNV_XIVE2_NR_ENDS (PNV10_XIVE2_END_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1801 1802 static void pnv_xive2_realize(DeviceState *dev, Error **errp) 1803 { 1804 PnvXive2 *xive = PNV_XIVE2(dev); 1805 PnvXive2Class *pxc = PNV_XIVE2_GET_CLASS(dev); 1806 XiveSource *xsrc = &xive->ipi_source; 1807 Xive2EndSource *end_xsrc = &xive->end_source; 1808 Error *local_err = NULL; 1809 int i; 1810 1811 pxc->parent_realize(dev, &local_err); 1812 if (local_err) { 1813 error_propagate(errp, local_err); 1814 return; 1815 } 1816 1817 assert(xive->chip); 1818 1819 /* 1820 * The XiveSource and Xive2EndSource objects are realized with the 1821 * maximum allowed HW configuration. The ESB MMIO regions will be 1822 * resized dynamically when the controller is configured by the FW 1823 * to limit accesses to resources not provisioned. 1824 */ 1825 object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI, 1826 &error_fatal); 1827 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS, 1828 &error_fatal); 1829 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), 1830 &error_fatal); 1831 qdev_realize(DEVICE(xsrc), NULL, &local_err); 1832 if (local_err) { 1833 error_propagate(errp, local_err); 1834 return; 1835 } 1836 1837 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS, 1838 &error_fatal); 1839 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 1840 &error_abort); 1841 qdev_realize(DEVICE(end_xsrc), NULL, &local_err); 1842 if (local_err) { 1843 error_propagate(errp, local_err); 1844 return; 1845 } 1846 1847 /* XSCOM region, used for initial configuration of the BARs */ 1848 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), 1849 &pnv_xive2_xscom_ops, xive, "xscom-xive", 1850 PNV10_XSCOM_XIVE2_SIZE << 3); 1851 1852 /* Interrupt controller MMIO regions */ 1853 xive->ic_shift = 16; 1854 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 1855 PNV10_XIVE2_IC_SIZE); 1856 1857 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 1858 memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev), 1859 pnv_xive2_ic_regions[i].ops, xive, 1860 pnv_xive2_ic_regions[i].name, 1861 pnv_xive2_ic_regions[i].pgsize << xive->ic_shift); 1862 } 1863 1864 /* 1865 * VC MMIO regions. 1866 */ 1867 xive->esb_shift = 16; 1868 xive->end_shift = 16; 1869 memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb", 1870 PNV10_XIVE2_ESB_SIZE); 1871 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end", 1872 PNV10_XIVE2_END_SIZE); 1873 1874 /* Presenter Controller MMIO region (not modeled) */ 1875 xive->nvc_shift = 16; 1876 xive->nvpg_shift = 16; 1877 memory_region_init_io(&xive->nvc_mmio, OBJECT(dev), 1878 &pnv_xive2_nvc_ops, xive, 1879 "xive-nvc", PNV10_XIVE2_NVC_SIZE); 1880 1881 memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev), 1882 &pnv_xive2_nvpg_ops, xive, 1883 "xive-nvpg", PNV10_XIVE2_NVPG_SIZE); 1884 1885 /* Thread Interrupt Management Area (Direct) */ 1886 xive->tm_shift = 16; 1887 memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops, 1888 xive, "xive-tima", PNV10_XIVE2_TM_SIZE); 1889 1890 qemu_register_reset(pnv_xive2_reset, dev); 1891 } 1892 1893 static Property pnv_xive2_properties[] = { 1894 DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0), 1895 DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0), 1896 DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0), 1897 DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0), 1898 DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0), 1899 DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0), 1900 DEFINE_PROP_UINT64("capabilities", PnvXive2, capabilities, 1901 PNV_XIVE2_CAPABILITIES), 1902 DEFINE_PROP_UINT64("config", PnvXive2, config, 1903 PNV_XIVE2_CONFIGURATION), 1904 DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *), 1905 DEFINE_PROP_END_OF_LIST(), 1906 }; 1907 1908 static void pnv_xive2_instance_init(Object *obj) 1909 { 1910 PnvXive2 *xive = PNV_XIVE2(obj); 1911 1912 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 1913 TYPE_XIVE_SOURCE); 1914 object_initialize_child(obj, "end_source", &xive->end_source, 1915 TYPE_XIVE2_END_SOURCE); 1916 } 1917 1918 static int pnv_xive2_dt_xscom(PnvXScomInterface *dev, void *fdt, 1919 int xscom_offset) 1920 { 1921 const char compat_p10[] = "ibm,power10-xive-x"; 1922 char *name; 1923 int offset; 1924 uint32_t reg[] = { 1925 cpu_to_be32(PNV10_XSCOM_XIVE2_BASE), 1926 cpu_to_be32(PNV10_XSCOM_XIVE2_SIZE) 1927 }; 1928 1929 name = g_strdup_printf("xive@%x", PNV10_XSCOM_XIVE2_BASE); 1930 offset = fdt_add_subnode(fdt, xscom_offset, name); 1931 _FDT(offset); 1932 g_free(name); 1933 1934 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 1935 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, 1936 sizeof(compat_p10))); 1937 return 0; 1938 } 1939 1940 static void pnv_xive2_class_init(ObjectClass *klass, void *data) 1941 { 1942 DeviceClass *dc = DEVICE_CLASS(klass); 1943 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 1944 Xive2RouterClass *xrc = XIVE2_ROUTER_CLASS(klass); 1945 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1946 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 1947 PnvXive2Class *pxc = PNV_XIVE2_CLASS(klass); 1948 1949 xdc->dt_xscom = pnv_xive2_dt_xscom; 1950 1951 dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)"; 1952 device_class_set_parent_realize(dc, pnv_xive2_realize, 1953 &pxc->parent_realize); 1954 device_class_set_props(dc, pnv_xive2_properties); 1955 1956 xrc->get_eas = pnv_xive2_get_eas; 1957 xrc->get_pq = pnv_xive2_get_pq; 1958 xrc->set_pq = pnv_xive2_set_pq; 1959 xrc->get_end = pnv_xive2_get_end; 1960 xrc->write_end = pnv_xive2_write_end; 1961 xrc->get_nvp = pnv_xive2_get_nvp; 1962 xrc->write_nvp = pnv_xive2_write_nvp; 1963 xrc->get_config = pnv_xive2_get_config; 1964 xrc->get_block_id = pnv_xive2_get_block_id; 1965 1966 xnc->notify = pnv_xive2_notify; 1967 1968 xpc->match_nvt = pnv_xive2_match_nvt; 1969 xpc->get_config = pnv_xive2_presenter_get_config; 1970 }; 1971 1972 static const TypeInfo pnv_xive2_info = { 1973 .name = TYPE_PNV_XIVE2, 1974 .parent = TYPE_XIVE2_ROUTER, 1975 .instance_init = pnv_xive2_instance_init, 1976 .instance_size = sizeof(PnvXive2), 1977 .class_init = pnv_xive2_class_init, 1978 .class_size = sizeof(PnvXive2Class), 1979 .interfaces = (InterfaceInfo[]) { 1980 { TYPE_PNV_XSCOM_INTERFACE }, 1981 { } 1982 } 1983 }; 1984 1985 static void pnv_xive2_register_types(void) 1986 { 1987 type_register_static(&pnv_xive2_info); 1988 } 1989 1990 type_init(pnv_xive2_register_types) 1991 1992 static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, 1993 Monitor *mon) 1994 { 1995 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 1996 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 1997 1998 if (!xive2_nvp_is_valid(nvp)) { 1999 return; 2000 } 2001 2002 monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x", 2003 nvp_idx, eq_blk, eq_idx, 2004 xive_get_field32(NVP2_W2_IPB, nvp->w2)); 2005 /* 2006 * When the NVP is HW controlled, more fields are updated 2007 */ 2008 if (xive2_nvp_is_hw(nvp)) { 2009 monitor_printf(mon, " CPPR:%02x", 2010 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 2011 if (xive2_nvp_is_co(nvp)) { 2012 monitor_printf(mon, " CO:%04x", 2013 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 2014 } 2015 } 2016 monitor_printf(mon, "\n"); 2017 } 2018 2019 /* 2020 * If the table is direct, we can compute the number of PQ entries 2021 * provisioned by FW. 2022 */ 2023 static uint32_t pnv_xive2_nr_esbs(PnvXive2 *xive) 2024 { 2025 uint8_t blk = pnv_xive2_block_id(xive); 2026 uint64_t vsd = xive->vsds[VST_ESB][blk]; 2027 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 2028 2029 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 2030 } 2031 2032 /* 2033 * Compute the number of entries per indirect subpage. 2034 */ 2035 static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type) 2036 { 2037 uint8_t blk = pnv_xive2_block_id(xive); 2038 uint64_t vsd = xive->vsds[type][blk]; 2039 const XiveVstInfo *info = &vst_infos[type]; 2040 uint64_t vsd_addr; 2041 uint32_t page_shift; 2042 2043 /* For direct tables, fake a valid value */ 2044 if (!(VSD_INDIRECT & vsd)) { 2045 return 1; 2046 } 2047 2048 /* Get the page size of the indirect table. */ 2049 vsd_addr = vsd & VSD_ADDRESS_MASK; 2050 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 2051 2052 if (!(vsd & VSD_ADDRESS_MASK)) { 2053 #ifdef XIVE2_DEBUG 2054 xive2_error(xive, "VST: invalid %s entry!?", info->name); 2055 #endif 2056 return 0; 2057 } 2058 2059 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 2060 2061 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 2062 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 2063 page_shift); 2064 return 0; 2065 } 2066 2067 return (1ull << page_shift) / info->size; 2068 } 2069 2070 void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon) 2071 { 2072 Xive2Router *xrtr = XIVE2_ROUTER(xive); 2073 uint8_t blk = pnv_xive2_block_id(xive); 2074 uint8_t chip_id = xive->chip->chip_id; 2075 uint32_t srcno0 = XIVE_EAS(blk, 0); 2076 uint32_t nr_esbs = pnv_xive2_nr_esbs(xive); 2077 Xive2Eas eas; 2078 Xive2End end; 2079 Xive2Nvp nvp; 2080 int i; 2081 uint64_t xive_nvp_per_subpage; 2082 2083 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, 2084 srcno0 + nr_esbs - 1); 2085 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); 2086 2087 monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, 2088 srcno0 + nr_esbs - 1); 2089 for (i = 0; i < nr_esbs; i++) { 2090 if (xive2_router_get_eas(xrtr, blk, i, &eas)) { 2091 break; 2092 } 2093 if (!xive2_eas_is_masked(&eas)) { 2094 xive2_eas_pic_print_info(&eas, i, mon); 2095 } 2096 } 2097 2098 monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); 2099 i = 0; 2100 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2101 xive2_end_eas_pic_print_info(&end, i++, mon); 2102 } 2103 2104 monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); 2105 i = 0; 2106 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2107 xive2_end_pic_print_info(&end, i++, mon); 2108 } 2109 2110 monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk, 2111 0, XIVE2_NVP_COUNT - 1); 2112 xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); 2113 for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) { 2114 while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) { 2115 xive2_nvp_pic_print_info(&nvp, i++, mon); 2116 } 2117 } 2118 } 2119