1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "monitor/monitor.h" 19 #include "hw/ppc/fdt.h" 20 #include "hw/ppc/pnv.h" 21 #include "hw/ppc/pnv_core.h" 22 #include "hw/ppc/pnv_xscom.h" 23 #include "hw/ppc/pnv_xive.h" 24 #include "hw/ppc/xive_regs.h" 25 #include "hw/qdev-properties.h" 26 #include "hw/ppc/ppc.h" 27 28 #include <libfdt.h> 29 30 #include "pnv_xive_regs.h" 31 32 #undef XIVE_DEBUG 33 34 /* 35 * Virtual structures table (VST) 36 */ 37 #define SBE_PER_BYTE 4 38 39 typedef struct XiveVstInfo { 40 const char *name; 41 uint32_t size; 42 uint32_t max_blocks; 43 } XiveVstInfo; 44 45 static const XiveVstInfo vst_infos[] = { 46 [VST_TSEL_IVT] = { "EAT", sizeof(XiveEAS), 16 }, 47 [VST_TSEL_SBE] = { "SBE", 1, 16 }, 48 [VST_TSEL_EQDT] = { "ENDT", sizeof(XiveEND), 16 }, 49 [VST_TSEL_VPDT] = { "VPDT", sizeof(XiveNVT), 32 }, 50 51 /* 52 * Interrupt fifo backing store table (not modeled) : 53 * 54 * 0 - IPI, 55 * 1 - HWD, 56 * 2 - First escalate, 57 * 3 - Second escalate, 58 * 4 - Redistribution, 59 * 5 - IPI cascaded queue ? 60 */ 61 [VST_TSEL_IRQ] = { "IRQ", 1, 6 }, 62 }; 63 64 #define xive_error(xive, fmt, ...) \ 65 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 66 (xive)->chip->chip_id, ## __VA_ARGS__); 67 68 /* 69 * QEMU version of the GETFIELD/SETFIELD macros 70 * 71 * TODO: It might be better to use the existing extract64() and 72 * deposit64() but this means that all the register definitions will 73 * change and become incompatible with the ones found in skiboot. 74 * 75 * Keep it as it is for now until we find a common ground. 76 */ 77 static inline uint64_t GETFIELD(uint64_t mask, uint64_t word) 78 { 79 return (word & mask) >> ctz64(mask); 80 } 81 82 static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, 83 uint64_t value) 84 { 85 return (word & ~mask) | ((value << ctz64(mask)) & mask); 86 } 87 88 /* 89 * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID 90 * field overrides the hardwired chip ID in the Powerbus operations 91 * and for CAM compares 92 */ 93 static uint8_t pnv_xive_block_id(PnvXive *xive) 94 { 95 uint8_t blk = xive->chip->chip_id; 96 uint64_t cfg_val = xive->regs[PC_TCTXT_CFG >> 3]; 97 98 if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) { 99 blk = GETFIELD(PC_TCTXT_CHIPID, cfg_val); 100 } 101 102 return blk; 103 } 104 105 /* 106 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 107 * of the chips is good enough. 108 * 109 * TODO: Block scope support 110 */ 111 static PnvXive *pnv_xive_get_remote(uint8_t blk) 112 { 113 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 114 int i; 115 116 for (i = 0; i < pnv->num_chips; i++) { 117 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 118 PnvXive *xive = &chip9->xive; 119 120 if (pnv_xive_block_id(xive) == blk) { 121 return xive; 122 } 123 } 124 return NULL; 125 } 126 127 /* 128 * VST accessors for SBE, EAT, ENDT, NVT 129 * 130 * Indirect VST tables are arrays of VSDs pointing to a page (of same 131 * size). Each page is a direct VST table. 132 */ 133 134 #define XIVE_VSD_SIZE 8 135 136 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 137 static uint64_t pnv_xive_vst_page_size_allowed(uint32_t page_shift) 138 { 139 return page_shift == 12 || page_shift == 16 || 140 page_shift == 21 || page_shift == 24; 141 } 142 143 static uint64_t pnv_xive_vst_addr_direct(PnvXive *xive, uint32_t type, 144 uint64_t vsd, uint32_t idx) 145 { 146 const XiveVstInfo *info = &vst_infos[type]; 147 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 148 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 149 uint32_t idx_max; 150 151 idx_max = vst_tsize / info->size - 1; 152 if (idx > idx_max) { 153 #ifdef XIVE_DEBUG 154 xive_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 155 info->name, idx, idx_max); 156 #endif 157 return 0; 158 } 159 160 return vst_addr + idx * info->size; 161 } 162 163 static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xive, uint32_t type, 164 uint64_t vsd, uint32_t idx) 165 { 166 const XiveVstInfo *info = &vst_infos[type]; 167 uint64_t vsd_addr; 168 uint32_t vsd_idx; 169 uint32_t page_shift; 170 uint32_t vst_per_page; 171 172 /* Get the page size of the indirect table. */ 173 vsd_addr = vsd & VSD_ADDRESS_MASK; 174 vsd = ldq_be_dma(&address_space_memory, vsd_addr); 175 176 if (!(vsd & VSD_ADDRESS_MASK)) { 177 #ifdef XIVE_DEBUG 178 xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 179 #endif 180 return 0; 181 } 182 183 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 184 185 if (!pnv_xive_vst_page_size_allowed(page_shift)) { 186 xive_error(xive, "VST: invalid %s page shift %d", info->name, 187 page_shift); 188 return 0; 189 } 190 191 vst_per_page = (1ull << page_shift) / info->size; 192 vsd_idx = idx / vst_per_page; 193 194 /* Load the VSD we are looking for, if not already done */ 195 if (vsd_idx) { 196 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 197 vsd = ldq_be_dma(&address_space_memory, vsd_addr); 198 199 if (!(vsd & VSD_ADDRESS_MASK)) { 200 #ifdef XIVE_DEBUG 201 xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 202 #endif 203 return 0; 204 } 205 206 /* 207 * Check that the pages have a consistent size across the 208 * indirect table 209 */ 210 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 211 xive_error(xive, "VST: %s entry %x indirect page size differ !?", 212 info->name, idx); 213 return 0; 214 } 215 } 216 217 return pnv_xive_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 218 } 219 220 static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk, 221 uint32_t idx) 222 { 223 const XiveVstInfo *info = &vst_infos[type]; 224 uint64_t vsd; 225 226 if (blk >= info->max_blocks) { 227 xive_error(xive, "VST: invalid block id %d for VST %s %d !?", 228 blk, info->name, idx); 229 return 0; 230 } 231 232 vsd = xive->vsds[type][blk]; 233 234 /* Remote VST access */ 235 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 236 xive = pnv_xive_get_remote(blk); 237 238 return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; 239 } 240 241 if (VSD_INDIRECT & vsd) { 242 return pnv_xive_vst_addr_indirect(xive, type, vsd, idx); 243 } 244 245 return pnv_xive_vst_addr_direct(xive, type, vsd, idx); 246 } 247 248 static int pnv_xive_vst_read(PnvXive *xive, uint32_t type, uint8_t blk, 249 uint32_t idx, void *data) 250 { 251 const XiveVstInfo *info = &vst_infos[type]; 252 uint64_t addr = pnv_xive_vst_addr(xive, type, blk, idx); 253 254 if (!addr) { 255 return -1; 256 } 257 258 cpu_physical_memory_read(addr, data, info->size); 259 return 0; 260 } 261 262 #define XIVE_VST_WORD_ALL -1 263 264 static int pnv_xive_vst_write(PnvXive *xive, uint32_t type, uint8_t blk, 265 uint32_t idx, void *data, uint32_t word_number) 266 { 267 const XiveVstInfo *info = &vst_infos[type]; 268 uint64_t addr = pnv_xive_vst_addr(xive, type, blk, idx); 269 270 if (!addr) { 271 return -1; 272 } 273 274 if (word_number == XIVE_VST_WORD_ALL) { 275 cpu_physical_memory_write(addr, data, info->size); 276 } else { 277 cpu_physical_memory_write(addr + word_number * 4, 278 data + word_number * 4, 4); 279 } 280 return 0; 281 } 282 283 static int pnv_xive_get_end(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 284 XiveEND *end) 285 { 286 return pnv_xive_vst_read(PNV_XIVE(xrtr), VST_TSEL_EQDT, blk, idx, end); 287 } 288 289 static int pnv_xive_write_end(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 290 XiveEND *end, uint8_t word_number) 291 { 292 return pnv_xive_vst_write(PNV_XIVE(xrtr), VST_TSEL_EQDT, blk, idx, end, 293 word_number); 294 } 295 296 static int pnv_xive_end_update(PnvXive *xive) 297 { 298 uint8_t blk = GETFIELD(VC_EQC_CWATCH_BLOCKID, 299 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 300 uint32_t idx = GETFIELD(VC_EQC_CWATCH_OFFSET, 301 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 302 int i; 303 uint64_t eqc_watch[4]; 304 305 for (i = 0; i < ARRAY_SIZE(eqc_watch); i++) { 306 eqc_watch[i] = cpu_to_be64(xive->regs[(VC_EQC_CWATCH_DAT0 >> 3) + i]); 307 } 308 309 return pnv_xive_vst_write(xive, VST_TSEL_EQDT, blk, idx, eqc_watch, 310 XIVE_VST_WORD_ALL); 311 } 312 313 static void pnv_xive_end_cache_load(PnvXive *xive) 314 { 315 uint8_t blk = GETFIELD(VC_EQC_CWATCH_BLOCKID, 316 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 317 uint32_t idx = GETFIELD(VC_EQC_CWATCH_OFFSET, 318 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 319 uint64_t eqc_watch[4] = { 0 }; 320 int i; 321 322 if (pnv_xive_vst_read(xive, VST_TSEL_EQDT, blk, idx, eqc_watch)) { 323 xive_error(xive, "VST: no END entry %x/%x !?", blk, idx); 324 } 325 326 for (i = 0; i < ARRAY_SIZE(eqc_watch); i++) { 327 xive->regs[(VC_EQC_CWATCH_DAT0 >> 3) + i] = be64_to_cpu(eqc_watch[i]); 328 } 329 } 330 331 static int pnv_xive_get_nvt(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 332 XiveNVT *nvt) 333 { 334 return pnv_xive_vst_read(PNV_XIVE(xrtr), VST_TSEL_VPDT, blk, idx, nvt); 335 } 336 337 static int pnv_xive_write_nvt(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 338 XiveNVT *nvt, uint8_t word_number) 339 { 340 return pnv_xive_vst_write(PNV_XIVE(xrtr), VST_TSEL_VPDT, blk, idx, nvt, 341 word_number); 342 } 343 344 static int pnv_xive_nvt_update(PnvXive *xive) 345 { 346 uint8_t blk = GETFIELD(PC_VPC_CWATCH_BLOCKID, 347 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 348 uint32_t idx = GETFIELD(PC_VPC_CWATCH_OFFSET, 349 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 350 int i; 351 uint64_t vpc_watch[8]; 352 353 for (i = 0; i < ARRAY_SIZE(vpc_watch); i++) { 354 vpc_watch[i] = cpu_to_be64(xive->regs[(PC_VPC_CWATCH_DAT0 >> 3) + i]); 355 } 356 357 return pnv_xive_vst_write(xive, VST_TSEL_VPDT, blk, idx, vpc_watch, 358 XIVE_VST_WORD_ALL); 359 } 360 361 static void pnv_xive_nvt_cache_load(PnvXive *xive) 362 { 363 uint8_t blk = GETFIELD(PC_VPC_CWATCH_BLOCKID, 364 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 365 uint32_t idx = GETFIELD(PC_VPC_CWATCH_OFFSET, 366 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 367 uint64_t vpc_watch[8] = { 0 }; 368 int i; 369 370 if (pnv_xive_vst_read(xive, VST_TSEL_VPDT, blk, idx, vpc_watch)) { 371 xive_error(xive, "VST: no NVT entry %x/%x !?", blk, idx); 372 } 373 374 for (i = 0; i < ARRAY_SIZE(vpc_watch); i++) { 375 xive->regs[(PC_VPC_CWATCH_DAT0 >> 3) + i] = be64_to_cpu(vpc_watch[i]); 376 } 377 } 378 379 static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 380 XiveEAS *eas) 381 { 382 PnvXive *xive = PNV_XIVE(xrtr); 383 384 /* 385 * EAT lookups should be local to the IC 386 */ 387 if (pnv_xive_block_id(xive) != blk) { 388 xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 389 return -1; 390 } 391 392 return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); 393 } 394 395 /* 396 * One bit per thread id. The first register PC_THREAD_EN_REG0 covers 397 * the first cores 0-15 (normal) of the chip or 0-7 (fused). The 398 * second register covers cores 16-23 (normal) or 8-11 (fused). 399 */ 400 static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu) 401 { 402 int pir = ppc_cpu_pir(cpu); 403 uint32_t fc = PNV9_PIR2FUSEDCORE(pir); 404 uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1; 405 uint32_t bit = pir & 0x3f; 406 407 return xive->regs[reg >> 3] & PPC_BIT(bit); 408 } 409 410 static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, 411 uint8_t nvt_blk, uint32_t nvt_idx, 412 bool cam_ignore, uint8_t priority, 413 uint32_t logic_serv, XiveTCTXMatch *match) 414 { 415 PnvXive *xive = PNV_XIVE(xptr); 416 PnvChip *chip = xive->chip; 417 int count = 0; 418 int i, j; 419 420 for (i = 0; i < chip->nr_cores; i++) { 421 PnvCore *pc = chip->cores[i]; 422 CPUCore *cc = CPU_CORE(pc); 423 424 for (j = 0; j < cc->nr_threads; j++) { 425 PowerPCCPU *cpu = pc->threads[j]; 426 XiveTCTX *tctx; 427 int ring; 428 429 if (!pnv_xive_is_cpu_enabled(xive, cpu)) { 430 continue; 431 } 432 433 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 434 435 /* 436 * Check the thread context CAM lines and record matches. 437 */ 438 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, 439 nvt_idx, cam_ignore, logic_serv); 440 /* 441 * Save the context and follow on to catch duplicates, that we 442 * don't support yet. 443 */ 444 if (ring != -1) { 445 if (match->tctx) { 446 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 447 "thread context NVT %x/%x\n", 448 nvt_blk, nvt_idx); 449 return -1; 450 } 451 452 match->ring = ring; 453 match->tctx = tctx; 454 count++; 455 } 456 } 457 } 458 459 return count; 460 } 461 462 static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) 463 { 464 return pnv_xive_block_id(PNV_XIVE(xrtr)); 465 } 466 467 /* 468 * The TIMA MMIO space is shared among the chips and to identify the 469 * chip from which the access is being done, we extract the chip id 470 * from the PIR. 471 */ 472 static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) 473 { 474 int pir = ppc_cpu_pir(cpu); 475 PnvChip *chip; 476 PnvXive *xive; 477 478 chip = pnv_get_chip(PNV9_PIR2CHIP(pir)); 479 assert(chip); 480 xive = &PNV9_CHIP(chip)->xive; 481 482 if (!pnv_xive_is_cpu_enabled(xive, cpu)) { 483 xive_error(xive, "IC: CPU %x is not enabled", pir); 484 } 485 return xive; 486 } 487 488 /* 489 * The internal sources (IPIs) of the interrupt controller have no 490 * knowledge of the XIVE chip on which they reside. Encode the block 491 * id in the source interrupt number before forwarding the source 492 * event notification to the Router. This is required on a multichip 493 * system. 494 */ 495 static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno) 496 { 497 PnvXive *xive = PNV_XIVE(xn); 498 uint8_t blk = pnv_xive_block_id(xive); 499 500 xive_router_notify(xn, XIVE_EAS(blk, srcno)); 501 } 502 503 /* 504 * XIVE helpers 505 */ 506 507 static uint64_t pnv_xive_vc_size(PnvXive *xive) 508 { 509 return (~xive->regs[CQ_VC_BARM >> 3] + 1) & CQ_VC_BARM_MASK; 510 } 511 512 static uint64_t pnv_xive_edt_shift(PnvXive *xive) 513 { 514 return ctz64(pnv_xive_vc_size(xive) / XIVE_TABLE_EDT_MAX); 515 } 516 517 static uint64_t pnv_xive_pc_size(PnvXive *xive) 518 { 519 return (~xive->regs[CQ_PC_BARM >> 3] + 1) & CQ_PC_BARM_MASK; 520 } 521 522 static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk) 523 { 524 uint64_t vsd = xive->vsds[VST_TSEL_SBE][blk]; 525 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 526 527 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 528 } 529 530 /* 531 * EDT Table 532 * 533 * The Virtualization Controller MMIO region containing the IPI ESB 534 * pages and END ESB pages is sub-divided into "sets" which map 535 * portions of the VC region to the different ESB pages. It is 536 * configured at runtime through the EDT "Domain Table" to let the 537 * firmware decide how to split the VC address space between IPI ESB 538 * pages and END ESB pages. 539 */ 540 541 /* 542 * Computes the overall size of the IPI or the END ESB pages 543 */ 544 static uint64_t pnv_xive_edt_size(PnvXive *xive, uint64_t type) 545 { 546 uint64_t edt_size = 1ull << pnv_xive_edt_shift(xive); 547 uint64_t size = 0; 548 int i; 549 550 for (i = 0; i < XIVE_TABLE_EDT_MAX; i++) { 551 uint64_t edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[i]); 552 553 if (edt_type == type) { 554 size += edt_size; 555 } 556 } 557 558 return size; 559 } 560 561 /* 562 * Maps an offset of the VC region in the IPI or END region using the 563 * layout defined by the EDT "Domaine Table" 564 */ 565 static uint64_t pnv_xive_edt_offset(PnvXive *xive, uint64_t vc_offset, 566 uint64_t type) 567 { 568 int i; 569 uint64_t edt_size = 1ull << pnv_xive_edt_shift(xive); 570 uint64_t edt_offset = vc_offset; 571 572 for (i = 0; i < XIVE_TABLE_EDT_MAX && (i * edt_size) < vc_offset; i++) { 573 uint64_t edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[i]); 574 575 if (edt_type != type) { 576 edt_offset -= edt_size; 577 } 578 } 579 580 return edt_offset; 581 } 582 583 static void pnv_xive_edt_resize(PnvXive *xive) 584 { 585 uint64_t ipi_edt_size = pnv_xive_edt_size(xive, CQ_TDR_EDT_IPI); 586 uint64_t end_edt_size = pnv_xive_edt_size(xive, CQ_TDR_EDT_EQ); 587 588 memory_region_set_size(&xive->ipi_edt_mmio, ipi_edt_size); 589 memory_region_add_subregion(&xive->ipi_mmio, 0, &xive->ipi_edt_mmio); 590 591 memory_region_set_size(&xive->end_edt_mmio, end_edt_size); 592 memory_region_add_subregion(&xive->end_mmio, 0, &xive->end_edt_mmio); 593 } 594 595 /* 596 * XIVE Table configuration. Only EDT is supported. 597 */ 598 static int pnv_xive_table_set_data(PnvXive *xive, uint64_t val) 599 { 600 uint64_t tsel = xive->regs[CQ_TAR >> 3] & CQ_TAR_TSEL; 601 uint8_t tsel_index = GETFIELD(CQ_TAR_TSEL_INDEX, xive->regs[CQ_TAR >> 3]); 602 uint64_t *xive_table; 603 uint8_t max_index; 604 605 switch (tsel) { 606 case CQ_TAR_TSEL_BLK: 607 max_index = ARRAY_SIZE(xive->blk); 608 xive_table = xive->blk; 609 break; 610 case CQ_TAR_TSEL_MIG: 611 max_index = ARRAY_SIZE(xive->mig); 612 xive_table = xive->mig; 613 break; 614 case CQ_TAR_TSEL_EDT: 615 max_index = ARRAY_SIZE(xive->edt); 616 xive_table = xive->edt; 617 break; 618 case CQ_TAR_TSEL_VDT: 619 max_index = ARRAY_SIZE(xive->vdt); 620 xive_table = xive->vdt; 621 break; 622 default: 623 xive_error(xive, "IC: invalid table %d", (int) tsel); 624 return -1; 625 } 626 627 if (tsel_index >= max_index) { 628 xive_error(xive, "IC: invalid index %d", (int) tsel_index); 629 return -1; 630 } 631 632 xive_table[tsel_index] = val; 633 634 if (xive->regs[CQ_TAR >> 3] & CQ_TAR_TBL_AUTOINC) { 635 xive->regs[CQ_TAR >> 3] = 636 SETFIELD(CQ_TAR_TSEL_INDEX, xive->regs[CQ_TAR >> 3], ++tsel_index); 637 } 638 639 /* 640 * EDT configuration is complete. Resize the MMIO windows exposing 641 * the IPI and the END ESBs in the VC region. 642 */ 643 if (tsel == CQ_TAR_TSEL_EDT && tsel_index == ARRAY_SIZE(xive->edt)) { 644 pnv_xive_edt_resize(xive); 645 } 646 647 return 0; 648 } 649 650 /* 651 * Virtual Structure Tables (VST) configuration 652 */ 653 static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type, 654 uint8_t blk, uint64_t vsd) 655 { 656 XiveENDSource *end_xsrc = &xive->end_source; 657 XiveSource *xsrc = &xive->ipi_source; 658 const XiveVstInfo *info = &vst_infos[type]; 659 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 660 uint64_t vst_tsize = 1ull << page_shift; 661 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 662 663 /* Basic checks */ 664 665 if (VSD_INDIRECT & vsd) { 666 if (!(xive->regs[VC_GLOBAL_CONFIG >> 3] & VC_GCONF_INDIRECT)) { 667 xive_error(xive, "VST: %s indirect tables are not enabled", 668 info->name); 669 return; 670 } 671 672 if (!pnv_xive_vst_page_size_allowed(page_shift)) { 673 xive_error(xive, "VST: invalid %s page shift %d", info->name, 674 page_shift); 675 return; 676 } 677 } 678 679 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 680 xive_error(xive, "VST: %s table address 0x%"PRIx64" is not aligned with" 681 " page shift %d", info->name, vst_addr, page_shift); 682 return; 683 } 684 685 /* Record the table configuration (in SRAM on HW) */ 686 xive->vsds[type][blk] = vsd; 687 688 /* Now tune the models with the configuration provided by the FW */ 689 690 switch (type) { 691 case VST_TSEL_IVT: /* Nothing to be done */ 692 break; 693 694 case VST_TSEL_EQDT: 695 /* 696 * Backing store pages for the END. 697 * 698 * If the table is direct, we can compute the number of PQ 699 * entries provisioned by FW (such as skiboot) and resize the 700 * END ESB window accordingly. 701 */ 702 if (!(VSD_INDIRECT & vsd)) { 703 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 704 * (1ull << xsrc->esb_shift)); 705 } 706 memory_region_add_subregion(&xive->end_edt_mmio, 0, 707 &end_xsrc->esb_mmio); 708 break; 709 710 case VST_TSEL_SBE: 711 /* 712 * Backing store pages for the source PQ bits. The model does 713 * not use these PQ bits backed in RAM because the XiveSource 714 * model has its own. 715 * 716 * If the table is direct, we can compute the number of PQ 717 * entries provisioned by FW (such as skiboot) and resize the 718 * ESB window accordingly. 719 */ 720 if (!(VSD_INDIRECT & vsd)) { 721 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 722 * (1ull << xsrc->esb_shift)); 723 } 724 memory_region_add_subregion(&xive->ipi_edt_mmio, 0, &xsrc->esb_mmio); 725 break; 726 727 case VST_TSEL_VPDT: /* Not modeled */ 728 case VST_TSEL_IRQ: /* Not modeled */ 729 /* 730 * These tables contains the backing store pages for the 731 * interrupt fifos of the VC sub-engine in case of overflow. 732 */ 733 break; 734 735 default: 736 g_assert_not_reached(); 737 } 738 } 739 740 /* 741 * Both PC and VC sub-engines are configured as each use the Virtual 742 * Structure Tables : SBE, EAS, END and NVT. 743 */ 744 static void pnv_xive_vst_set_data(PnvXive *xive, uint64_t vsd, bool pc_engine) 745 { 746 uint8_t mode = GETFIELD(VSD_MODE, vsd); 747 uint8_t type = GETFIELD(VST_TABLE_SELECT, 748 xive->regs[VC_VSD_TABLE_ADDR >> 3]); 749 uint8_t blk = GETFIELD(VST_TABLE_BLOCK, 750 xive->regs[VC_VSD_TABLE_ADDR >> 3]); 751 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 752 753 if (type > VST_TSEL_IRQ) { 754 xive_error(xive, "VST: invalid table type %d", type); 755 return; 756 } 757 758 if (blk >= vst_infos[type].max_blocks) { 759 xive_error(xive, "VST: invalid block id %d for" 760 " %s table", blk, vst_infos[type].name); 761 return; 762 } 763 764 /* 765 * Only take the VC sub-engine configuration into account because 766 * the XiveRouter model combines both VC and PC sub-engines 767 */ 768 if (pc_engine) { 769 return; 770 } 771 772 if (!vst_addr) { 773 xive_error(xive, "VST: invalid %s table address", vst_infos[type].name); 774 return; 775 } 776 777 switch (mode) { 778 case VSD_MODE_FORWARD: 779 xive->vsds[type][blk] = vsd; 780 break; 781 782 case VSD_MODE_EXCLUSIVE: 783 pnv_xive_vst_set_exclusive(xive, type, blk, vsd); 784 break; 785 786 default: 787 xive_error(xive, "VST: unsupported table mode %d", mode); 788 return; 789 } 790 } 791 792 /* 793 * Interrupt controller MMIO region. The layout is compatible between 794 * 4K and 64K pages : 795 * 796 * Page 0 sub-engine BARs 797 * 0x000 - 0x3FF IC registers 798 * 0x400 - 0x7FF PC registers 799 * 0x800 - 0xFFF VC registers 800 * 801 * Page 1 Notify page (writes only) 802 * 0x000 - 0x7FF HW interrupt triggers (PSI, PHB) 803 * 0x800 - 0xFFF forwards and syncs 804 * 805 * Page 2 LSI Trigger page (writes only) (not modeled) 806 * Page 3 LSI SB EOI page (reads only) (not modeled) 807 * 808 * Page 4-7 indirect TIMA 809 */ 810 811 /* 812 * IC - registers MMIO 813 */ 814 static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset, 815 uint64_t val, unsigned size) 816 { 817 PnvXive *xive = PNV_XIVE(opaque); 818 MemoryRegion *sysmem = get_system_memory(); 819 uint32_t reg = offset >> 3; 820 bool is_chip0 = xive->chip->chip_id == 0; 821 822 switch (offset) { 823 824 /* 825 * XIVE CQ (PowerBus bridge) settings 826 */ 827 case CQ_MSGSND: /* msgsnd for doorbells */ 828 case CQ_FIRMASK_OR: /* FIR error reporting */ 829 break; 830 case CQ_PBI_CTL: 831 if (val & CQ_PBI_PC_64K) { 832 xive->pc_shift = 16; 833 } 834 if (val & CQ_PBI_VC_64K) { 835 xive->vc_shift = 16; 836 } 837 break; 838 case CQ_CFG_PB_GEN: /* PowerBus General Configuration */ 839 /* 840 * TODO: CQ_INT_ADDR_OPT for 1-block-per-chip mode 841 */ 842 break; 843 844 /* 845 * XIVE Virtualization Controller settings 846 */ 847 case VC_GLOBAL_CONFIG: 848 break; 849 850 /* 851 * XIVE Presenter Controller settings 852 */ 853 case PC_GLOBAL_CONFIG: 854 /* 855 * PC_GCONF_CHIPID_OVR 856 * Overrides Int command Chip ID with the Chip ID field (DEBUG) 857 */ 858 break; 859 case PC_TCTXT_CFG: 860 /* 861 * TODO: block group support 862 */ 863 break; 864 case PC_TCTXT_TRACK: 865 /* 866 * PC_TCTXT_TRACK_EN: 867 * enable block tracking and exchange of block ownership 868 * information between Interrupt controllers 869 */ 870 break; 871 872 /* 873 * Misc settings 874 */ 875 case VC_SBC_CONFIG: /* Store EOI configuration */ 876 /* 877 * Configure store EOI if required by firwmare (skiboot has removed 878 * support recently though) 879 */ 880 if (val & (VC_SBC_CONF_CPLX_CIST | VC_SBC_CONF_CIST_BOTH)) { 881 xive->ipi_source.esb_flags |= XIVE_SRC_STORE_EOI; 882 } 883 break; 884 885 case VC_EQC_CONFIG: /* TODO: silent escalation */ 886 case VC_AIB_TX_ORDER_TAG2: /* relax ordering */ 887 break; 888 889 /* 890 * XIVE BAR settings (XSCOM only) 891 */ 892 case CQ_RST_CTL: 893 /* bit4: resets all BAR registers */ 894 break; 895 896 case CQ_IC_BAR: /* IC BAR. 8 pages */ 897 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 898 if (!(val & CQ_IC_BAR_VALID)) { 899 xive->ic_base = 0; 900 if (xive->regs[reg] & CQ_IC_BAR_VALID) { 901 memory_region_del_subregion(&xive->ic_mmio, 902 &xive->ic_reg_mmio); 903 memory_region_del_subregion(&xive->ic_mmio, 904 &xive->ic_notify_mmio); 905 memory_region_del_subregion(&xive->ic_mmio, 906 &xive->ic_lsi_mmio); 907 memory_region_del_subregion(&xive->ic_mmio, 908 &xive->tm_indirect_mmio); 909 910 memory_region_del_subregion(sysmem, &xive->ic_mmio); 911 } 912 } else { 913 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 914 if (!(xive->regs[reg] & CQ_IC_BAR_VALID)) { 915 memory_region_add_subregion(sysmem, xive->ic_base, 916 &xive->ic_mmio); 917 918 memory_region_add_subregion(&xive->ic_mmio, 0, 919 &xive->ic_reg_mmio); 920 memory_region_add_subregion(&xive->ic_mmio, 921 1ul << xive->ic_shift, 922 &xive->ic_notify_mmio); 923 memory_region_add_subregion(&xive->ic_mmio, 924 2ul << xive->ic_shift, 925 &xive->ic_lsi_mmio); 926 memory_region_add_subregion(&xive->ic_mmio, 927 4ull << xive->ic_shift, 928 &xive->tm_indirect_mmio); 929 } 930 } 931 break; 932 933 case CQ_TM1_BAR: /* TM BAR. 4 pages. Map only once */ 934 case CQ_TM2_BAR: /* second TM BAR. for hotplug. Not modeled */ 935 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 936 if (!(val & CQ_TM_BAR_VALID)) { 937 xive->tm_base = 0; 938 if (xive->regs[reg] & CQ_TM_BAR_VALID && is_chip0) { 939 memory_region_del_subregion(sysmem, &xive->tm_mmio); 940 } 941 } else { 942 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 943 if (!(xive->regs[reg] & CQ_TM_BAR_VALID) && is_chip0) { 944 memory_region_add_subregion(sysmem, xive->tm_base, 945 &xive->tm_mmio); 946 } 947 } 948 break; 949 950 case CQ_PC_BARM: 951 xive->regs[reg] = val; 952 memory_region_set_size(&xive->pc_mmio, pnv_xive_pc_size(xive)); 953 break; 954 case CQ_PC_BAR: /* From 32M to 512G */ 955 if (!(val & CQ_PC_BAR_VALID)) { 956 xive->pc_base = 0; 957 if (xive->regs[reg] & CQ_PC_BAR_VALID) { 958 memory_region_del_subregion(sysmem, &xive->pc_mmio); 959 } 960 } else { 961 xive->pc_base = val & ~(CQ_PC_BAR_VALID); 962 if (!(xive->regs[reg] & CQ_PC_BAR_VALID)) { 963 memory_region_add_subregion(sysmem, xive->pc_base, 964 &xive->pc_mmio); 965 } 966 } 967 break; 968 969 case CQ_VC_BARM: 970 xive->regs[reg] = val; 971 memory_region_set_size(&xive->vc_mmio, pnv_xive_vc_size(xive)); 972 break; 973 case CQ_VC_BAR: /* From 64M to 4TB */ 974 if (!(val & CQ_VC_BAR_VALID)) { 975 xive->vc_base = 0; 976 if (xive->regs[reg] & CQ_VC_BAR_VALID) { 977 memory_region_del_subregion(sysmem, &xive->vc_mmio); 978 } 979 } else { 980 xive->vc_base = val & ~(CQ_VC_BAR_VALID); 981 if (!(xive->regs[reg] & CQ_VC_BAR_VALID)) { 982 memory_region_add_subregion(sysmem, xive->vc_base, 983 &xive->vc_mmio); 984 } 985 } 986 break; 987 988 /* 989 * XIVE Table settings. 990 */ 991 case CQ_TAR: /* Table Address */ 992 break; 993 case CQ_TDR: /* Table Data */ 994 pnv_xive_table_set_data(xive, val); 995 break; 996 997 /* 998 * XIVE VC & PC Virtual Structure Table settings 999 */ 1000 case VC_VSD_TABLE_ADDR: 1001 case PC_VSD_TABLE_ADDR: /* Virtual table selector */ 1002 break; 1003 case VC_VSD_TABLE_DATA: /* Virtual table setting */ 1004 case PC_VSD_TABLE_DATA: 1005 pnv_xive_vst_set_data(xive, val, offset == PC_VSD_TABLE_DATA); 1006 break; 1007 1008 /* 1009 * Interrupt fifo overflow in memory backing store (Not modeled) 1010 */ 1011 case VC_IRQ_CONFIG_IPI: 1012 case VC_IRQ_CONFIG_HW: 1013 case VC_IRQ_CONFIG_CASCADE1: 1014 case VC_IRQ_CONFIG_CASCADE2: 1015 case VC_IRQ_CONFIG_REDIST: 1016 case VC_IRQ_CONFIG_IPI_CASC: 1017 break; 1018 1019 /* 1020 * XIVE hardware thread enablement 1021 */ 1022 case PC_THREAD_EN_REG0: /* Physical Thread Enable */ 1023 case PC_THREAD_EN_REG1: /* Physical Thread Enable (fused core) */ 1024 break; 1025 1026 case PC_THREAD_EN_REG0_SET: 1027 xive->regs[PC_THREAD_EN_REG0 >> 3] |= val; 1028 break; 1029 case PC_THREAD_EN_REG1_SET: 1030 xive->regs[PC_THREAD_EN_REG1 >> 3] |= val; 1031 break; 1032 case PC_THREAD_EN_REG0_CLR: 1033 xive->regs[PC_THREAD_EN_REG0 >> 3] &= ~val; 1034 break; 1035 case PC_THREAD_EN_REG1_CLR: 1036 xive->regs[PC_THREAD_EN_REG1 >> 3] &= ~val; 1037 break; 1038 1039 /* 1040 * Indirect TIMA access set up. Defines the PIR of the HW thread 1041 * to use. 1042 */ 1043 case PC_TCTXT_INDIR0 ... PC_TCTXT_INDIR3: 1044 break; 1045 1046 /* 1047 * XIVE PC & VC cache updates for EAS, NVT and END 1048 */ 1049 case VC_IVC_SCRUB_MASK: 1050 case VC_IVC_SCRUB_TRIG: 1051 break; 1052 1053 case VC_EQC_CWATCH_SPEC: 1054 val &= ~VC_EQC_CWATCH_CONFLICT; /* HW resets this bit */ 1055 break; 1056 case VC_EQC_CWATCH_DAT1 ... VC_EQC_CWATCH_DAT3: 1057 break; 1058 case VC_EQC_CWATCH_DAT0: 1059 /* writing to DATA0 triggers the cache write */ 1060 xive->regs[reg] = val; 1061 pnv_xive_end_update(xive); 1062 break; 1063 case VC_EQC_SCRUB_MASK: 1064 case VC_EQC_SCRUB_TRIG: 1065 /* 1066 * The scrubbing registers flush the cache in RAM and can also 1067 * invalidate. 1068 */ 1069 break; 1070 1071 case PC_VPC_CWATCH_SPEC: 1072 val &= ~PC_VPC_CWATCH_CONFLICT; /* HW resets this bit */ 1073 break; 1074 case PC_VPC_CWATCH_DAT1 ... PC_VPC_CWATCH_DAT7: 1075 break; 1076 case PC_VPC_CWATCH_DAT0: 1077 /* writing to DATA0 triggers the cache write */ 1078 xive->regs[reg] = val; 1079 pnv_xive_nvt_update(xive); 1080 break; 1081 case PC_VPC_SCRUB_MASK: 1082 case PC_VPC_SCRUB_TRIG: 1083 /* 1084 * The scrubbing registers flush the cache in RAM and can also 1085 * invalidate. 1086 */ 1087 break; 1088 1089 1090 /* 1091 * XIVE PC & VC cache invalidation 1092 */ 1093 case PC_AT_KILL: 1094 break; 1095 case VC_AT_MACRO_KILL: 1096 break; 1097 case PC_AT_KILL_MASK: 1098 case VC_AT_MACRO_KILL_MASK: 1099 break; 1100 1101 default: 1102 xive_error(xive, "IC: invalid write to reg=0x%"HWADDR_PRIx, offset); 1103 return; 1104 } 1105 1106 xive->regs[reg] = val; 1107 } 1108 1109 static uint64_t pnv_xive_ic_reg_read(void *opaque, hwaddr offset, unsigned size) 1110 { 1111 PnvXive *xive = PNV_XIVE(opaque); 1112 uint64_t val = 0; 1113 uint32_t reg = offset >> 3; 1114 1115 switch (offset) { 1116 case CQ_CFG_PB_GEN: 1117 case CQ_IC_BAR: 1118 case CQ_TM1_BAR: 1119 case CQ_TM2_BAR: 1120 case CQ_PC_BAR: 1121 case CQ_PC_BARM: 1122 case CQ_VC_BAR: 1123 case CQ_VC_BARM: 1124 case CQ_TAR: 1125 case CQ_TDR: 1126 case CQ_PBI_CTL: 1127 1128 case PC_TCTXT_CFG: 1129 case PC_TCTXT_TRACK: 1130 case PC_TCTXT_INDIR0: 1131 case PC_TCTXT_INDIR1: 1132 case PC_TCTXT_INDIR2: 1133 case PC_TCTXT_INDIR3: 1134 case PC_GLOBAL_CONFIG: 1135 1136 case PC_VPC_SCRUB_MASK: 1137 1138 case VC_GLOBAL_CONFIG: 1139 case VC_AIB_TX_ORDER_TAG2: 1140 1141 case VC_IRQ_CONFIG_IPI: 1142 case VC_IRQ_CONFIG_HW: 1143 case VC_IRQ_CONFIG_CASCADE1: 1144 case VC_IRQ_CONFIG_CASCADE2: 1145 case VC_IRQ_CONFIG_REDIST: 1146 case VC_IRQ_CONFIG_IPI_CASC: 1147 1148 case VC_EQC_SCRUB_MASK: 1149 case VC_IVC_SCRUB_MASK: 1150 case VC_SBC_CONFIG: 1151 case VC_AT_MACRO_KILL_MASK: 1152 case VC_VSD_TABLE_ADDR: 1153 case PC_VSD_TABLE_ADDR: 1154 case VC_VSD_TABLE_DATA: 1155 case PC_VSD_TABLE_DATA: 1156 case PC_THREAD_EN_REG0: 1157 case PC_THREAD_EN_REG1: 1158 val = xive->regs[reg]; 1159 break; 1160 1161 /* 1162 * XIVE hardware thread enablement 1163 */ 1164 case PC_THREAD_EN_REG0_SET: 1165 case PC_THREAD_EN_REG0_CLR: 1166 val = xive->regs[PC_THREAD_EN_REG0 >> 3]; 1167 break; 1168 case PC_THREAD_EN_REG1_SET: 1169 case PC_THREAD_EN_REG1_CLR: 1170 val = xive->regs[PC_THREAD_EN_REG1 >> 3]; 1171 break; 1172 1173 case CQ_MSGSND: /* Identifies which cores have msgsnd enabled. */ 1174 val = 0xffffff0000000000; 1175 break; 1176 1177 /* 1178 * XIVE PC & VC cache updates for EAS, NVT and END 1179 */ 1180 case VC_EQC_CWATCH_SPEC: 1181 xive->regs[reg] = ~(VC_EQC_CWATCH_FULL | VC_EQC_CWATCH_CONFLICT); 1182 val = xive->regs[reg]; 1183 break; 1184 case VC_EQC_CWATCH_DAT0: 1185 /* 1186 * Load DATA registers from cache with data requested by the 1187 * SPEC register 1188 */ 1189 pnv_xive_end_cache_load(xive); 1190 val = xive->regs[reg]; 1191 break; 1192 case VC_EQC_CWATCH_DAT1 ... VC_EQC_CWATCH_DAT3: 1193 val = xive->regs[reg]; 1194 break; 1195 1196 case PC_VPC_CWATCH_SPEC: 1197 xive->regs[reg] = ~(PC_VPC_CWATCH_FULL | PC_VPC_CWATCH_CONFLICT); 1198 val = xive->regs[reg]; 1199 break; 1200 case PC_VPC_CWATCH_DAT0: 1201 /* 1202 * Load DATA registers from cache with data requested by the 1203 * SPEC register 1204 */ 1205 pnv_xive_nvt_cache_load(xive); 1206 val = xive->regs[reg]; 1207 break; 1208 case PC_VPC_CWATCH_DAT1 ... PC_VPC_CWATCH_DAT7: 1209 val = xive->regs[reg]; 1210 break; 1211 1212 case PC_VPC_SCRUB_TRIG: 1213 case VC_IVC_SCRUB_TRIG: 1214 case VC_EQC_SCRUB_TRIG: 1215 xive->regs[reg] &= ~VC_SCRUB_VALID; 1216 val = xive->regs[reg]; 1217 break; 1218 1219 /* 1220 * XIVE PC & VC cache invalidation 1221 */ 1222 case PC_AT_KILL: 1223 xive->regs[reg] &= ~PC_AT_KILL_VALID; 1224 val = xive->regs[reg]; 1225 break; 1226 case VC_AT_MACRO_KILL: 1227 xive->regs[reg] &= ~VC_KILL_VALID; 1228 val = xive->regs[reg]; 1229 break; 1230 1231 /* 1232 * XIVE synchronisation 1233 */ 1234 case VC_EQC_CONFIG: 1235 val = VC_EQC_SYNC_MASK; 1236 break; 1237 1238 default: 1239 xive_error(xive, "IC: invalid read reg=0x%"HWADDR_PRIx, offset); 1240 } 1241 1242 return val; 1243 } 1244 1245 static const MemoryRegionOps pnv_xive_ic_reg_ops = { 1246 .read = pnv_xive_ic_reg_read, 1247 .write = pnv_xive_ic_reg_write, 1248 .endianness = DEVICE_BIG_ENDIAN, 1249 .valid = { 1250 .min_access_size = 8, 1251 .max_access_size = 8, 1252 }, 1253 .impl = { 1254 .min_access_size = 8, 1255 .max_access_size = 8, 1256 }, 1257 }; 1258 1259 /* 1260 * IC - Notify MMIO port page (write only) 1261 */ 1262 #define PNV_XIVE_FORWARD_IPI 0x800 /* Forward IPI */ 1263 #define PNV_XIVE_FORWARD_HW 0x880 /* Forward HW */ 1264 #define PNV_XIVE_FORWARD_OS_ESC 0x900 /* Forward OS escalation */ 1265 #define PNV_XIVE_FORWARD_HW_ESC 0x980 /* Forward Hyp escalation */ 1266 #define PNV_XIVE_FORWARD_REDIS 0xa00 /* Forward Redistribution */ 1267 #define PNV_XIVE_RESERVED5 0xa80 /* Cache line 5 PowerBUS operation */ 1268 #define PNV_XIVE_RESERVED6 0xb00 /* Cache line 6 PowerBUS operation */ 1269 #define PNV_XIVE_RESERVED7 0xb80 /* Cache line 7 PowerBUS operation */ 1270 1271 /* VC synchronisation */ 1272 #define PNV_XIVE_SYNC_IPI 0xc00 /* Sync IPI */ 1273 #define PNV_XIVE_SYNC_HW 0xc80 /* Sync HW */ 1274 #define PNV_XIVE_SYNC_OS_ESC 0xd00 /* Sync OS escalation */ 1275 #define PNV_XIVE_SYNC_HW_ESC 0xd80 /* Sync Hyp escalation */ 1276 #define PNV_XIVE_SYNC_REDIS 0xe00 /* Sync Redistribution */ 1277 1278 /* PC synchronisation */ 1279 #define PNV_XIVE_SYNC_PULL 0xe80 /* Sync pull context */ 1280 #define PNV_XIVE_SYNC_PUSH 0xf00 /* Sync push context */ 1281 #define PNV_XIVE_SYNC_VPC 0xf80 /* Sync remove VPC store */ 1282 1283 static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr addr, uint64_t val) 1284 { 1285 uint8_t blk; 1286 uint32_t idx; 1287 1288 if (val & XIVE_TRIGGER_END) { 1289 xive_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1290 addr, val); 1291 return; 1292 } 1293 1294 /* 1295 * Forward the source event notification directly to the Router. 1296 * The source interrupt number should already be correctly encoded 1297 * with the chip block id by the sending device (PHB, PSI). 1298 */ 1299 blk = XIVE_EAS_BLOCK(val); 1300 idx = XIVE_EAS_INDEX(val); 1301 1302 xive_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx)); 1303 } 1304 1305 static void pnv_xive_ic_notify_write(void *opaque, hwaddr addr, uint64_t val, 1306 unsigned size) 1307 { 1308 PnvXive *xive = PNV_XIVE(opaque); 1309 1310 /* VC: HW triggers */ 1311 switch (addr) { 1312 case 0x000 ... 0x7FF: 1313 pnv_xive_ic_hw_trigger(opaque, addr, val); 1314 break; 1315 1316 /* VC: Forwarded IRQs */ 1317 case PNV_XIVE_FORWARD_IPI: 1318 case PNV_XIVE_FORWARD_HW: 1319 case PNV_XIVE_FORWARD_OS_ESC: 1320 case PNV_XIVE_FORWARD_HW_ESC: 1321 case PNV_XIVE_FORWARD_REDIS: 1322 /* TODO: forwarded IRQs. Should be like HW triggers */ 1323 xive_error(xive, "IC: forwarded at @0x%"HWADDR_PRIx" IRQ 0x%"PRIx64, 1324 addr, val); 1325 break; 1326 1327 /* VC syncs */ 1328 case PNV_XIVE_SYNC_IPI: 1329 case PNV_XIVE_SYNC_HW: 1330 case PNV_XIVE_SYNC_OS_ESC: 1331 case PNV_XIVE_SYNC_HW_ESC: 1332 case PNV_XIVE_SYNC_REDIS: 1333 break; 1334 1335 /* PC syncs */ 1336 case PNV_XIVE_SYNC_PULL: 1337 case PNV_XIVE_SYNC_PUSH: 1338 case PNV_XIVE_SYNC_VPC: 1339 break; 1340 1341 default: 1342 xive_error(xive, "IC: invalid notify write @%"HWADDR_PRIx, addr); 1343 } 1344 } 1345 1346 static uint64_t pnv_xive_ic_notify_read(void *opaque, hwaddr addr, 1347 unsigned size) 1348 { 1349 PnvXive *xive = PNV_XIVE(opaque); 1350 1351 /* loads are invalid */ 1352 xive_error(xive, "IC: invalid notify read @%"HWADDR_PRIx, addr); 1353 return -1; 1354 } 1355 1356 static const MemoryRegionOps pnv_xive_ic_notify_ops = { 1357 .read = pnv_xive_ic_notify_read, 1358 .write = pnv_xive_ic_notify_write, 1359 .endianness = DEVICE_BIG_ENDIAN, 1360 .valid = { 1361 .min_access_size = 8, 1362 .max_access_size = 8, 1363 }, 1364 .impl = { 1365 .min_access_size = 8, 1366 .max_access_size = 8, 1367 }, 1368 }; 1369 1370 /* 1371 * IC - LSI MMIO handlers (not modeled) 1372 */ 1373 1374 static void pnv_xive_ic_lsi_write(void *opaque, hwaddr addr, 1375 uint64_t val, unsigned size) 1376 { 1377 PnvXive *xive = PNV_XIVE(opaque); 1378 1379 xive_error(xive, "IC: LSI invalid write @%"HWADDR_PRIx, addr); 1380 } 1381 1382 static uint64_t pnv_xive_ic_lsi_read(void *opaque, hwaddr addr, unsigned size) 1383 { 1384 PnvXive *xive = PNV_XIVE(opaque); 1385 1386 xive_error(xive, "IC: LSI invalid read @%"HWADDR_PRIx, addr); 1387 return -1; 1388 } 1389 1390 static const MemoryRegionOps pnv_xive_ic_lsi_ops = { 1391 .read = pnv_xive_ic_lsi_read, 1392 .write = pnv_xive_ic_lsi_write, 1393 .endianness = DEVICE_BIG_ENDIAN, 1394 .valid = { 1395 .min_access_size = 8, 1396 .max_access_size = 8, 1397 }, 1398 .impl = { 1399 .min_access_size = 8, 1400 .max_access_size = 8, 1401 }, 1402 }; 1403 1404 /* 1405 * IC - Indirect TIMA MMIO handlers 1406 */ 1407 1408 /* 1409 * When the TIMA is accessed from the indirect page, the thread id of 1410 * the target CPU is configured in the PC_TCTXT_INDIR0 register before 1411 * use. This is used for resets and for debug purpose also. 1412 */ 1413 static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive) 1414 { 1415 PnvChip *chip = xive->chip; 1416 uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3]; 1417 PowerPCCPU *cpu = NULL; 1418 int pir; 1419 1420 if (!(tctxt_indir & PC_TCTXT_INDIR_VALID)) { 1421 xive_error(xive, "IC: no indirect TIMA access in progress"); 1422 return NULL; 1423 } 1424 1425 pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir); 1426 cpu = pnv_chip_find_cpu(chip, pir); 1427 if (!cpu) { 1428 xive_error(xive, "IC: invalid PIR %x for indirect access", pir); 1429 return NULL; 1430 } 1431 1432 /* Check that HW thread is XIVE enabled */ 1433 if (!pnv_xive_is_cpu_enabled(xive, cpu)) { 1434 xive_error(xive, "IC: CPU %x is not enabled", pir); 1435 } 1436 1437 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1438 } 1439 1440 static void xive_tm_indirect_write(void *opaque, hwaddr offset, 1441 uint64_t value, unsigned size) 1442 { 1443 XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); 1444 1445 xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); 1446 } 1447 1448 static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset, 1449 unsigned size) 1450 { 1451 XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); 1452 1453 return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); 1454 } 1455 1456 static const MemoryRegionOps xive_tm_indirect_ops = { 1457 .read = xive_tm_indirect_read, 1458 .write = xive_tm_indirect_write, 1459 .endianness = DEVICE_BIG_ENDIAN, 1460 .valid = { 1461 .min_access_size = 1, 1462 .max_access_size = 8, 1463 }, 1464 .impl = { 1465 .min_access_size = 1, 1466 .max_access_size = 8, 1467 }, 1468 }; 1469 1470 static void pnv_xive_tm_write(void *opaque, hwaddr offset, 1471 uint64_t value, unsigned size) 1472 { 1473 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1474 PnvXive *xive = pnv_xive_tm_get_xive(cpu); 1475 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1476 1477 xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size); 1478 } 1479 1480 static uint64_t pnv_xive_tm_read(void *opaque, hwaddr offset, unsigned size) 1481 { 1482 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1483 PnvXive *xive = pnv_xive_tm_get_xive(cpu); 1484 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1485 1486 return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size); 1487 } 1488 1489 const MemoryRegionOps pnv_xive_tm_ops = { 1490 .read = pnv_xive_tm_read, 1491 .write = pnv_xive_tm_write, 1492 .endianness = DEVICE_BIG_ENDIAN, 1493 .valid = { 1494 .min_access_size = 1, 1495 .max_access_size = 8, 1496 }, 1497 .impl = { 1498 .min_access_size = 1, 1499 .max_access_size = 8, 1500 }, 1501 }; 1502 1503 /* 1504 * Interrupt controller XSCOM region. 1505 */ 1506 static uint64_t pnv_xive_xscom_read(void *opaque, hwaddr addr, unsigned size) 1507 { 1508 switch (addr >> 3) { 1509 case X_VC_EQC_CONFIG: 1510 /* FIXME (skiboot): This is the only XSCOM load. Bizarre. */ 1511 return VC_EQC_SYNC_MASK; 1512 default: 1513 return pnv_xive_ic_reg_read(opaque, addr, size); 1514 } 1515 } 1516 1517 static void pnv_xive_xscom_write(void *opaque, hwaddr addr, 1518 uint64_t val, unsigned size) 1519 { 1520 pnv_xive_ic_reg_write(opaque, addr, val, size); 1521 } 1522 1523 static const MemoryRegionOps pnv_xive_xscom_ops = { 1524 .read = pnv_xive_xscom_read, 1525 .write = pnv_xive_xscom_write, 1526 .endianness = DEVICE_BIG_ENDIAN, 1527 .valid = { 1528 .min_access_size = 8, 1529 .max_access_size = 8, 1530 }, 1531 .impl = { 1532 .min_access_size = 8, 1533 .max_access_size = 8, 1534 } 1535 }; 1536 1537 /* 1538 * Virtualization Controller MMIO region containing the IPI and END ESB pages 1539 */ 1540 static uint64_t pnv_xive_vc_read(void *opaque, hwaddr offset, 1541 unsigned size) 1542 { 1543 PnvXive *xive = PNV_XIVE(opaque); 1544 uint64_t edt_index = offset >> pnv_xive_edt_shift(xive); 1545 uint64_t edt_type = 0; 1546 uint64_t edt_offset; 1547 MemTxResult result; 1548 AddressSpace *edt_as = NULL; 1549 uint64_t ret = -1; 1550 1551 if (edt_index < XIVE_TABLE_EDT_MAX) { 1552 edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[edt_index]); 1553 } 1554 1555 switch (edt_type) { 1556 case CQ_TDR_EDT_IPI: 1557 edt_as = &xive->ipi_as; 1558 break; 1559 case CQ_TDR_EDT_EQ: 1560 edt_as = &xive->end_as; 1561 break; 1562 default: 1563 xive_error(xive, "VC: invalid EDT type for read @%"HWADDR_PRIx, offset); 1564 return -1; 1565 } 1566 1567 /* Remap the offset for the targeted address space */ 1568 edt_offset = pnv_xive_edt_offset(xive, offset, edt_type); 1569 1570 ret = address_space_ldq(edt_as, edt_offset, MEMTXATTRS_UNSPECIFIED, 1571 &result); 1572 1573 if (result != MEMTX_OK) { 1574 xive_error(xive, "VC: %s read failed at @0x%"HWADDR_PRIx " -> @0x%" 1575 HWADDR_PRIx, edt_type == CQ_TDR_EDT_IPI ? "IPI" : "END", 1576 offset, edt_offset); 1577 return -1; 1578 } 1579 1580 return ret; 1581 } 1582 1583 static void pnv_xive_vc_write(void *opaque, hwaddr offset, 1584 uint64_t val, unsigned size) 1585 { 1586 PnvXive *xive = PNV_XIVE(opaque); 1587 uint64_t edt_index = offset >> pnv_xive_edt_shift(xive); 1588 uint64_t edt_type = 0; 1589 uint64_t edt_offset; 1590 MemTxResult result; 1591 AddressSpace *edt_as = NULL; 1592 1593 if (edt_index < XIVE_TABLE_EDT_MAX) { 1594 edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[edt_index]); 1595 } 1596 1597 switch (edt_type) { 1598 case CQ_TDR_EDT_IPI: 1599 edt_as = &xive->ipi_as; 1600 break; 1601 case CQ_TDR_EDT_EQ: 1602 edt_as = &xive->end_as; 1603 break; 1604 default: 1605 xive_error(xive, "VC: invalid EDT type for write @%"HWADDR_PRIx, 1606 offset); 1607 return; 1608 } 1609 1610 /* Remap the offset for the targeted address space */ 1611 edt_offset = pnv_xive_edt_offset(xive, offset, edt_type); 1612 1613 address_space_stq(edt_as, edt_offset, val, MEMTXATTRS_UNSPECIFIED, &result); 1614 if (result != MEMTX_OK) { 1615 xive_error(xive, "VC: write failed at @0x%"HWADDR_PRIx, edt_offset); 1616 } 1617 } 1618 1619 static const MemoryRegionOps pnv_xive_vc_ops = { 1620 .read = pnv_xive_vc_read, 1621 .write = pnv_xive_vc_write, 1622 .endianness = DEVICE_BIG_ENDIAN, 1623 .valid = { 1624 .min_access_size = 8, 1625 .max_access_size = 8, 1626 }, 1627 .impl = { 1628 .min_access_size = 8, 1629 .max_access_size = 8, 1630 }, 1631 }; 1632 1633 /* 1634 * Presenter Controller MMIO region. The Virtualization Controller 1635 * updates the IPB in the NVT table when required. Not modeled. 1636 */ 1637 static uint64_t pnv_xive_pc_read(void *opaque, hwaddr addr, 1638 unsigned size) 1639 { 1640 PnvXive *xive = PNV_XIVE(opaque); 1641 1642 xive_error(xive, "PC: invalid read @%"HWADDR_PRIx, addr); 1643 return -1; 1644 } 1645 1646 static void pnv_xive_pc_write(void *opaque, hwaddr addr, 1647 uint64_t value, unsigned size) 1648 { 1649 PnvXive *xive = PNV_XIVE(opaque); 1650 1651 xive_error(xive, "PC: invalid write to VC @%"HWADDR_PRIx, addr); 1652 } 1653 1654 static const MemoryRegionOps pnv_xive_pc_ops = { 1655 .read = pnv_xive_pc_read, 1656 .write = pnv_xive_pc_write, 1657 .endianness = DEVICE_BIG_ENDIAN, 1658 .valid = { 1659 .min_access_size = 8, 1660 .max_access_size = 8, 1661 }, 1662 .impl = { 1663 .min_access_size = 8, 1664 .max_access_size = 8, 1665 }, 1666 }; 1667 1668 void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) 1669 { 1670 XiveRouter *xrtr = XIVE_ROUTER(xive); 1671 uint8_t blk = pnv_xive_block_id(xive); 1672 uint8_t chip_id = xive->chip->chip_id; 1673 uint32_t srcno0 = XIVE_EAS(blk, 0); 1674 uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk); 1675 XiveEAS eas; 1676 XiveEND end; 1677 int i; 1678 1679 monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk, 1680 srcno0, srcno0 + nr_ipis - 1); 1681 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); 1682 1683 monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk, 1684 srcno0, srcno0 + nr_ipis - 1); 1685 for (i = 0; i < nr_ipis; i++) { 1686 if (xive_router_get_eas(xrtr, blk, i, &eas)) { 1687 break; 1688 } 1689 if (!xive_eas_is_masked(&eas)) { 1690 xive_eas_pic_print_info(&eas, i, mon); 1691 } 1692 } 1693 1694 monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); 1695 i = 0; 1696 while (!xive_router_get_end(xrtr, blk, i, &end)) { 1697 xive_end_pic_print_info(&end, i++, mon); 1698 } 1699 1700 monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); 1701 i = 0; 1702 while (!xive_router_get_end(xrtr, blk, i, &end)) { 1703 xive_end_eas_pic_print_info(&end, i++, mon); 1704 } 1705 } 1706 1707 static void pnv_xive_reset(void *dev) 1708 { 1709 PnvXive *xive = PNV_XIVE(dev); 1710 XiveSource *xsrc = &xive->ipi_source; 1711 XiveENDSource *end_xsrc = &xive->end_source; 1712 1713 /* Default page size (Should be changed at runtime to 64k) */ 1714 xive->ic_shift = xive->vc_shift = xive->pc_shift = 12; 1715 1716 /* Clear subregions */ 1717 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 1718 memory_region_del_subregion(&xive->ipi_edt_mmio, &xsrc->esb_mmio); 1719 } 1720 1721 if (memory_region_is_mapped(&xive->ipi_edt_mmio)) { 1722 memory_region_del_subregion(&xive->ipi_mmio, &xive->ipi_edt_mmio); 1723 } 1724 1725 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 1726 memory_region_del_subregion(&xive->end_edt_mmio, &end_xsrc->esb_mmio); 1727 } 1728 1729 if (memory_region_is_mapped(&xive->end_edt_mmio)) { 1730 memory_region_del_subregion(&xive->end_mmio, &xive->end_edt_mmio); 1731 } 1732 } 1733 1734 static void pnv_xive_init(Object *obj) 1735 { 1736 PnvXive *xive = PNV_XIVE(obj); 1737 1738 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 1739 sizeof(xive->ipi_source), TYPE_XIVE_SOURCE, 1740 &error_abort, NULL); 1741 object_initialize_child(obj, "end_source", &xive->end_source, 1742 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 1743 &error_abort, NULL); 1744 } 1745 1746 /* 1747 * Maximum number of IRQs and ENDs supported by HW 1748 */ 1749 #define PNV_XIVE_NR_IRQS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1750 #define PNV_XIVE_NR_ENDS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1751 1752 static void pnv_xive_realize(DeviceState *dev, Error **errp) 1753 { 1754 PnvXive *xive = PNV_XIVE(dev); 1755 XiveSource *xsrc = &xive->ipi_source; 1756 XiveENDSource *end_xsrc = &xive->end_source; 1757 Error *local_err = NULL; 1758 1759 assert(xive->chip); 1760 1761 /* 1762 * The XiveSource and XiveENDSource objects are realized with the 1763 * maximum allowed HW configuration. The ESB MMIO regions will be 1764 * resized dynamically when the controller is configured by the FW 1765 * to limit accesses to resources not provisioned. 1766 */ 1767 object_property_set_int(OBJECT(xsrc), PNV_XIVE_NR_IRQS, "nr-irqs", 1768 &error_fatal); 1769 object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive", 1770 &error_abort); 1771 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 1772 if (local_err) { 1773 error_propagate(errp, local_err); 1774 return; 1775 } 1776 1777 object_property_set_int(OBJECT(end_xsrc), PNV_XIVE_NR_ENDS, "nr-ends", 1778 &error_fatal); 1779 object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive", 1780 &error_abort); 1781 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 1782 if (local_err) { 1783 error_propagate(errp, local_err); 1784 return; 1785 } 1786 1787 /* Default page size. Generally changed at runtime to 64k */ 1788 xive->ic_shift = xive->vc_shift = xive->pc_shift = 12; 1789 1790 /* XSCOM region, used for initial configuration of the BARs */ 1791 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), &pnv_xive_xscom_ops, 1792 xive, "xscom-xive", PNV9_XSCOM_XIVE_SIZE << 3); 1793 1794 /* Interrupt controller MMIO regions */ 1795 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 1796 PNV9_XIVE_IC_SIZE); 1797 1798 memory_region_init_io(&xive->ic_reg_mmio, OBJECT(dev), &pnv_xive_ic_reg_ops, 1799 xive, "xive-ic-reg", 1 << xive->ic_shift); 1800 memory_region_init_io(&xive->ic_notify_mmio, OBJECT(dev), 1801 &pnv_xive_ic_notify_ops, 1802 xive, "xive-ic-notify", 1 << xive->ic_shift); 1803 1804 /* The Pervasive LSI trigger and EOI pages (not modeled) */ 1805 memory_region_init_io(&xive->ic_lsi_mmio, OBJECT(dev), &pnv_xive_ic_lsi_ops, 1806 xive, "xive-ic-lsi", 2 << xive->ic_shift); 1807 1808 /* Thread Interrupt Management Area (Indirect) */ 1809 memory_region_init_io(&xive->tm_indirect_mmio, OBJECT(dev), 1810 &xive_tm_indirect_ops, 1811 xive, "xive-tima-indirect", PNV9_XIVE_TM_SIZE); 1812 /* 1813 * Overall Virtualization Controller MMIO region containing the 1814 * IPI ESB pages and END ESB pages. The layout is defined by the 1815 * EDT "Domain table" and the accesses are dispatched using 1816 * address spaces for each. 1817 */ 1818 memory_region_init_io(&xive->vc_mmio, OBJECT(xive), &pnv_xive_vc_ops, xive, 1819 "xive-vc", PNV9_XIVE_VC_SIZE); 1820 1821 memory_region_init(&xive->ipi_mmio, OBJECT(xive), "xive-vc-ipi", 1822 PNV9_XIVE_VC_SIZE); 1823 address_space_init(&xive->ipi_as, &xive->ipi_mmio, "xive-vc-ipi"); 1824 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-vc-end", 1825 PNV9_XIVE_VC_SIZE); 1826 address_space_init(&xive->end_as, &xive->end_mmio, "xive-vc-end"); 1827 1828 /* 1829 * The MMIO windows exposing the IPI ESBs and the END ESBs in the 1830 * VC region. Their size is configured by the FW in the EDT table. 1831 */ 1832 memory_region_init(&xive->ipi_edt_mmio, OBJECT(xive), "xive-vc-ipi-edt", 0); 1833 memory_region_init(&xive->end_edt_mmio, OBJECT(xive), "xive-vc-end-edt", 0); 1834 1835 /* Presenter Controller MMIO region (not modeled) */ 1836 memory_region_init_io(&xive->pc_mmio, OBJECT(xive), &pnv_xive_pc_ops, xive, 1837 "xive-pc", PNV9_XIVE_PC_SIZE); 1838 1839 /* Thread Interrupt Management Area (Direct) */ 1840 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops, 1841 xive, "xive-tima", PNV9_XIVE_TM_SIZE); 1842 1843 qemu_register_reset(pnv_xive_reset, dev); 1844 } 1845 1846 static int pnv_xive_dt_xscom(PnvXScomInterface *dev, void *fdt, 1847 int xscom_offset) 1848 { 1849 const char compat[] = "ibm,power9-xive-x"; 1850 char *name; 1851 int offset; 1852 uint32_t lpc_pcba = PNV9_XSCOM_XIVE_BASE; 1853 uint32_t reg[] = { 1854 cpu_to_be32(lpc_pcba), 1855 cpu_to_be32(PNV9_XSCOM_XIVE_SIZE) 1856 }; 1857 1858 name = g_strdup_printf("xive@%x", lpc_pcba); 1859 offset = fdt_add_subnode(fdt, xscom_offset, name); 1860 _FDT(offset); 1861 g_free(name); 1862 1863 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 1864 _FDT((fdt_setprop(fdt, offset, "compatible", compat, 1865 sizeof(compat)))); 1866 return 0; 1867 } 1868 1869 static Property pnv_xive_properties[] = { 1870 DEFINE_PROP_UINT64("ic-bar", PnvXive, ic_base, 0), 1871 DEFINE_PROP_UINT64("vc-bar", PnvXive, vc_base, 0), 1872 DEFINE_PROP_UINT64("pc-bar", PnvXive, pc_base, 0), 1873 DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0), 1874 /* The PnvChip id identifies the XIVE interrupt controller. */ 1875 DEFINE_PROP_LINK("chip", PnvXive, chip, TYPE_PNV_CHIP, PnvChip *), 1876 DEFINE_PROP_END_OF_LIST(), 1877 }; 1878 1879 static void pnv_xive_class_init(ObjectClass *klass, void *data) 1880 { 1881 DeviceClass *dc = DEVICE_CLASS(klass); 1882 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 1883 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 1884 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1885 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 1886 1887 xdc->dt_xscom = pnv_xive_dt_xscom; 1888 1889 dc->desc = "PowerNV XIVE Interrupt Controller"; 1890 dc->realize = pnv_xive_realize; 1891 dc->props = pnv_xive_properties; 1892 1893 xrc->get_eas = pnv_xive_get_eas; 1894 xrc->get_end = pnv_xive_get_end; 1895 xrc->write_end = pnv_xive_write_end; 1896 xrc->get_nvt = pnv_xive_get_nvt; 1897 xrc->write_nvt = pnv_xive_write_nvt; 1898 xrc->get_block_id = pnv_xive_get_block_id; 1899 1900 xnc->notify = pnv_xive_notify; 1901 xpc->match_nvt = pnv_xive_match_nvt; 1902 }; 1903 1904 static const TypeInfo pnv_xive_info = { 1905 .name = TYPE_PNV_XIVE, 1906 .parent = TYPE_XIVE_ROUTER, 1907 .instance_init = pnv_xive_init, 1908 .instance_size = sizeof(PnvXive), 1909 .class_init = pnv_xive_class_init, 1910 .interfaces = (InterfaceInfo[]) { 1911 { TYPE_PNV_XSCOM_INTERFACE }, 1912 { } 1913 } 1914 }; 1915 1916 static void pnv_xive_register_types(void) 1917 { 1918 type_register_static(&pnv_xive_info); 1919 } 1920 1921 type_init(pnv_xive_register_types) 1922