1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "monitor/monitor.h" 19 #include "hw/ppc/fdt.h" 20 #include "hw/ppc/pnv.h" 21 #include "hw/ppc/pnv_core.h" 22 #include "hw/ppc/pnv_xscom.h" 23 #include "hw/ppc/pnv_xive.h" 24 #include "hw/ppc/xive_regs.h" 25 #include "hw/qdev-properties.h" 26 #include "hw/ppc/ppc.h" 27 28 #include <libfdt.h> 29 30 #include "pnv_xive_regs.h" 31 32 #undef XIVE_DEBUG 33 34 /* 35 * Virtual structures table (VST) 36 */ 37 #define SBE_PER_BYTE 4 38 39 typedef struct XiveVstInfo { 40 const char *name; 41 uint32_t size; 42 uint32_t max_blocks; 43 } XiveVstInfo; 44 45 static const XiveVstInfo vst_infos[] = { 46 [VST_TSEL_IVT] = { "EAT", sizeof(XiveEAS), 16 }, 47 [VST_TSEL_SBE] = { "SBE", 1, 16 }, 48 [VST_TSEL_EQDT] = { "ENDT", sizeof(XiveEND), 16 }, 49 [VST_TSEL_VPDT] = { "VPDT", sizeof(XiveNVT), 32 }, 50 51 /* 52 * Interrupt fifo backing store table (not modeled) : 53 * 54 * 0 - IPI, 55 * 1 - HWD, 56 * 2 - First escalate, 57 * 3 - Second escalate, 58 * 4 - Redistribution, 59 * 5 - IPI cascaded queue ? 60 */ 61 [VST_TSEL_IRQ] = { "IRQ", 1, 6 }, 62 }; 63 64 #define xive_error(xive, fmt, ...) \ 65 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 66 (xive)->chip->chip_id, ## __VA_ARGS__); 67 68 /* 69 * QEMU version of the GETFIELD/SETFIELD macros 70 * 71 * TODO: It might be better to use the existing extract64() and 72 * deposit64() but this means that all the register definitions will 73 * change and become incompatible with the ones found in skiboot. 74 * 75 * Keep it as it is for now until we find a common ground. 76 */ 77 static inline uint64_t GETFIELD(uint64_t mask, uint64_t word) 78 { 79 return (word & mask) >> ctz64(mask); 80 } 81 82 static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, 83 uint64_t value) 84 { 85 return (word & ~mask) | ((value << ctz64(mask)) & mask); 86 } 87 88 /* 89 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 90 * of the chips is good enough. 91 * 92 * TODO: Block scope support 93 */ 94 static PnvXive *pnv_xive_get_ic(uint8_t blk) 95 { 96 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 97 int i; 98 99 for (i = 0; i < pnv->num_chips; i++) { 100 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 101 PnvXive *xive = &chip9->xive; 102 103 if (xive->chip->chip_id == blk) { 104 return xive; 105 } 106 } 107 return NULL; 108 } 109 110 /* 111 * VST accessors for SBE, EAT, ENDT, NVT 112 * 113 * Indirect VST tables are arrays of VSDs pointing to a page (of same 114 * size). Each page is a direct VST table. 115 */ 116 117 #define XIVE_VSD_SIZE 8 118 119 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 120 static uint64_t pnv_xive_vst_page_size_allowed(uint32_t page_shift) 121 { 122 return page_shift == 12 || page_shift == 16 || 123 page_shift == 21 || page_shift == 24; 124 } 125 126 static uint64_t pnv_xive_vst_addr_direct(PnvXive *xive, uint32_t type, 127 uint64_t vsd, uint32_t idx) 128 { 129 const XiveVstInfo *info = &vst_infos[type]; 130 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 131 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 132 uint32_t idx_max; 133 134 idx_max = vst_tsize / info->size - 1; 135 if (idx > idx_max) { 136 #ifdef XIVE_DEBUG 137 xive_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 138 info->name, idx, idx_max); 139 #endif 140 return 0; 141 } 142 143 return vst_addr + idx * info->size; 144 } 145 146 static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xive, uint32_t type, 147 uint64_t vsd, uint32_t idx) 148 { 149 const XiveVstInfo *info = &vst_infos[type]; 150 uint64_t vsd_addr; 151 uint32_t vsd_idx; 152 uint32_t page_shift; 153 uint32_t vst_per_page; 154 155 /* Get the page size of the indirect table. */ 156 vsd_addr = vsd & VSD_ADDRESS_MASK; 157 vsd = ldq_be_dma(&address_space_memory, vsd_addr); 158 159 if (!(vsd & VSD_ADDRESS_MASK)) { 160 #ifdef XIVE_DEBUG 161 xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 162 #endif 163 return 0; 164 } 165 166 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 167 168 if (!pnv_xive_vst_page_size_allowed(page_shift)) { 169 xive_error(xive, "VST: invalid %s page shift %d", info->name, 170 page_shift); 171 return 0; 172 } 173 174 vst_per_page = (1ull << page_shift) / info->size; 175 vsd_idx = idx / vst_per_page; 176 177 /* Load the VSD we are looking for, if not already done */ 178 if (vsd_idx) { 179 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 180 vsd = ldq_be_dma(&address_space_memory, vsd_addr); 181 182 if (!(vsd & VSD_ADDRESS_MASK)) { 183 #ifdef XIVE_DEBUG 184 xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 185 #endif 186 return 0; 187 } 188 189 /* 190 * Check that the pages have a consistent size across the 191 * indirect table 192 */ 193 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 194 xive_error(xive, "VST: %s entry %x indirect page size differ !?", 195 info->name, idx); 196 return 0; 197 } 198 } 199 200 return pnv_xive_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 201 } 202 203 static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk, 204 uint32_t idx) 205 { 206 const XiveVstInfo *info = &vst_infos[type]; 207 uint64_t vsd; 208 209 if (blk >= info->max_blocks) { 210 xive_error(xive, "VST: invalid block id %d for VST %s %d !?", 211 blk, info->name, idx); 212 return 0; 213 } 214 215 vsd = xive->vsds[type][blk]; 216 217 /* Remote VST access */ 218 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 219 xive = pnv_xive_get_ic(blk); 220 221 return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; 222 } 223 224 if (VSD_INDIRECT & vsd) { 225 return pnv_xive_vst_addr_indirect(xive, type, vsd, idx); 226 } 227 228 return pnv_xive_vst_addr_direct(xive, type, vsd, idx); 229 } 230 231 static int pnv_xive_vst_read(PnvXive *xive, uint32_t type, uint8_t blk, 232 uint32_t idx, void *data) 233 { 234 const XiveVstInfo *info = &vst_infos[type]; 235 uint64_t addr = pnv_xive_vst_addr(xive, type, blk, idx); 236 237 if (!addr) { 238 return -1; 239 } 240 241 cpu_physical_memory_read(addr, data, info->size); 242 return 0; 243 } 244 245 #define XIVE_VST_WORD_ALL -1 246 247 static int pnv_xive_vst_write(PnvXive *xive, uint32_t type, uint8_t blk, 248 uint32_t idx, void *data, uint32_t word_number) 249 { 250 const XiveVstInfo *info = &vst_infos[type]; 251 uint64_t addr = pnv_xive_vst_addr(xive, type, blk, idx); 252 253 if (!addr) { 254 return -1; 255 } 256 257 if (word_number == XIVE_VST_WORD_ALL) { 258 cpu_physical_memory_write(addr, data, info->size); 259 } else { 260 cpu_physical_memory_write(addr + word_number * 4, 261 data + word_number * 4, 4); 262 } 263 return 0; 264 } 265 266 static int pnv_xive_get_end(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 267 XiveEND *end) 268 { 269 return pnv_xive_vst_read(PNV_XIVE(xrtr), VST_TSEL_EQDT, blk, idx, end); 270 } 271 272 static int pnv_xive_write_end(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 273 XiveEND *end, uint8_t word_number) 274 { 275 return pnv_xive_vst_write(PNV_XIVE(xrtr), VST_TSEL_EQDT, blk, idx, end, 276 word_number); 277 } 278 279 static int pnv_xive_end_update(PnvXive *xive) 280 { 281 uint8_t blk = GETFIELD(VC_EQC_CWATCH_BLOCKID, 282 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 283 uint32_t idx = GETFIELD(VC_EQC_CWATCH_OFFSET, 284 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 285 int i; 286 uint64_t eqc_watch[4]; 287 288 for (i = 0; i < ARRAY_SIZE(eqc_watch); i++) { 289 eqc_watch[i] = cpu_to_be64(xive->regs[(VC_EQC_CWATCH_DAT0 >> 3) + i]); 290 } 291 292 return pnv_xive_vst_write(xive, VST_TSEL_EQDT, blk, idx, eqc_watch, 293 XIVE_VST_WORD_ALL); 294 } 295 296 static void pnv_xive_end_cache_load(PnvXive *xive) 297 { 298 uint8_t blk = GETFIELD(VC_EQC_CWATCH_BLOCKID, 299 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 300 uint32_t idx = GETFIELD(VC_EQC_CWATCH_OFFSET, 301 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 302 uint64_t eqc_watch[4] = { 0 }; 303 int i; 304 305 if (pnv_xive_vst_read(xive, VST_TSEL_EQDT, blk, idx, eqc_watch)) { 306 xive_error(xive, "VST: no END entry %x/%x !?", blk, idx); 307 } 308 309 for (i = 0; i < ARRAY_SIZE(eqc_watch); i++) { 310 xive->regs[(VC_EQC_CWATCH_DAT0 >> 3) + i] = be64_to_cpu(eqc_watch[i]); 311 } 312 } 313 314 static int pnv_xive_get_nvt(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 315 XiveNVT *nvt) 316 { 317 return pnv_xive_vst_read(PNV_XIVE(xrtr), VST_TSEL_VPDT, blk, idx, nvt); 318 } 319 320 static int pnv_xive_write_nvt(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 321 XiveNVT *nvt, uint8_t word_number) 322 { 323 return pnv_xive_vst_write(PNV_XIVE(xrtr), VST_TSEL_VPDT, blk, idx, nvt, 324 word_number); 325 } 326 327 static int pnv_xive_nvt_update(PnvXive *xive) 328 { 329 uint8_t blk = GETFIELD(PC_VPC_CWATCH_BLOCKID, 330 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 331 uint32_t idx = GETFIELD(PC_VPC_CWATCH_OFFSET, 332 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 333 int i; 334 uint64_t vpc_watch[8]; 335 336 for (i = 0; i < ARRAY_SIZE(vpc_watch); i++) { 337 vpc_watch[i] = cpu_to_be64(xive->regs[(PC_VPC_CWATCH_DAT0 >> 3) + i]); 338 } 339 340 return pnv_xive_vst_write(xive, VST_TSEL_VPDT, blk, idx, vpc_watch, 341 XIVE_VST_WORD_ALL); 342 } 343 344 static void pnv_xive_nvt_cache_load(PnvXive *xive) 345 { 346 uint8_t blk = GETFIELD(PC_VPC_CWATCH_BLOCKID, 347 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 348 uint32_t idx = GETFIELD(PC_VPC_CWATCH_OFFSET, 349 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 350 uint64_t vpc_watch[8] = { 0 }; 351 int i; 352 353 if (pnv_xive_vst_read(xive, VST_TSEL_VPDT, blk, idx, vpc_watch)) { 354 xive_error(xive, "VST: no NVT entry %x/%x !?", blk, idx); 355 } 356 357 for (i = 0; i < ARRAY_SIZE(vpc_watch); i++) { 358 xive->regs[(PC_VPC_CWATCH_DAT0 >> 3) + i] = be64_to_cpu(vpc_watch[i]); 359 } 360 } 361 362 static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 363 XiveEAS *eas) 364 { 365 PnvXive *xive = PNV_XIVE(xrtr); 366 367 if (pnv_xive_get_ic(blk) != xive) { 368 xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 369 return -1; 370 } 371 372 return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); 373 } 374 375 /* 376 * One bit per thread id. The first register PC_THREAD_EN_REG0 covers 377 * the first cores 0-15 (normal) of the chip or 0-7 (fused). The 378 * second register covers cores 16-23 (normal) or 8-11 (fused). 379 */ 380 static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu) 381 { 382 int pir = ppc_cpu_pir(cpu); 383 uint32_t fc = PNV9_PIR2FUSEDCORE(pir); 384 uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1; 385 uint32_t bit = pir & 0x3f; 386 387 return xive->regs[reg >> 3] & PPC_BIT(bit); 388 } 389 390 static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, 391 uint8_t nvt_blk, uint32_t nvt_idx, 392 bool cam_ignore, uint8_t priority, 393 uint32_t logic_serv, XiveTCTXMatch *match) 394 { 395 PnvXive *xive = PNV_XIVE(xptr); 396 PnvChip *chip = xive->chip; 397 int count = 0; 398 int i, j; 399 400 for (i = 0; i < chip->nr_cores; i++) { 401 PnvCore *pc = chip->cores[i]; 402 CPUCore *cc = CPU_CORE(pc); 403 404 for (j = 0; j < cc->nr_threads; j++) { 405 PowerPCCPU *cpu = pc->threads[j]; 406 XiveTCTX *tctx; 407 int ring; 408 409 if (!pnv_xive_is_cpu_enabled(xive, cpu)) { 410 continue; 411 } 412 413 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 414 415 /* 416 * Check the thread context CAM lines and record matches. 417 */ 418 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, 419 nvt_idx, cam_ignore, logic_serv); 420 /* 421 * Save the context and follow on to catch duplicates, that we 422 * don't support yet. 423 */ 424 if (ring != -1) { 425 if (match->tctx) { 426 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 427 "thread context NVT %x/%x\n", 428 nvt_blk, nvt_idx); 429 return -1; 430 } 431 432 match->ring = ring; 433 match->tctx = tctx; 434 count++; 435 } 436 } 437 } 438 439 return count; 440 } 441 442 /* 443 * The TIMA MMIO space is shared among the chips and to identify the 444 * chip from which the access is being done, we extract the chip id 445 * from the PIR. 446 */ 447 static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) 448 { 449 int pir = ppc_cpu_pir(cpu); 450 PnvChip *chip; 451 PnvXive *xive; 452 453 chip = pnv_get_chip(PNV9_PIR2CHIP(pir)); 454 assert(chip); 455 xive = &PNV9_CHIP(chip)->xive; 456 457 if (!pnv_xive_is_cpu_enabled(xive, cpu)) { 458 xive_error(xive, "IC: CPU %x is not enabled", pir); 459 } 460 return xive; 461 } 462 463 static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) 464 { 465 PowerPCCPU *cpu = POWERPC_CPU(cs); 466 PnvXive *xive = pnv_xive_tm_get_xive(cpu); 467 468 if (!xive) { 469 return NULL; 470 } 471 472 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 473 } 474 475 /* 476 * The internal sources (IPIs) of the interrupt controller have no 477 * knowledge of the XIVE chip on which they reside. Encode the block 478 * id in the source interrupt number before forwarding the source 479 * event notification to the Router. This is required on a multichip 480 * system. 481 */ 482 static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno) 483 { 484 PnvXive *xive = PNV_XIVE(xn); 485 uint8_t blk = xive->chip->chip_id; 486 487 xive_router_notify(xn, XIVE_EAS(blk, srcno)); 488 } 489 490 /* 491 * XIVE helpers 492 */ 493 494 static uint64_t pnv_xive_vc_size(PnvXive *xive) 495 { 496 return (~xive->regs[CQ_VC_BARM >> 3] + 1) & CQ_VC_BARM_MASK; 497 } 498 499 static uint64_t pnv_xive_edt_shift(PnvXive *xive) 500 { 501 return ctz64(pnv_xive_vc_size(xive) / XIVE_TABLE_EDT_MAX); 502 } 503 504 static uint64_t pnv_xive_pc_size(PnvXive *xive) 505 { 506 return (~xive->regs[CQ_PC_BARM >> 3] + 1) & CQ_PC_BARM_MASK; 507 } 508 509 static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk) 510 { 511 uint64_t vsd = xive->vsds[VST_TSEL_SBE][blk]; 512 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 513 514 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 515 } 516 517 /* 518 * EDT Table 519 * 520 * The Virtualization Controller MMIO region containing the IPI ESB 521 * pages and END ESB pages is sub-divided into "sets" which map 522 * portions of the VC region to the different ESB pages. It is 523 * configured at runtime through the EDT "Domain Table" to let the 524 * firmware decide how to split the VC address space between IPI ESB 525 * pages and END ESB pages. 526 */ 527 528 /* 529 * Computes the overall size of the IPI or the END ESB pages 530 */ 531 static uint64_t pnv_xive_edt_size(PnvXive *xive, uint64_t type) 532 { 533 uint64_t edt_size = 1ull << pnv_xive_edt_shift(xive); 534 uint64_t size = 0; 535 int i; 536 537 for (i = 0; i < XIVE_TABLE_EDT_MAX; i++) { 538 uint64_t edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[i]); 539 540 if (edt_type == type) { 541 size += edt_size; 542 } 543 } 544 545 return size; 546 } 547 548 /* 549 * Maps an offset of the VC region in the IPI or END region using the 550 * layout defined by the EDT "Domaine Table" 551 */ 552 static uint64_t pnv_xive_edt_offset(PnvXive *xive, uint64_t vc_offset, 553 uint64_t type) 554 { 555 int i; 556 uint64_t edt_size = 1ull << pnv_xive_edt_shift(xive); 557 uint64_t edt_offset = vc_offset; 558 559 for (i = 0; i < XIVE_TABLE_EDT_MAX && (i * edt_size) < vc_offset; i++) { 560 uint64_t edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[i]); 561 562 if (edt_type != type) { 563 edt_offset -= edt_size; 564 } 565 } 566 567 return edt_offset; 568 } 569 570 static void pnv_xive_edt_resize(PnvXive *xive) 571 { 572 uint64_t ipi_edt_size = pnv_xive_edt_size(xive, CQ_TDR_EDT_IPI); 573 uint64_t end_edt_size = pnv_xive_edt_size(xive, CQ_TDR_EDT_EQ); 574 575 memory_region_set_size(&xive->ipi_edt_mmio, ipi_edt_size); 576 memory_region_add_subregion(&xive->ipi_mmio, 0, &xive->ipi_edt_mmio); 577 578 memory_region_set_size(&xive->end_edt_mmio, end_edt_size); 579 memory_region_add_subregion(&xive->end_mmio, 0, &xive->end_edt_mmio); 580 } 581 582 /* 583 * XIVE Table configuration. Only EDT is supported. 584 */ 585 static int pnv_xive_table_set_data(PnvXive *xive, uint64_t val) 586 { 587 uint64_t tsel = xive->regs[CQ_TAR >> 3] & CQ_TAR_TSEL; 588 uint8_t tsel_index = GETFIELD(CQ_TAR_TSEL_INDEX, xive->regs[CQ_TAR >> 3]); 589 uint64_t *xive_table; 590 uint8_t max_index; 591 592 switch (tsel) { 593 case CQ_TAR_TSEL_BLK: 594 max_index = ARRAY_SIZE(xive->blk); 595 xive_table = xive->blk; 596 break; 597 case CQ_TAR_TSEL_MIG: 598 max_index = ARRAY_SIZE(xive->mig); 599 xive_table = xive->mig; 600 break; 601 case CQ_TAR_TSEL_EDT: 602 max_index = ARRAY_SIZE(xive->edt); 603 xive_table = xive->edt; 604 break; 605 case CQ_TAR_TSEL_VDT: 606 max_index = ARRAY_SIZE(xive->vdt); 607 xive_table = xive->vdt; 608 break; 609 default: 610 xive_error(xive, "IC: invalid table %d", (int) tsel); 611 return -1; 612 } 613 614 if (tsel_index >= max_index) { 615 xive_error(xive, "IC: invalid index %d", (int) tsel_index); 616 return -1; 617 } 618 619 xive_table[tsel_index] = val; 620 621 if (xive->regs[CQ_TAR >> 3] & CQ_TAR_TBL_AUTOINC) { 622 xive->regs[CQ_TAR >> 3] = 623 SETFIELD(CQ_TAR_TSEL_INDEX, xive->regs[CQ_TAR >> 3], ++tsel_index); 624 } 625 626 /* 627 * EDT configuration is complete. Resize the MMIO windows exposing 628 * the IPI and the END ESBs in the VC region. 629 */ 630 if (tsel == CQ_TAR_TSEL_EDT && tsel_index == ARRAY_SIZE(xive->edt)) { 631 pnv_xive_edt_resize(xive); 632 } 633 634 return 0; 635 } 636 637 /* 638 * Virtual Structure Tables (VST) configuration 639 */ 640 static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type, 641 uint8_t blk, uint64_t vsd) 642 { 643 XiveENDSource *end_xsrc = &xive->end_source; 644 XiveSource *xsrc = &xive->ipi_source; 645 const XiveVstInfo *info = &vst_infos[type]; 646 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 647 uint64_t vst_tsize = 1ull << page_shift; 648 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 649 650 /* Basic checks */ 651 652 if (VSD_INDIRECT & vsd) { 653 if (!(xive->regs[VC_GLOBAL_CONFIG >> 3] & VC_GCONF_INDIRECT)) { 654 xive_error(xive, "VST: %s indirect tables are not enabled", 655 info->name); 656 return; 657 } 658 659 if (!pnv_xive_vst_page_size_allowed(page_shift)) { 660 xive_error(xive, "VST: invalid %s page shift %d", info->name, 661 page_shift); 662 return; 663 } 664 } 665 666 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 667 xive_error(xive, "VST: %s table address 0x%"PRIx64" is not aligned with" 668 " page shift %d", info->name, vst_addr, page_shift); 669 return; 670 } 671 672 /* Record the table configuration (in SRAM on HW) */ 673 xive->vsds[type][blk] = vsd; 674 675 /* Now tune the models with the configuration provided by the FW */ 676 677 switch (type) { 678 case VST_TSEL_IVT: /* Nothing to be done */ 679 break; 680 681 case VST_TSEL_EQDT: 682 /* 683 * Backing store pages for the END. 684 * 685 * If the table is direct, we can compute the number of PQ 686 * entries provisioned by FW (such as skiboot) and resize the 687 * END ESB window accordingly. 688 */ 689 if (!(VSD_INDIRECT & vsd)) { 690 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 691 * (1ull << xsrc->esb_shift)); 692 } 693 memory_region_add_subregion(&xive->end_edt_mmio, 0, 694 &end_xsrc->esb_mmio); 695 break; 696 697 case VST_TSEL_SBE: 698 /* 699 * Backing store pages for the source PQ bits. The model does 700 * not use these PQ bits backed in RAM because the XiveSource 701 * model has its own. 702 * 703 * If the table is direct, we can compute the number of PQ 704 * entries provisioned by FW (such as skiboot) and resize the 705 * ESB window accordingly. 706 */ 707 if (!(VSD_INDIRECT & vsd)) { 708 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 709 * (1ull << xsrc->esb_shift)); 710 } 711 memory_region_add_subregion(&xive->ipi_edt_mmio, 0, &xsrc->esb_mmio); 712 break; 713 714 case VST_TSEL_VPDT: /* Not modeled */ 715 case VST_TSEL_IRQ: /* Not modeled */ 716 /* 717 * These tables contains the backing store pages for the 718 * interrupt fifos of the VC sub-engine in case of overflow. 719 */ 720 break; 721 722 default: 723 g_assert_not_reached(); 724 } 725 } 726 727 /* 728 * Both PC and VC sub-engines are configured as each use the Virtual 729 * Structure Tables : SBE, EAS, END and NVT. 730 */ 731 static void pnv_xive_vst_set_data(PnvXive *xive, uint64_t vsd, bool pc_engine) 732 { 733 uint8_t mode = GETFIELD(VSD_MODE, vsd); 734 uint8_t type = GETFIELD(VST_TABLE_SELECT, 735 xive->regs[VC_VSD_TABLE_ADDR >> 3]); 736 uint8_t blk = GETFIELD(VST_TABLE_BLOCK, 737 xive->regs[VC_VSD_TABLE_ADDR >> 3]); 738 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 739 740 if (type > VST_TSEL_IRQ) { 741 xive_error(xive, "VST: invalid table type %d", type); 742 return; 743 } 744 745 if (blk >= vst_infos[type].max_blocks) { 746 xive_error(xive, "VST: invalid block id %d for" 747 " %s table", blk, vst_infos[type].name); 748 return; 749 } 750 751 /* 752 * Only take the VC sub-engine configuration into account because 753 * the XiveRouter model combines both VC and PC sub-engines 754 */ 755 if (pc_engine) { 756 return; 757 } 758 759 if (!vst_addr) { 760 xive_error(xive, "VST: invalid %s table address", vst_infos[type].name); 761 return; 762 } 763 764 switch (mode) { 765 case VSD_MODE_FORWARD: 766 xive->vsds[type][blk] = vsd; 767 break; 768 769 case VSD_MODE_EXCLUSIVE: 770 pnv_xive_vst_set_exclusive(xive, type, blk, vsd); 771 break; 772 773 default: 774 xive_error(xive, "VST: unsupported table mode %d", mode); 775 return; 776 } 777 } 778 779 /* 780 * Interrupt controller MMIO region. The layout is compatible between 781 * 4K and 64K pages : 782 * 783 * Page 0 sub-engine BARs 784 * 0x000 - 0x3FF IC registers 785 * 0x400 - 0x7FF PC registers 786 * 0x800 - 0xFFF VC registers 787 * 788 * Page 1 Notify page (writes only) 789 * 0x000 - 0x7FF HW interrupt triggers (PSI, PHB) 790 * 0x800 - 0xFFF forwards and syncs 791 * 792 * Page 2 LSI Trigger page (writes only) (not modeled) 793 * Page 3 LSI SB EOI page (reads only) (not modeled) 794 * 795 * Page 4-7 indirect TIMA 796 */ 797 798 /* 799 * IC - registers MMIO 800 */ 801 static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset, 802 uint64_t val, unsigned size) 803 { 804 PnvXive *xive = PNV_XIVE(opaque); 805 MemoryRegion *sysmem = get_system_memory(); 806 uint32_t reg = offset >> 3; 807 bool is_chip0 = xive->chip->chip_id == 0; 808 809 switch (offset) { 810 811 /* 812 * XIVE CQ (PowerBus bridge) settings 813 */ 814 case CQ_MSGSND: /* msgsnd for doorbells */ 815 case CQ_FIRMASK_OR: /* FIR error reporting */ 816 break; 817 case CQ_PBI_CTL: 818 if (val & CQ_PBI_PC_64K) { 819 xive->pc_shift = 16; 820 } 821 if (val & CQ_PBI_VC_64K) { 822 xive->vc_shift = 16; 823 } 824 break; 825 case CQ_CFG_PB_GEN: /* PowerBus General Configuration */ 826 /* 827 * TODO: CQ_INT_ADDR_OPT for 1-block-per-chip mode 828 */ 829 break; 830 831 /* 832 * XIVE Virtualization Controller settings 833 */ 834 case VC_GLOBAL_CONFIG: 835 break; 836 837 /* 838 * XIVE Presenter Controller settings 839 */ 840 case PC_GLOBAL_CONFIG: 841 /* 842 * PC_GCONF_CHIPID_OVR 843 * Overrides Int command Chip ID with the Chip ID field (DEBUG) 844 */ 845 break; 846 case PC_TCTXT_CFG: 847 /* 848 * TODO: block group support 849 * 850 * PC_TCTXT_CFG_BLKGRP_EN 851 * PC_TCTXT_CFG_HARD_CHIPID_BLK : 852 * Moves the chipid into block field for hardwired CAM compares. 853 * Block offset value is adjusted to 0b0..01 & ThrdId 854 * 855 * Will require changes in xive_presenter_tctx_match(). I am 856 * not sure how to handle that yet. 857 */ 858 859 /* Overrides hardwired chip ID with the chip ID field */ 860 if (val & PC_TCTXT_CHIPID_OVERRIDE) { 861 xive->tctx_chipid = GETFIELD(PC_TCTXT_CHIPID, val); 862 } 863 break; 864 case PC_TCTXT_TRACK: 865 /* 866 * PC_TCTXT_TRACK_EN: 867 * enable block tracking and exchange of block ownership 868 * information between Interrupt controllers 869 */ 870 break; 871 872 /* 873 * Misc settings 874 */ 875 case VC_SBC_CONFIG: /* Store EOI configuration */ 876 /* 877 * Configure store EOI if required by firwmare (skiboot has removed 878 * support recently though) 879 */ 880 if (val & (VC_SBC_CONF_CPLX_CIST | VC_SBC_CONF_CIST_BOTH)) { 881 xive->ipi_source.esb_flags |= XIVE_SRC_STORE_EOI; 882 } 883 break; 884 885 case VC_EQC_CONFIG: /* TODO: silent escalation */ 886 case VC_AIB_TX_ORDER_TAG2: /* relax ordering */ 887 break; 888 889 /* 890 * XIVE BAR settings (XSCOM only) 891 */ 892 case CQ_RST_CTL: 893 /* bit4: resets all BAR registers */ 894 break; 895 896 case CQ_IC_BAR: /* IC BAR. 8 pages */ 897 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 898 if (!(val & CQ_IC_BAR_VALID)) { 899 xive->ic_base = 0; 900 if (xive->regs[reg] & CQ_IC_BAR_VALID) { 901 memory_region_del_subregion(&xive->ic_mmio, 902 &xive->ic_reg_mmio); 903 memory_region_del_subregion(&xive->ic_mmio, 904 &xive->ic_notify_mmio); 905 memory_region_del_subregion(&xive->ic_mmio, 906 &xive->ic_lsi_mmio); 907 memory_region_del_subregion(&xive->ic_mmio, 908 &xive->tm_indirect_mmio); 909 910 memory_region_del_subregion(sysmem, &xive->ic_mmio); 911 } 912 } else { 913 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 914 if (!(xive->regs[reg] & CQ_IC_BAR_VALID)) { 915 memory_region_add_subregion(sysmem, xive->ic_base, 916 &xive->ic_mmio); 917 918 memory_region_add_subregion(&xive->ic_mmio, 0, 919 &xive->ic_reg_mmio); 920 memory_region_add_subregion(&xive->ic_mmio, 921 1ul << xive->ic_shift, 922 &xive->ic_notify_mmio); 923 memory_region_add_subregion(&xive->ic_mmio, 924 2ul << xive->ic_shift, 925 &xive->ic_lsi_mmio); 926 memory_region_add_subregion(&xive->ic_mmio, 927 4ull << xive->ic_shift, 928 &xive->tm_indirect_mmio); 929 } 930 } 931 break; 932 933 case CQ_TM1_BAR: /* TM BAR. 4 pages. Map only once */ 934 case CQ_TM2_BAR: /* second TM BAR. for hotplug. Not modeled */ 935 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 936 if (!(val & CQ_TM_BAR_VALID)) { 937 xive->tm_base = 0; 938 if (xive->regs[reg] & CQ_TM_BAR_VALID && is_chip0) { 939 memory_region_del_subregion(sysmem, &xive->tm_mmio); 940 } 941 } else { 942 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 943 if (!(xive->regs[reg] & CQ_TM_BAR_VALID) && is_chip0) { 944 memory_region_add_subregion(sysmem, xive->tm_base, 945 &xive->tm_mmio); 946 } 947 } 948 break; 949 950 case CQ_PC_BARM: 951 xive->regs[reg] = val; 952 memory_region_set_size(&xive->pc_mmio, pnv_xive_pc_size(xive)); 953 break; 954 case CQ_PC_BAR: /* From 32M to 512G */ 955 if (!(val & CQ_PC_BAR_VALID)) { 956 xive->pc_base = 0; 957 if (xive->regs[reg] & CQ_PC_BAR_VALID) { 958 memory_region_del_subregion(sysmem, &xive->pc_mmio); 959 } 960 } else { 961 xive->pc_base = val & ~(CQ_PC_BAR_VALID); 962 if (!(xive->regs[reg] & CQ_PC_BAR_VALID)) { 963 memory_region_add_subregion(sysmem, xive->pc_base, 964 &xive->pc_mmio); 965 } 966 } 967 break; 968 969 case CQ_VC_BARM: 970 xive->regs[reg] = val; 971 memory_region_set_size(&xive->vc_mmio, pnv_xive_vc_size(xive)); 972 break; 973 case CQ_VC_BAR: /* From 64M to 4TB */ 974 if (!(val & CQ_VC_BAR_VALID)) { 975 xive->vc_base = 0; 976 if (xive->regs[reg] & CQ_VC_BAR_VALID) { 977 memory_region_del_subregion(sysmem, &xive->vc_mmio); 978 } 979 } else { 980 xive->vc_base = val & ~(CQ_VC_BAR_VALID); 981 if (!(xive->regs[reg] & CQ_VC_BAR_VALID)) { 982 memory_region_add_subregion(sysmem, xive->vc_base, 983 &xive->vc_mmio); 984 } 985 } 986 break; 987 988 /* 989 * XIVE Table settings. 990 */ 991 case CQ_TAR: /* Table Address */ 992 break; 993 case CQ_TDR: /* Table Data */ 994 pnv_xive_table_set_data(xive, val); 995 break; 996 997 /* 998 * XIVE VC & PC Virtual Structure Table settings 999 */ 1000 case VC_VSD_TABLE_ADDR: 1001 case PC_VSD_TABLE_ADDR: /* Virtual table selector */ 1002 break; 1003 case VC_VSD_TABLE_DATA: /* Virtual table setting */ 1004 case PC_VSD_TABLE_DATA: 1005 pnv_xive_vst_set_data(xive, val, offset == PC_VSD_TABLE_DATA); 1006 break; 1007 1008 /* 1009 * Interrupt fifo overflow in memory backing store (Not modeled) 1010 */ 1011 case VC_IRQ_CONFIG_IPI: 1012 case VC_IRQ_CONFIG_HW: 1013 case VC_IRQ_CONFIG_CASCADE1: 1014 case VC_IRQ_CONFIG_CASCADE2: 1015 case VC_IRQ_CONFIG_REDIST: 1016 case VC_IRQ_CONFIG_IPI_CASC: 1017 break; 1018 1019 /* 1020 * XIVE hardware thread enablement 1021 */ 1022 case PC_THREAD_EN_REG0: /* Physical Thread Enable */ 1023 case PC_THREAD_EN_REG1: /* Physical Thread Enable (fused core) */ 1024 break; 1025 1026 case PC_THREAD_EN_REG0_SET: 1027 xive->regs[PC_THREAD_EN_REG0 >> 3] |= val; 1028 break; 1029 case PC_THREAD_EN_REG1_SET: 1030 xive->regs[PC_THREAD_EN_REG1 >> 3] |= val; 1031 break; 1032 case PC_THREAD_EN_REG0_CLR: 1033 xive->regs[PC_THREAD_EN_REG0 >> 3] &= ~val; 1034 break; 1035 case PC_THREAD_EN_REG1_CLR: 1036 xive->regs[PC_THREAD_EN_REG1 >> 3] &= ~val; 1037 break; 1038 1039 /* 1040 * Indirect TIMA access set up. Defines the PIR of the HW thread 1041 * to use. 1042 */ 1043 case PC_TCTXT_INDIR0 ... PC_TCTXT_INDIR3: 1044 break; 1045 1046 /* 1047 * XIVE PC & VC cache updates for EAS, NVT and END 1048 */ 1049 case VC_IVC_SCRUB_MASK: 1050 case VC_IVC_SCRUB_TRIG: 1051 break; 1052 1053 case VC_EQC_CWATCH_SPEC: 1054 val &= ~VC_EQC_CWATCH_CONFLICT; /* HW resets this bit */ 1055 break; 1056 case VC_EQC_CWATCH_DAT1 ... VC_EQC_CWATCH_DAT3: 1057 break; 1058 case VC_EQC_CWATCH_DAT0: 1059 /* writing to DATA0 triggers the cache write */ 1060 xive->regs[reg] = val; 1061 pnv_xive_end_update(xive); 1062 break; 1063 case VC_EQC_SCRUB_MASK: 1064 case VC_EQC_SCRUB_TRIG: 1065 /* 1066 * The scrubbing registers flush the cache in RAM and can also 1067 * invalidate. 1068 */ 1069 break; 1070 1071 case PC_VPC_CWATCH_SPEC: 1072 val &= ~PC_VPC_CWATCH_CONFLICT; /* HW resets this bit */ 1073 break; 1074 case PC_VPC_CWATCH_DAT1 ... PC_VPC_CWATCH_DAT7: 1075 break; 1076 case PC_VPC_CWATCH_DAT0: 1077 /* writing to DATA0 triggers the cache write */ 1078 xive->regs[reg] = val; 1079 pnv_xive_nvt_update(xive); 1080 break; 1081 case PC_VPC_SCRUB_MASK: 1082 case PC_VPC_SCRUB_TRIG: 1083 /* 1084 * The scrubbing registers flush the cache in RAM and can also 1085 * invalidate. 1086 */ 1087 break; 1088 1089 1090 /* 1091 * XIVE PC & VC cache invalidation 1092 */ 1093 case PC_AT_KILL: 1094 break; 1095 case VC_AT_MACRO_KILL: 1096 break; 1097 case PC_AT_KILL_MASK: 1098 case VC_AT_MACRO_KILL_MASK: 1099 break; 1100 1101 default: 1102 xive_error(xive, "IC: invalid write to reg=0x%"HWADDR_PRIx, offset); 1103 return; 1104 } 1105 1106 xive->regs[reg] = val; 1107 } 1108 1109 static uint64_t pnv_xive_ic_reg_read(void *opaque, hwaddr offset, unsigned size) 1110 { 1111 PnvXive *xive = PNV_XIVE(opaque); 1112 uint64_t val = 0; 1113 uint32_t reg = offset >> 3; 1114 1115 switch (offset) { 1116 case CQ_CFG_PB_GEN: 1117 case CQ_IC_BAR: 1118 case CQ_TM1_BAR: 1119 case CQ_TM2_BAR: 1120 case CQ_PC_BAR: 1121 case CQ_PC_BARM: 1122 case CQ_VC_BAR: 1123 case CQ_VC_BARM: 1124 case CQ_TAR: 1125 case CQ_TDR: 1126 case CQ_PBI_CTL: 1127 1128 case PC_TCTXT_CFG: 1129 case PC_TCTXT_TRACK: 1130 case PC_TCTXT_INDIR0: 1131 case PC_TCTXT_INDIR1: 1132 case PC_TCTXT_INDIR2: 1133 case PC_TCTXT_INDIR3: 1134 case PC_GLOBAL_CONFIG: 1135 1136 case PC_VPC_SCRUB_MASK: 1137 1138 case VC_GLOBAL_CONFIG: 1139 case VC_AIB_TX_ORDER_TAG2: 1140 1141 case VC_IRQ_CONFIG_IPI: 1142 case VC_IRQ_CONFIG_HW: 1143 case VC_IRQ_CONFIG_CASCADE1: 1144 case VC_IRQ_CONFIG_CASCADE2: 1145 case VC_IRQ_CONFIG_REDIST: 1146 case VC_IRQ_CONFIG_IPI_CASC: 1147 1148 case VC_EQC_SCRUB_MASK: 1149 case VC_IVC_SCRUB_MASK: 1150 case VC_SBC_CONFIG: 1151 case VC_AT_MACRO_KILL_MASK: 1152 case VC_VSD_TABLE_ADDR: 1153 case PC_VSD_TABLE_ADDR: 1154 case VC_VSD_TABLE_DATA: 1155 case PC_VSD_TABLE_DATA: 1156 case PC_THREAD_EN_REG0: 1157 case PC_THREAD_EN_REG1: 1158 val = xive->regs[reg]; 1159 break; 1160 1161 /* 1162 * XIVE hardware thread enablement 1163 */ 1164 case PC_THREAD_EN_REG0_SET: 1165 case PC_THREAD_EN_REG0_CLR: 1166 val = xive->regs[PC_THREAD_EN_REG0 >> 3]; 1167 break; 1168 case PC_THREAD_EN_REG1_SET: 1169 case PC_THREAD_EN_REG1_CLR: 1170 val = xive->regs[PC_THREAD_EN_REG1 >> 3]; 1171 break; 1172 1173 case CQ_MSGSND: /* Identifies which cores have msgsnd enabled. */ 1174 val = 0xffffff0000000000; 1175 break; 1176 1177 /* 1178 * XIVE PC & VC cache updates for EAS, NVT and END 1179 */ 1180 case VC_EQC_CWATCH_SPEC: 1181 xive->regs[reg] = ~(VC_EQC_CWATCH_FULL | VC_EQC_CWATCH_CONFLICT); 1182 val = xive->regs[reg]; 1183 break; 1184 case VC_EQC_CWATCH_DAT0: 1185 /* 1186 * Load DATA registers from cache with data requested by the 1187 * SPEC register 1188 */ 1189 pnv_xive_end_cache_load(xive); 1190 val = xive->regs[reg]; 1191 break; 1192 case VC_EQC_CWATCH_DAT1 ... VC_EQC_CWATCH_DAT3: 1193 val = xive->regs[reg]; 1194 break; 1195 1196 case PC_VPC_CWATCH_SPEC: 1197 xive->regs[reg] = ~(PC_VPC_CWATCH_FULL | PC_VPC_CWATCH_CONFLICT); 1198 val = xive->regs[reg]; 1199 break; 1200 case PC_VPC_CWATCH_DAT0: 1201 /* 1202 * Load DATA registers from cache with data requested by the 1203 * SPEC register 1204 */ 1205 pnv_xive_nvt_cache_load(xive); 1206 val = xive->regs[reg]; 1207 break; 1208 case PC_VPC_CWATCH_DAT1 ... PC_VPC_CWATCH_DAT7: 1209 val = xive->regs[reg]; 1210 break; 1211 1212 case PC_VPC_SCRUB_TRIG: 1213 case VC_IVC_SCRUB_TRIG: 1214 case VC_EQC_SCRUB_TRIG: 1215 xive->regs[reg] &= ~VC_SCRUB_VALID; 1216 val = xive->regs[reg]; 1217 break; 1218 1219 /* 1220 * XIVE PC & VC cache invalidation 1221 */ 1222 case PC_AT_KILL: 1223 xive->regs[reg] &= ~PC_AT_KILL_VALID; 1224 val = xive->regs[reg]; 1225 break; 1226 case VC_AT_MACRO_KILL: 1227 xive->regs[reg] &= ~VC_KILL_VALID; 1228 val = xive->regs[reg]; 1229 break; 1230 1231 /* 1232 * XIVE synchronisation 1233 */ 1234 case VC_EQC_CONFIG: 1235 val = VC_EQC_SYNC_MASK; 1236 break; 1237 1238 default: 1239 xive_error(xive, "IC: invalid read reg=0x%"HWADDR_PRIx, offset); 1240 } 1241 1242 return val; 1243 } 1244 1245 static const MemoryRegionOps pnv_xive_ic_reg_ops = { 1246 .read = pnv_xive_ic_reg_read, 1247 .write = pnv_xive_ic_reg_write, 1248 .endianness = DEVICE_BIG_ENDIAN, 1249 .valid = { 1250 .min_access_size = 8, 1251 .max_access_size = 8, 1252 }, 1253 .impl = { 1254 .min_access_size = 8, 1255 .max_access_size = 8, 1256 }, 1257 }; 1258 1259 /* 1260 * IC - Notify MMIO port page (write only) 1261 */ 1262 #define PNV_XIVE_FORWARD_IPI 0x800 /* Forward IPI */ 1263 #define PNV_XIVE_FORWARD_HW 0x880 /* Forward HW */ 1264 #define PNV_XIVE_FORWARD_OS_ESC 0x900 /* Forward OS escalation */ 1265 #define PNV_XIVE_FORWARD_HW_ESC 0x980 /* Forward Hyp escalation */ 1266 #define PNV_XIVE_FORWARD_REDIS 0xa00 /* Forward Redistribution */ 1267 #define PNV_XIVE_RESERVED5 0xa80 /* Cache line 5 PowerBUS operation */ 1268 #define PNV_XIVE_RESERVED6 0xb00 /* Cache line 6 PowerBUS operation */ 1269 #define PNV_XIVE_RESERVED7 0xb80 /* Cache line 7 PowerBUS operation */ 1270 1271 /* VC synchronisation */ 1272 #define PNV_XIVE_SYNC_IPI 0xc00 /* Sync IPI */ 1273 #define PNV_XIVE_SYNC_HW 0xc80 /* Sync HW */ 1274 #define PNV_XIVE_SYNC_OS_ESC 0xd00 /* Sync OS escalation */ 1275 #define PNV_XIVE_SYNC_HW_ESC 0xd80 /* Sync Hyp escalation */ 1276 #define PNV_XIVE_SYNC_REDIS 0xe00 /* Sync Redistribution */ 1277 1278 /* PC synchronisation */ 1279 #define PNV_XIVE_SYNC_PULL 0xe80 /* Sync pull context */ 1280 #define PNV_XIVE_SYNC_PUSH 0xf00 /* Sync push context */ 1281 #define PNV_XIVE_SYNC_VPC 0xf80 /* Sync remove VPC store */ 1282 1283 static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr addr, uint64_t val) 1284 { 1285 uint8_t blk; 1286 uint32_t idx; 1287 1288 if (val & XIVE_TRIGGER_END) { 1289 xive_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1290 addr, val); 1291 return; 1292 } 1293 1294 /* 1295 * Forward the source event notification directly to the Router. 1296 * The source interrupt number should already be correctly encoded 1297 * with the chip block id by the sending device (PHB, PSI). 1298 */ 1299 blk = XIVE_EAS_BLOCK(val); 1300 idx = XIVE_EAS_INDEX(val); 1301 1302 xive_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx)); 1303 } 1304 1305 static void pnv_xive_ic_notify_write(void *opaque, hwaddr addr, uint64_t val, 1306 unsigned size) 1307 { 1308 PnvXive *xive = PNV_XIVE(opaque); 1309 1310 /* VC: HW triggers */ 1311 switch (addr) { 1312 case 0x000 ... 0x7FF: 1313 pnv_xive_ic_hw_trigger(opaque, addr, val); 1314 break; 1315 1316 /* VC: Forwarded IRQs */ 1317 case PNV_XIVE_FORWARD_IPI: 1318 case PNV_XIVE_FORWARD_HW: 1319 case PNV_XIVE_FORWARD_OS_ESC: 1320 case PNV_XIVE_FORWARD_HW_ESC: 1321 case PNV_XIVE_FORWARD_REDIS: 1322 /* TODO: forwarded IRQs. Should be like HW triggers */ 1323 xive_error(xive, "IC: forwarded at @0x%"HWADDR_PRIx" IRQ 0x%"PRIx64, 1324 addr, val); 1325 break; 1326 1327 /* VC syncs */ 1328 case PNV_XIVE_SYNC_IPI: 1329 case PNV_XIVE_SYNC_HW: 1330 case PNV_XIVE_SYNC_OS_ESC: 1331 case PNV_XIVE_SYNC_HW_ESC: 1332 case PNV_XIVE_SYNC_REDIS: 1333 break; 1334 1335 /* PC syncs */ 1336 case PNV_XIVE_SYNC_PULL: 1337 case PNV_XIVE_SYNC_PUSH: 1338 case PNV_XIVE_SYNC_VPC: 1339 break; 1340 1341 default: 1342 xive_error(xive, "IC: invalid notify write @%"HWADDR_PRIx, addr); 1343 } 1344 } 1345 1346 static uint64_t pnv_xive_ic_notify_read(void *opaque, hwaddr addr, 1347 unsigned size) 1348 { 1349 PnvXive *xive = PNV_XIVE(opaque); 1350 1351 /* loads are invalid */ 1352 xive_error(xive, "IC: invalid notify read @%"HWADDR_PRIx, addr); 1353 return -1; 1354 } 1355 1356 static const MemoryRegionOps pnv_xive_ic_notify_ops = { 1357 .read = pnv_xive_ic_notify_read, 1358 .write = pnv_xive_ic_notify_write, 1359 .endianness = DEVICE_BIG_ENDIAN, 1360 .valid = { 1361 .min_access_size = 8, 1362 .max_access_size = 8, 1363 }, 1364 .impl = { 1365 .min_access_size = 8, 1366 .max_access_size = 8, 1367 }, 1368 }; 1369 1370 /* 1371 * IC - LSI MMIO handlers (not modeled) 1372 */ 1373 1374 static void pnv_xive_ic_lsi_write(void *opaque, hwaddr addr, 1375 uint64_t val, unsigned size) 1376 { 1377 PnvXive *xive = PNV_XIVE(opaque); 1378 1379 xive_error(xive, "IC: LSI invalid write @%"HWADDR_PRIx, addr); 1380 } 1381 1382 static uint64_t pnv_xive_ic_lsi_read(void *opaque, hwaddr addr, unsigned size) 1383 { 1384 PnvXive *xive = PNV_XIVE(opaque); 1385 1386 xive_error(xive, "IC: LSI invalid read @%"HWADDR_PRIx, addr); 1387 return -1; 1388 } 1389 1390 static const MemoryRegionOps pnv_xive_ic_lsi_ops = { 1391 .read = pnv_xive_ic_lsi_read, 1392 .write = pnv_xive_ic_lsi_write, 1393 .endianness = DEVICE_BIG_ENDIAN, 1394 .valid = { 1395 .min_access_size = 8, 1396 .max_access_size = 8, 1397 }, 1398 .impl = { 1399 .min_access_size = 8, 1400 .max_access_size = 8, 1401 }, 1402 }; 1403 1404 /* 1405 * IC - Indirect TIMA MMIO handlers 1406 */ 1407 1408 /* 1409 * When the TIMA is accessed from the indirect page, the thread id of 1410 * the target CPU is configured in the PC_TCTXT_INDIR0 register before 1411 * use. This is used for resets and for debug purpose also. 1412 */ 1413 static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive) 1414 { 1415 PnvChip *chip = xive->chip; 1416 uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3]; 1417 PowerPCCPU *cpu = NULL; 1418 int pir; 1419 1420 if (!(tctxt_indir & PC_TCTXT_INDIR_VALID)) { 1421 xive_error(xive, "IC: no indirect TIMA access in progress"); 1422 return NULL; 1423 } 1424 1425 pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir); 1426 cpu = pnv_chip_find_cpu(chip, pir); 1427 if (!cpu) { 1428 xive_error(xive, "IC: invalid PIR %x for indirect access", pir); 1429 return NULL; 1430 } 1431 1432 /* Check that HW thread is XIVE enabled */ 1433 if (!pnv_xive_is_cpu_enabled(xive, cpu)) { 1434 xive_error(xive, "IC: CPU %x is not enabled", pir); 1435 } 1436 1437 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1438 } 1439 1440 static void xive_tm_indirect_write(void *opaque, hwaddr offset, 1441 uint64_t value, unsigned size) 1442 { 1443 XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); 1444 1445 xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); 1446 } 1447 1448 static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset, 1449 unsigned size) 1450 { 1451 XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); 1452 1453 return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); 1454 } 1455 1456 static const MemoryRegionOps xive_tm_indirect_ops = { 1457 .read = xive_tm_indirect_read, 1458 .write = xive_tm_indirect_write, 1459 .endianness = DEVICE_BIG_ENDIAN, 1460 .valid = { 1461 .min_access_size = 1, 1462 .max_access_size = 8, 1463 }, 1464 .impl = { 1465 .min_access_size = 1, 1466 .max_access_size = 8, 1467 }, 1468 }; 1469 1470 /* 1471 * Interrupt controller XSCOM region. 1472 */ 1473 static uint64_t pnv_xive_xscom_read(void *opaque, hwaddr addr, unsigned size) 1474 { 1475 switch (addr >> 3) { 1476 case X_VC_EQC_CONFIG: 1477 /* FIXME (skiboot): This is the only XSCOM load. Bizarre. */ 1478 return VC_EQC_SYNC_MASK; 1479 default: 1480 return pnv_xive_ic_reg_read(opaque, addr, size); 1481 } 1482 } 1483 1484 static void pnv_xive_xscom_write(void *opaque, hwaddr addr, 1485 uint64_t val, unsigned size) 1486 { 1487 pnv_xive_ic_reg_write(opaque, addr, val, size); 1488 } 1489 1490 static const MemoryRegionOps pnv_xive_xscom_ops = { 1491 .read = pnv_xive_xscom_read, 1492 .write = pnv_xive_xscom_write, 1493 .endianness = DEVICE_BIG_ENDIAN, 1494 .valid = { 1495 .min_access_size = 8, 1496 .max_access_size = 8, 1497 }, 1498 .impl = { 1499 .min_access_size = 8, 1500 .max_access_size = 8, 1501 } 1502 }; 1503 1504 /* 1505 * Virtualization Controller MMIO region containing the IPI and END ESB pages 1506 */ 1507 static uint64_t pnv_xive_vc_read(void *opaque, hwaddr offset, 1508 unsigned size) 1509 { 1510 PnvXive *xive = PNV_XIVE(opaque); 1511 uint64_t edt_index = offset >> pnv_xive_edt_shift(xive); 1512 uint64_t edt_type = 0; 1513 uint64_t edt_offset; 1514 MemTxResult result; 1515 AddressSpace *edt_as = NULL; 1516 uint64_t ret = -1; 1517 1518 if (edt_index < XIVE_TABLE_EDT_MAX) { 1519 edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[edt_index]); 1520 } 1521 1522 switch (edt_type) { 1523 case CQ_TDR_EDT_IPI: 1524 edt_as = &xive->ipi_as; 1525 break; 1526 case CQ_TDR_EDT_EQ: 1527 edt_as = &xive->end_as; 1528 break; 1529 default: 1530 xive_error(xive, "VC: invalid EDT type for read @%"HWADDR_PRIx, offset); 1531 return -1; 1532 } 1533 1534 /* Remap the offset for the targeted address space */ 1535 edt_offset = pnv_xive_edt_offset(xive, offset, edt_type); 1536 1537 ret = address_space_ldq(edt_as, edt_offset, MEMTXATTRS_UNSPECIFIED, 1538 &result); 1539 1540 if (result != MEMTX_OK) { 1541 xive_error(xive, "VC: %s read failed at @0x%"HWADDR_PRIx " -> @0x%" 1542 HWADDR_PRIx, edt_type == CQ_TDR_EDT_IPI ? "IPI" : "END", 1543 offset, edt_offset); 1544 return -1; 1545 } 1546 1547 return ret; 1548 } 1549 1550 static void pnv_xive_vc_write(void *opaque, hwaddr offset, 1551 uint64_t val, unsigned size) 1552 { 1553 PnvXive *xive = PNV_XIVE(opaque); 1554 uint64_t edt_index = offset >> pnv_xive_edt_shift(xive); 1555 uint64_t edt_type = 0; 1556 uint64_t edt_offset; 1557 MemTxResult result; 1558 AddressSpace *edt_as = NULL; 1559 1560 if (edt_index < XIVE_TABLE_EDT_MAX) { 1561 edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[edt_index]); 1562 } 1563 1564 switch (edt_type) { 1565 case CQ_TDR_EDT_IPI: 1566 edt_as = &xive->ipi_as; 1567 break; 1568 case CQ_TDR_EDT_EQ: 1569 edt_as = &xive->end_as; 1570 break; 1571 default: 1572 xive_error(xive, "VC: invalid EDT type for write @%"HWADDR_PRIx, 1573 offset); 1574 return; 1575 } 1576 1577 /* Remap the offset for the targeted address space */ 1578 edt_offset = pnv_xive_edt_offset(xive, offset, edt_type); 1579 1580 address_space_stq(edt_as, edt_offset, val, MEMTXATTRS_UNSPECIFIED, &result); 1581 if (result != MEMTX_OK) { 1582 xive_error(xive, "VC: write failed at @0x%"HWADDR_PRIx, edt_offset); 1583 } 1584 } 1585 1586 static const MemoryRegionOps pnv_xive_vc_ops = { 1587 .read = pnv_xive_vc_read, 1588 .write = pnv_xive_vc_write, 1589 .endianness = DEVICE_BIG_ENDIAN, 1590 .valid = { 1591 .min_access_size = 8, 1592 .max_access_size = 8, 1593 }, 1594 .impl = { 1595 .min_access_size = 8, 1596 .max_access_size = 8, 1597 }, 1598 }; 1599 1600 /* 1601 * Presenter Controller MMIO region. The Virtualization Controller 1602 * updates the IPB in the NVT table when required. Not modeled. 1603 */ 1604 static uint64_t pnv_xive_pc_read(void *opaque, hwaddr addr, 1605 unsigned size) 1606 { 1607 PnvXive *xive = PNV_XIVE(opaque); 1608 1609 xive_error(xive, "PC: invalid read @%"HWADDR_PRIx, addr); 1610 return -1; 1611 } 1612 1613 static void pnv_xive_pc_write(void *opaque, hwaddr addr, 1614 uint64_t value, unsigned size) 1615 { 1616 PnvXive *xive = PNV_XIVE(opaque); 1617 1618 xive_error(xive, "PC: invalid write to VC @%"HWADDR_PRIx, addr); 1619 } 1620 1621 static const MemoryRegionOps pnv_xive_pc_ops = { 1622 .read = pnv_xive_pc_read, 1623 .write = pnv_xive_pc_write, 1624 .endianness = DEVICE_BIG_ENDIAN, 1625 .valid = { 1626 .min_access_size = 8, 1627 .max_access_size = 8, 1628 }, 1629 .impl = { 1630 .min_access_size = 8, 1631 .max_access_size = 8, 1632 }, 1633 }; 1634 1635 void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) 1636 { 1637 XiveRouter *xrtr = XIVE_ROUTER(xive); 1638 uint8_t blk = xive->chip->chip_id; 1639 uint32_t srcno0 = XIVE_EAS(blk, 0); 1640 uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk); 1641 XiveEAS eas; 1642 XiveEND end; 1643 int i; 1644 1645 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, 1646 srcno0 + nr_ipis - 1); 1647 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); 1648 1649 monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, 1650 srcno0 + nr_ipis - 1); 1651 for (i = 0; i < nr_ipis; i++) { 1652 if (xive_router_get_eas(xrtr, blk, i, &eas)) { 1653 break; 1654 } 1655 if (!xive_eas_is_masked(&eas)) { 1656 xive_eas_pic_print_info(&eas, i, mon); 1657 } 1658 } 1659 1660 monitor_printf(mon, "XIVE[%x] ENDT\n", blk); 1661 i = 0; 1662 while (!xive_router_get_end(xrtr, blk, i, &end)) { 1663 xive_end_pic_print_info(&end, i++, mon); 1664 } 1665 1666 monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk); 1667 i = 0; 1668 while (!xive_router_get_end(xrtr, blk, i, &end)) { 1669 xive_end_eas_pic_print_info(&end, i++, mon); 1670 } 1671 } 1672 1673 static void pnv_xive_reset(void *dev) 1674 { 1675 PnvXive *xive = PNV_XIVE(dev); 1676 XiveSource *xsrc = &xive->ipi_source; 1677 XiveENDSource *end_xsrc = &xive->end_source; 1678 1679 /* 1680 * Use the PnvChip id to identify the XIVE interrupt controller. 1681 * It can be overriden by configuration at runtime. 1682 */ 1683 xive->tctx_chipid = xive->chip->chip_id; 1684 1685 /* Default page size (Should be changed at runtime to 64k) */ 1686 xive->ic_shift = xive->vc_shift = xive->pc_shift = 12; 1687 1688 /* Clear subregions */ 1689 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 1690 memory_region_del_subregion(&xive->ipi_edt_mmio, &xsrc->esb_mmio); 1691 } 1692 1693 if (memory_region_is_mapped(&xive->ipi_edt_mmio)) { 1694 memory_region_del_subregion(&xive->ipi_mmio, &xive->ipi_edt_mmio); 1695 } 1696 1697 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 1698 memory_region_del_subregion(&xive->end_edt_mmio, &end_xsrc->esb_mmio); 1699 } 1700 1701 if (memory_region_is_mapped(&xive->end_edt_mmio)) { 1702 memory_region_del_subregion(&xive->end_mmio, &xive->end_edt_mmio); 1703 } 1704 } 1705 1706 static void pnv_xive_init(Object *obj) 1707 { 1708 PnvXive *xive = PNV_XIVE(obj); 1709 1710 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 1711 sizeof(xive->ipi_source), TYPE_XIVE_SOURCE, 1712 &error_abort, NULL); 1713 object_initialize_child(obj, "end_source", &xive->end_source, 1714 sizeof(xive->end_source), TYPE_XIVE_END_SOURCE, 1715 &error_abort, NULL); 1716 } 1717 1718 /* 1719 * Maximum number of IRQs and ENDs supported by HW 1720 */ 1721 #define PNV_XIVE_NR_IRQS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1722 #define PNV_XIVE_NR_ENDS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1723 1724 static void pnv_xive_realize(DeviceState *dev, Error **errp) 1725 { 1726 PnvXive *xive = PNV_XIVE(dev); 1727 XiveSource *xsrc = &xive->ipi_source; 1728 XiveENDSource *end_xsrc = &xive->end_source; 1729 Error *local_err = NULL; 1730 1731 assert(xive->chip); 1732 1733 /* 1734 * The XiveSource and XiveENDSource objects are realized with the 1735 * maximum allowed HW configuration. The ESB MMIO regions will be 1736 * resized dynamically when the controller is configured by the FW 1737 * to limit accesses to resources not provisioned. 1738 */ 1739 object_property_set_int(OBJECT(xsrc), PNV_XIVE_NR_IRQS, "nr-irqs", 1740 &error_fatal); 1741 object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive", 1742 &error_abort); 1743 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); 1744 if (local_err) { 1745 error_propagate(errp, local_err); 1746 return; 1747 } 1748 1749 object_property_set_int(OBJECT(end_xsrc), PNV_XIVE_NR_ENDS, "nr-ends", 1750 &error_fatal); 1751 object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive", 1752 &error_abort); 1753 object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); 1754 if (local_err) { 1755 error_propagate(errp, local_err); 1756 return; 1757 } 1758 1759 /* Default page size. Generally changed at runtime to 64k */ 1760 xive->ic_shift = xive->vc_shift = xive->pc_shift = 12; 1761 1762 /* XSCOM region, used for initial configuration of the BARs */ 1763 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), &pnv_xive_xscom_ops, 1764 xive, "xscom-xive", PNV9_XSCOM_XIVE_SIZE << 3); 1765 1766 /* Interrupt controller MMIO regions */ 1767 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 1768 PNV9_XIVE_IC_SIZE); 1769 1770 memory_region_init_io(&xive->ic_reg_mmio, OBJECT(dev), &pnv_xive_ic_reg_ops, 1771 xive, "xive-ic-reg", 1 << xive->ic_shift); 1772 memory_region_init_io(&xive->ic_notify_mmio, OBJECT(dev), 1773 &pnv_xive_ic_notify_ops, 1774 xive, "xive-ic-notify", 1 << xive->ic_shift); 1775 1776 /* The Pervasive LSI trigger and EOI pages (not modeled) */ 1777 memory_region_init_io(&xive->ic_lsi_mmio, OBJECT(dev), &pnv_xive_ic_lsi_ops, 1778 xive, "xive-ic-lsi", 2 << xive->ic_shift); 1779 1780 /* Thread Interrupt Management Area (Indirect) */ 1781 memory_region_init_io(&xive->tm_indirect_mmio, OBJECT(dev), 1782 &xive_tm_indirect_ops, 1783 xive, "xive-tima-indirect", PNV9_XIVE_TM_SIZE); 1784 /* 1785 * Overall Virtualization Controller MMIO region containing the 1786 * IPI ESB pages and END ESB pages. The layout is defined by the 1787 * EDT "Domain table" and the accesses are dispatched using 1788 * address spaces for each. 1789 */ 1790 memory_region_init_io(&xive->vc_mmio, OBJECT(xive), &pnv_xive_vc_ops, xive, 1791 "xive-vc", PNV9_XIVE_VC_SIZE); 1792 1793 memory_region_init(&xive->ipi_mmio, OBJECT(xive), "xive-vc-ipi", 1794 PNV9_XIVE_VC_SIZE); 1795 address_space_init(&xive->ipi_as, &xive->ipi_mmio, "xive-vc-ipi"); 1796 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-vc-end", 1797 PNV9_XIVE_VC_SIZE); 1798 address_space_init(&xive->end_as, &xive->end_mmio, "xive-vc-end"); 1799 1800 /* 1801 * The MMIO windows exposing the IPI ESBs and the END ESBs in the 1802 * VC region. Their size is configured by the FW in the EDT table. 1803 */ 1804 memory_region_init(&xive->ipi_edt_mmio, OBJECT(xive), "xive-vc-ipi-edt", 0); 1805 memory_region_init(&xive->end_edt_mmio, OBJECT(xive), "xive-vc-end-edt", 0); 1806 1807 /* Presenter Controller MMIO region (not modeled) */ 1808 memory_region_init_io(&xive->pc_mmio, OBJECT(xive), &pnv_xive_pc_ops, xive, 1809 "xive-pc", PNV9_XIVE_PC_SIZE); 1810 1811 /* Thread Interrupt Management Area (Direct) */ 1812 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, 1813 xive, "xive-tima", PNV9_XIVE_TM_SIZE); 1814 1815 qemu_register_reset(pnv_xive_reset, dev); 1816 } 1817 1818 static int pnv_xive_dt_xscom(PnvXScomInterface *dev, void *fdt, 1819 int xscom_offset) 1820 { 1821 const char compat[] = "ibm,power9-xive-x"; 1822 char *name; 1823 int offset; 1824 uint32_t lpc_pcba = PNV9_XSCOM_XIVE_BASE; 1825 uint32_t reg[] = { 1826 cpu_to_be32(lpc_pcba), 1827 cpu_to_be32(PNV9_XSCOM_XIVE_SIZE) 1828 }; 1829 1830 name = g_strdup_printf("xive@%x", lpc_pcba); 1831 offset = fdt_add_subnode(fdt, xscom_offset, name); 1832 _FDT(offset); 1833 g_free(name); 1834 1835 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 1836 _FDT((fdt_setprop(fdt, offset, "compatible", compat, 1837 sizeof(compat)))); 1838 return 0; 1839 } 1840 1841 static Property pnv_xive_properties[] = { 1842 DEFINE_PROP_UINT64("ic-bar", PnvXive, ic_base, 0), 1843 DEFINE_PROP_UINT64("vc-bar", PnvXive, vc_base, 0), 1844 DEFINE_PROP_UINT64("pc-bar", PnvXive, pc_base, 0), 1845 DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0), 1846 /* The PnvChip id identifies the XIVE interrupt controller. */ 1847 DEFINE_PROP_LINK("chip", PnvXive, chip, TYPE_PNV_CHIP, PnvChip *), 1848 DEFINE_PROP_END_OF_LIST(), 1849 }; 1850 1851 static void pnv_xive_class_init(ObjectClass *klass, void *data) 1852 { 1853 DeviceClass *dc = DEVICE_CLASS(klass); 1854 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 1855 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 1856 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1857 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 1858 1859 xdc->dt_xscom = pnv_xive_dt_xscom; 1860 1861 dc->desc = "PowerNV XIVE Interrupt Controller"; 1862 dc->realize = pnv_xive_realize; 1863 dc->props = pnv_xive_properties; 1864 1865 xrc->get_eas = pnv_xive_get_eas; 1866 xrc->get_end = pnv_xive_get_end; 1867 xrc->write_end = pnv_xive_write_end; 1868 xrc->get_nvt = pnv_xive_get_nvt; 1869 xrc->write_nvt = pnv_xive_write_nvt; 1870 xrc->get_tctx = pnv_xive_get_tctx; 1871 1872 xnc->notify = pnv_xive_notify; 1873 xpc->match_nvt = pnv_xive_match_nvt; 1874 }; 1875 1876 static const TypeInfo pnv_xive_info = { 1877 .name = TYPE_PNV_XIVE, 1878 .parent = TYPE_XIVE_ROUTER, 1879 .instance_init = pnv_xive_init, 1880 .instance_size = sizeof(PnvXive), 1881 .class_init = pnv_xive_class_init, 1882 .interfaces = (InterfaceInfo[]) { 1883 { TYPE_PNV_XSCOM_INTERFACE }, 1884 { } 1885 } 1886 }; 1887 1888 static void pnv_xive_register_types(void) 1889 { 1890 type_register_static(&pnv_xive_info); 1891 } 1892 1893 type_init(pnv_xive_register_types) 1894