1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "sysemu/reset.h" 18 #include "monitor/monitor.h" 19 #include "hw/ppc/fdt.h" 20 #include "hw/ppc/pnv.h" 21 #include "hw/ppc/pnv_core.h" 22 #include "hw/ppc/pnv_xscom.h" 23 #include "hw/ppc/pnv_xive.h" 24 #include "hw/ppc/xive_regs.h" 25 #include "hw/qdev-properties.h" 26 #include "hw/ppc/ppc.h" 27 #include "trace.h" 28 29 #include <libfdt.h> 30 31 #include "pnv_xive_regs.h" 32 33 #undef XIVE_DEBUG 34 35 /* 36 * Virtual structures table (VST) 37 */ 38 #define SBE_PER_BYTE 4 39 40 typedef struct XiveVstInfo { 41 const char *name; 42 uint32_t size; 43 uint32_t max_blocks; 44 } XiveVstInfo; 45 46 static const XiveVstInfo vst_infos[] = { 47 [VST_TSEL_IVT] = { "EAT", sizeof(XiveEAS), 16 }, 48 [VST_TSEL_SBE] = { "SBE", 1, 16 }, 49 [VST_TSEL_EQDT] = { "ENDT", sizeof(XiveEND), 16 }, 50 [VST_TSEL_VPDT] = { "VPDT", sizeof(XiveNVT), 32 }, 51 52 /* 53 * Interrupt fifo backing store table (not modeled) : 54 * 55 * 0 - IPI, 56 * 1 - HWD, 57 * 2 - First escalate, 58 * 3 - Second escalate, 59 * 4 - Redistribution, 60 * 5 - IPI cascaded queue ? 61 */ 62 [VST_TSEL_IRQ] = { "IRQ", 1, 6 }, 63 }; 64 65 #define xive_error(xive, fmt, ...) \ 66 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 67 (xive)->chip->chip_id, ## __VA_ARGS__); 68 69 /* 70 * QEMU version of the GETFIELD/SETFIELD macros 71 * 72 * TODO: It might be better to use the existing extract64() and 73 * deposit64() but this means that all the register definitions will 74 * change and become incompatible with the ones found in skiboot. 75 * 76 * Keep it as it is for now until we find a common ground. 77 */ 78 static inline uint64_t GETFIELD(uint64_t mask, uint64_t word) 79 { 80 return (word & mask) >> ctz64(mask); 81 } 82 83 static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, 84 uint64_t value) 85 { 86 return (word & ~mask) | ((value << ctz64(mask)) & mask); 87 } 88 89 /* 90 * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID 91 * field overrides the hardwired chip ID in the Powerbus operations 92 * and for CAM compares 93 */ 94 static uint8_t pnv_xive_block_id(PnvXive *xive) 95 { 96 uint8_t blk = xive->chip->chip_id; 97 uint64_t cfg_val = xive->regs[PC_TCTXT_CFG >> 3]; 98 99 if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) { 100 blk = GETFIELD(PC_TCTXT_CHIPID, cfg_val); 101 } 102 103 return blk; 104 } 105 106 /* 107 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 108 * of the chips is good enough. 109 * 110 * TODO: Block scope support 111 */ 112 static PnvXive *pnv_xive_get_remote(uint8_t blk) 113 { 114 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 115 int i; 116 117 for (i = 0; i < pnv->num_chips; i++) { 118 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 119 PnvXive *xive = &chip9->xive; 120 121 if (pnv_xive_block_id(xive) == blk) { 122 return xive; 123 } 124 } 125 return NULL; 126 } 127 128 /* 129 * VST accessors for SBE, EAT, ENDT, NVT 130 * 131 * Indirect VST tables are arrays of VSDs pointing to a page (of same 132 * size). Each page is a direct VST table. 133 */ 134 135 #define XIVE_VSD_SIZE 8 136 137 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 138 static uint64_t pnv_xive_vst_page_size_allowed(uint32_t page_shift) 139 { 140 return page_shift == 12 || page_shift == 16 || 141 page_shift == 21 || page_shift == 24; 142 } 143 144 static uint64_t pnv_xive_vst_addr_direct(PnvXive *xive, uint32_t type, 145 uint64_t vsd, uint32_t idx) 146 { 147 const XiveVstInfo *info = &vst_infos[type]; 148 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 149 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 150 uint32_t idx_max; 151 152 idx_max = vst_tsize / info->size - 1; 153 if (idx > idx_max) { 154 #ifdef XIVE_DEBUG 155 xive_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 156 info->name, idx, idx_max); 157 #endif 158 return 0; 159 } 160 161 return vst_addr + idx * info->size; 162 } 163 164 static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xive, uint32_t type, 165 uint64_t vsd, uint32_t idx) 166 { 167 const XiveVstInfo *info = &vst_infos[type]; 168 uint64_t vsd_addr; 169 uint32_t vsd_idx; 170 uint32_t page_shift; 171 uint32_t vst_per_page; 172 173 /* Get the page size of the indirect table. */ 174 vsd_addr = vsd & VSD_ADDRESS_MASK; 175 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 176 177 if (!(vsd & VSD_ADDRESS_MASK)) { 178 #ifdef XIVE_DEBUG 179 xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 180 #endif 181 return 0; 182 } 183 184 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 185 186 if (!pnv_xive_vst_page_size_allowed(page_shift)) { 187 xive_error(xive, "VST: invalid %s page shift %d", info->name, 188 page_shift); 189 return 0; 190 } 191 192 vst_per_page = (1ull << page_shift) / info->size; 193 vsd_idx = idx / vst_per_page; 194 195 /* Load the VSD we are looking for, if not already done */ 196 if (vsd_idx) { 197 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 198 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, 199 MEMTXATTRS_UNSPECIFIED); 200 201 if (!(vsd & VSD_ADDRESS_MASK)) { 202 #ifdef XIVE_DEBUG 203 xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 204 #endif 205 return 0; 206 } 207 208 /* 209 * Check that the pages have a consistent size across the 210 * indirect table 211 */ 212 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 213 xive_error(xive, "VST: %s entry %x indirect page size differ !?", 214 info->name, idx); 215 return 0; 216 } 217 } 218 219 return pnv_xive_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 220 } 221 222 static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk, 223 uint32_t idx) 224 { 225 const XiveVstInfo *info = &vst_infos[type]; 226 uint64_t vsd; 227 228 if (blk >= info->max_blocks) { 229 xive_error(xive, "VST: invalid block id %d for VST %s %d !?", 230 blk, info->name, idx); 231 return 0; 232 } 233 234 vsd = xive->vsds[type][blk]; 235 236 /* Remote VST access */ 237 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 238 xive = pnv_xive_get_remote(blk); 239 240 return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; 241 } 242 243 if (VSD_INDIRECT & vsd) { 244 return pnv_xive_vst_addr_indirect(xive, type, vsd, idx); 245 } 246 247 return pnv_xive_vst_addr_direct(xive, type, vsd, idx); 248 } 249 250 static int pnv_xive_vst_read(PnvXive *xive, uint32_t type, uint8_t blk, 251 uint32_t idx, void *data) 252 { 253 const XiveVstInfo *info = &vst_infos[type]; 254 uint64_t addr = pnv_xive_vst_addr(xive, type, blk, idx); 255 256 if (!addr) { 257 return -1; 258 } 259 260 cpu_physical_memory_read(addr, data, info->size); 261 return 0; 262 } 263 264 #define XIVE_VST_WORD_ALL -1 265 266 static int pnv_xive_vst_write(PnvXive *xive, uint32_t type, uint8_t blk, 267 uint32_t idx, void *data, uint32_t word_number) 268 { 269 const XiveVstInfo *info = &vst_infos[type]; 270 uint64_t addr = pnv_xive_vst_addr(xive, type, blk, idx); 271 272 if (!addr) { 273 return -1; 274 } 275 276 if (word_number == XIVE_VST_WORD_ALL) { 277 cpu_physical_memory_write(addr, data, info->size); 278 } else { 279 cpu_physical_memory_write(addr + word_number * 4, 280 data + word_number * 4, 4); 281 } 282 return 0; 283 } 284 285 static int pnv_xive_get_end(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 286 XiveEND *end) 287 { 288 return pnv_xive_vst_read(PNV_XIVE(xrtr), VST_TSEL_EQDT, blk, idx, end); 289 } 290 291 static int pnv_xive_write_end(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 292 XiveEND *end, uint8_t word_number) 293 { 294 return pnv_xive_vst_write(PNV_XIVE(xrtr), VST_TSEL_EQDT, blk, idx, end, 295 word_number); 296 } 297 298 static int pnv_xive_end_update(PnvXive *xive) 299 { 300 uint8_t blk = GETFIELD(VC_EQC_CWATCH_BLOCKID, 301 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 302 uint32_t idx = GETFIELD(VC_EQC_CWATCH_OFFSET, 303 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 304 int i; 305 uint64_t eqc_watch[4]; 306 307 for (i = 0; i < ARRAY_SIZE(eqc_watch); i++) { 308 eqc_watch[i] = cpu_to_be64(xive->regs[(VC_EQC_CWATCH_DAT0 >> 3) + i]); 309 } 310 311 return pnv_xive_vst_write(xive, VST_TSEL_EQDT, blk, idx, eqc_watch, 312 XIVE_VST_WORD_ALL); 313 } 314 315 static void pnv_xive_end_cache_load(PnvXive *xive) 316 { 317 uint8_t blk = GETFIELD(VC_EQC_CWATCH_BLOCKID, 318 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 319 uint32_t idx = GETFIELD(VC_EQC_CWATCH_OFFSET, 320 xive->regs[(VC_EQC_CWATCH_SPEC >> 3)]); 321 uint64_t eqc_watch[4] = { 0 }; 322 int i; 323 324 if (pnv_xive_vst_read(xive, VST_TSEL_EQDT, blk, idx, eqc_watch)) { 325 xive_error(xive, "VST: no END entry %x/%x !?", blk, idx); 326 } 327 328 for (i = 0; i < ARRAY_SIZE(eqc_watch); i++) { 329 xive->regs[(VC_EQC_CWATCH_DAT0 >> 3) + i] = be64_to_cpu(eqc_watch[i]); 330 } 331 } 332 333 static int pnv_xive_get_nvt(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 334 XiveNVT *nvt) 335 { 336 return pnv_xive_vst_read(PNV_XIVE(xrtr), VST_TSEL_VPDT, blk, idx, nvt); 337 } 338 339 static int pnv_xive_write_nvt(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 340 XiveNVT *nvt, uint8_t word_number) 341 { 342 return pnv_xive_vst_write(PNV_XIVE(xrtr), VST_TSEL_VPDT, blk, idx, nvt, 343 word_number); 344 } 345 346 static int pnv_xive_nvt_update(PnvXive *xive) 347 { 348 uint8_t blk = GETFIELD(PC_VPC_CWATCH_BLOCKID, 349 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 350 uint32_t idx = GETFIELD(PC_VPC_CWATCH_OFFSET, 351 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 352 int i; 353 uint64_t vpc_watch[8]; 354 355 for (i = 0; i < ARRAY_SIZE(vpc_watch); i++) { 356 vpc_watch[i] = cpu_to_be64(xive->regs[(PC_VPC_CWATCH_DAT0 >> 3) + i]); 357 } 358 359 return pnv_xive_vst_write(xive, VST_TSEL_VPDT, blk, idx, vpc_watch, 360 XIVE_VST_WORD_ALL); 361 } 362 363 static void pnv_xive_nvt_cache_load(PnvXive *xive) 364 { 365 uint8_t blk = GETFIELD(PC_VPC_CWATCH_BLOCKID, 366 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 367 uint32_t idx = GETFIELD(PC_VPC_CWATCH_OFFSET, 368 xive->regs[(PC_VPC_CWATCH_SPEC >> 3)]); 369 uint64_t vpc_watch[8] = { 0 }; 370 int i; 371 372 if (pnv_xive_vst_read(xive, VST_TSEL_VPDT, blk, idx, vpc_watch)) { 373 xive_error(xive, "VST: no NVT entry %x/%x !?", blk, idx); 374 } 375 376 for (i = 0; i < ARRAY_SIZE(vpc_watch); i++) { 377 xive->regs[(PC_VPC_CWATCH_DAT0 >> 3) + i] = be64_to_cpu(vpc_watch[i]); 378 } 379 } 380 381 static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, 382 XiveEAS *eas) 383 { 384 PnvXive *xive = PNV_XIVE(xrtr); 385 386 /* 387 * EAT lookups should be local to the IC 388 */ 389 if (pnv_xive_block_id(xive) != blk) { 390 xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 391 return -1; 392 } 393 394 return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); 395 } 396 397 /* 398 * One bit per thread id. The first register PC_THREAD_EN_REG0 covers 399 * the first cores 0-15 (normal) of the chip or 0-7 (fused). The 400 * second register covers cores 16-23 (normal) or 8-11 (fused). 401 */ 402 static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu) 403 { 404 int pir = ppc_cpu_pir(cpu); 405 uint32_t fc = PNV9_PIR2FUSEDCORE(pir); 406 uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1; 407 uint32_t bit = pir & 0x3f; 408 409 return xive->regs[reg >> 3] & PPC_BIT(bit); 410 } 411 412 static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, 413 uint8_t nvt_blk, uint32_t nvt_idx, 414 bool cam_ignore, uint8_t priority, 415 uint32_t logic_serv, XiveTCTXMatch *match) 416 { 417 PnvXive *xive = PNV_XIVE(xptr); 418 PnvChip *chip = xive->chip; 419 int count = 0; 420 int i, j; 421 422 for (i = 0; i < chip->nr_cores; i++) { 423 PnvCore *pc = chip->cores[i]; 424 CPUCore *cc = CPU_CORE(pc); 425 426 for (j = 0; j < cc->nr_threads; j++) { 427 PowerPCCPU *cpu = pc->threads[j]; 428 XiveTCTX *tctx; 429 int ring; 430 431 if (!pnv_xive_is_cpu_enabled(xive, cpu)) { 432 continue; 433 } 434 435 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 436 437 /* 438 * Check the thread context CAM lines and record matches. 439 */ 440 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, 441 nvt_idx, cam_ignore, logic_serv); 442 /* 443 * Save the context and follow on to catch duplicates, that we 444 * don't support yet. 445 */ 446 if (ring != -1) { 447 if (match->tctx) { 448 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 449 "thread context NVT %x/%x\n", 450 nvt_blk, nvt_idx); 451 return -1; 452 } 453 454 match->ring = ring; 455 match->tctx = tctx; 456 count++; 457 } 458 } 459 } 460 461 return count; 462 } 463 464 static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) 465 { 466 return pnv_xive_block_id(PNV_XIVE(xrtr)); 467 } 468 469 /* 470 * The TIMA MMIO space is shared among the chips and to identify the 471 * chip from which the access is being done, we extract the chip id 472 * from the PIR. 473 */ 474 static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) 475 { 476 int pir = ppc_cpu_pir(cpu); 477 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; 478 PnvXive *xive = PNV_XIVE(xptr); 479 480 if (!pnv_xive_is_cpu_enabled(xive, cpu)) { 481 xive_error(xive, "IC: CPU %x is not enabled", pir); 482 } 483 return xive; 484 } 485 486 /* 487 * The internal sources (IPIs) of the interrupt controller have no 488 * knowledge of the XIVE chip on which they reside. Encode the block 489 * id in the source interrupt number before forwarding the source 490 * event notification to the Router. This is required on a multichip 491 * system. 492 */ 493 static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno) 494 { 495 PnvXive *xive = PNV_XIVE(xn); 496 uint8_t blk = pnv_xive_block_id(xive); 497 498 xive_router_notify(xn, XIVE_EAS(blk, srcno)); 499 } 500 501 /* 502 * XIVE helpers 503 */ 504 505 static uint64_t pnv_xive_vc_size(PnvXive *xive) 506 { 507 return (~xive->regs[CQ_VC_BARM >> 3] + 1) & CQ_VC_BARM_MASK; 508 } 509 510 static uint64_t pnv_xive_edt_shift(PnvXive *xive) 511 { 512 return ctz64(pnv_xive_vc_size(xive) / XIVE_TABLE_EDT_MAX); 513 } 514 515 static uint64_t pnv_xive_pc_size(PnvXive *xive) 516 { 517 return (~xive->regs[CQ_PC_BARM >> 3] + 1) & CQ_PC_BARM_MASK; 518 } 519 520 static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk) 521 { 522 uint64_t vsd = xive->vsds[VST_TSEL_SBE][blk]; 523 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 524 525 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 526 } 527 528 /* 529 * Compute the number of entries per indirect subpage. 530 */ 531 static uint64_t pnv_xive_vst_per_subpage(PnvXive *xive, uint32_t type) 532 { 533 uint8_t blk = pnv_xive_block_id(xive); 534 uint64_t vsd = xive->vsds[type][blk]; 535 const XiveVstInfo *info = &vst_infos[type]; 536 uint64_t vsd_addr; 537 uint32_t page_shift; 538 539 /* For direct tables, fake a valid value */ 540 if (!(VSD_INDIRECT & vsd)) { 541 return 1; 542 } 543 544 /* Get the page size of the indirect table. */ 545 vsd_addr = vsd & VSD_ADDRESS_MASK; 546 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 547 548 if (!(vsd & VSD_ADDRESS_MASK)) { 549 #ifdef XIVE_DEBUG 550 xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 551 #endif 552 return 0; 553 } 554 555 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 556 557 if (!pnv_xive_vst_page_size_allowed(page_shift)) { 558 xive_error(xive, "VST: invalid %s page shift %d", info->name, 559 page_shift); 560 return 0; 561 } 562 563 return (1ull << page_shift) / info->size; 564 } 565 566 /* 567 * EDT Table 568 * 569 * The Virtualization Controller MMIO region containing the IPI ESB 570 * pages and END ESB pages is sub-divided into "sets" which map 571 * portions of the VC region to the different ESB pages. It is 572 * configured at runtime through the EDT "Domain Table" to let the 573 * firmware decide how to split the VC address space between IPI ESB 574 * pages and END ESB pages. 575 */ 576 577 /* 578 * Computes the overall size of the IPI or the END ESB pages 579 */ 580 static uint64_t pnv_xive_edt_size(PnvXive *xive, uint64_t type) 581 { 582 uint64_t edt_size = 1ull << pnv_xive_edt_shift(xive); 583 uint64_t size = 0; 584 int i; 585 586 for (i = 0; i < XIVE_TABLE_EDT_MAX; i++) { 587 uint64_t edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[i]); 588 589 if (edt_type == type) { 590 size += edt_size; 591 } 592 } 593 594 return size; 595 } 596 597 /* 598 * Maps an offset of the VC region in the IPI or END region using the 599 * layout defined by the EDT "Domaine Table" 600 */ 601 static uint64_t pnv_xive_edt_offset(PnvXive *xive, uint64_t vc_offset, 602 uint64_t type) 603 { 604 int i; 605 uint64_t edt_size = 1ull << pnv_xive_edt_shift(xive); 606 uint64_t edt_offset = vc_offset; 607 608 for (i = 0; i < XIVE_TABLE_EDT_MAX && (i * edt_size) < vc_offset; i++) { 609 uint64_t edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[i]); 610 611 if (edt_type != type) { 612 edt_offset -= edt_size; 613 } 614 } 615 616 return edt_offset; 617 } 618 619 static void pnv_xive_edt_resize(PnvXive *xive) 620 { 621 uint64_t ipi_edt_size = pnv_xive_edt_size(xive, CQ_TDR_EDT_IPI); 622 uint64_t end_edt_size = pnv_xive_edt_size(xive, CQ_TDR_EDT_EQ); 623 624 memory_region_set_size(&xive->ipi_edt_mmio, ipi_edt_size); 625 memory_region_add_subregion(&xive->ipi_mmio, 0, &xive->ipi_edt_mmio); 626 627 memory_region_set_size(&xive->end_edt_mmio, end_edt_size); 628 memory_region_add_subregion(&xive->end_mmio, 0, &xive->end_edt_mmio); 629 } 630 631 /* 632 * XIVE Table configuration. Only EDT is supported. 633 */ 634 static int pnv_xive_table_set_data(PnvXive *xive, uint64_t val) 635 { 636 uint64_t tsel = xive->regs[CQ_TAR >> 3] & CQ_TAR_TSEL; 637 uint8_t tsel_index = GETFIELD(CQ_TAR_TSEL_INDEX, xive->regs[CQ_TAR >> 3]); 638 uint64_t *xive_table; 639 uint8_t max_index; 640 641 switch (tsel) { 642 case CQ_TAR_TSEL_BLK: 643 max_index = ARRAY_SIZE(xive->blk); 644 xive_table = xive->blk; 645 break; 646 case CQ_TAR_TSEL_MIG: 647 max_index = ARRAY_SIZE(xive->mig); 648 xive_table = xive->mig; 649 break; 650 case CQ_TAR_TSEL_EDT: 651 max_index = ARRAY_SIZE(xive->edt); 652 xive_table = xive->edt; 653 break; 654 case CQ_TAR_TSEL_VDT: 655 max_index = ARRAY_SIZE(xive->vdt); 656 xive_table = xive->vdt; 657 break; 658 default: 659 xive_error(xive, "IC: invalid table %d", (int) tsel); 660 return -1; 661 } 662 663 if (tsel_index >= max_index) { 664 xive_error(xive, "IC: invalid index %d", (int) tsel_index); 665 return -1; 666 } 667 668 xive_table[tsel_index] = val; 669 670 if (xive->regs[CQ_TAR >> 3] & CQ_TAR_TBL_AUTOINC) { 671 xive->regs[CQ_TAR >> 3] = 672 SETFIELD(CQ_TAR_TSEL_INDEX, xive->regs[CQ_TAR >> 3], ++tsel_index); 673 } 674 675 /* 676 * EDT configuration is complete. Resize the MMIO windows exposing 677 * the IPI and the END ESBs in the VC region. 678 */ 679 if (tsel == CQ_TAR_TSEL_EDT && tsel_index == ARRAY_SIZE(xive->edt)) { 680 pnv_xive_edt_resize(xive); 681 } 682 683 return 0; 684 } 685 686 /* 687 * Virtual Structure Tables (VST) configuration 688 */ 689 static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type, 690 uint8_t blk, uint64_t vsd) 691 { 692 XiveENDSource *end_xsrc = &xive->end_source; 693 XiveSource *xsrc = &xive->ipi_source; 694 const XiveVstInfo *info = &vst_infos[type]; 695 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 696 uint64_t vst_tsize = 1ull << page_shift; 697 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 698 699 /* Basic checks */ 700 701 if (VSD_INDIRECT & vsd) { 702 if (!(xive->regs[VC_GLOBAL_CONFIG >> 3] & VC_GCONF_INDIRECT)) { 703 xive_error(xive, "VST: %s indirect tables are not enabled", 704 info->name); 705 return; 706 } 707 708 if (!pnv_xive_vst_page_size_allowed(page_shift)) { 709 xive_error(xive, "VST: invalid %s page shift %d", info->name, 710 page_shift); 711 return; 712 } 713 } 714 715 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 716 xive_error(xive, "VST: %s table address 0x%"PRIx64" is not aligned with" 717 " page shift %d", info->name, vst_addr, page_shift); 718 return; 719 } 720 721 /* Record the table configuration (in SRAM on HW) */ 722 xive->vsds[type][blk] = vsd; 723 724 /* Now tune the models with the configuration provided by the FW */ 725 726 switch (type) { 727 case VST_TSEL_IVT: /* Nothing to be done */ 728 break; 729 730 case VST_TSEL_EQDT: 731 /* 732 * Backing store pages for the END. 733 * 734 * If the table is direct, we can compute the number of PQ 735 * entries provisioned by FW (such as skiboot) and resize the 736 * END ESB window accordingly. 737 */ 738 if (!(VSD_INDIRECT & vsd)) { 739 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 740 * (1ull << xsrc->esb_shift)); 741 } 742 memory_region_add_subregion(&xive->end_edt_mmio, 0, 743 &end_xsrc->esb_mmio); 744 break; 745 746 case VST_TSEL_SBE: 747 /* 748 * Backing store pages for the source PQ bits. The model does 749 * not use these PQ bits backed in RAM because the XiveSource 750 * model has its own. 751 * 752 * If the table is direct, we can compute the number of PQ 753 * entries provisioned by FW (such as skiboot) and resize the 754 * ESB window accordingly. 755 */ 756 if (!(VSD_INDIRECT & vsd)) { 757 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 758 * (1ull << xsrc->esb_shift)); 759 } 760 memory_region_add_subregion(&xive->ipi_edt_mmio, 0, &xsrc->esb_mmio); 761 break; 762 763 case VST_TSEL_VPDT: /* Not modeled */ 764 case VST_TSEL_IRQ: /* Not modeled */ 765 /* 766 * These tables contains the backing store pages for the 767 * interrupt fifos of the VC sub-engine in case of overflow. 768 */ 769 break; 770 771 default: 772 g_assert_not_reached(); 773 } 774 } 775 776 /* 777 * Both PC and VC sub-engines are configured as each use the Virtual 778 * Structure Tables : SBE, EAS, END and NVT. 779 */ 780 static void pnv_xive_vst_set_data(PnvXive *xive, uint64_t vsd, bool pc_engine) 781 { 782 uint8_t mode = GETFIELD(VSD_MODE, vsd); 783 uint8_t type = GETFIELD(VST_TABLE_SELECT, 784 xive->regs[VC_VSD_TABLE_ADDR >> 3]); 785 uint8_t blk = GETFIELD(VST_TABLE_BLOCK, 786 xive->regs[VC_VSD_TABLE_ADDR >> 3]); 787 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 788 789 if (type > VST_TSEL_IRQ) { 790 xive_error(xive, "VST: invalid table type %d", type); 791 return; 792 } 793 794 if (blk >= vst_infos[type].max_blocks) { 795 xive_error(xive, "VST: invalid block id %d for" 796 " %s table", blk, vst_infos[type].name); 797 return; 798 } 799 800 /* 801 * Only take the VC sub-engine configuration into account because 802 * the XiveRouter model combines both VC and PC sub-engines 803 */ 804 if (pc_engine) { 805 return; 806 } 807 808 if (!vst_addr) { 809 xive_error(xive, "VST: invalid %s table address", vst_infos[type].name); 810 return; 811 } 812 813 switch (mode) { 814 case VSD_MODE_FORWARD: 815 xive->vsds[type][blk] = vsd; 816 break; 817 818 case VSD_MODE_EXCLUSIVE: 819 pnv_xive_vst_set_exclusive(xive, type, blk, vsd); 820 break; 821 822 default: 823 xive_error(xive, "VST: unsupported table mode %d", mode); 824 return; 825 } 826 } 827 828 /* 829 * Interrupt controller MMIO region. The layout is compatible between 830 * 4K and 64K pages : 831 * 832 * Page 0 sub-engine BARs 833 * 0x000 - 0x3FF IC registers 834 * 0x400 - 0x7FF PC registers 835 * 0x800 - 0xFFF VC registers 836 * 837 * Page 1 Notify page (writes only) 838 * 0x000 - 0x7FF HW interrupt triggers (PSI, PHB) 839 * 0x800 - 0xFFF forwards and syncs 840 * 841 * Page 2 LSI Trigger page (writes only) (not modeled) 842 * Page 3 LSI SB EOI page (reads only) (not modeled) 843 * 844 * Page 4-7 indirect TIMA 845 */ 846 847 /* 848 * IC - registers MMIO 849 */ 850 static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset, 851 uint64_t val, unsigned size) 852 { 853 PnvXive *xive = PNV_XIVE(opaque); 854 MemoryRegion *sysmem = get_system_memory(); 855 uint32_t reg = offset >> 3; 856 bool is_chip0 = xive->chip->chip_id == 0; 857 858 switch (offset) { 859 860 /* 861 * XIVE CQ (PowerBus bridge) settings 862 */ 863 case CQ_MSGSND: /* msgsnd for doorbells */ 864 case CQ_FIRMASK_OR: /* FIR error reporting */ 865 break; 866 case CQ_PBI_CTL: 867 if (val & CQ_PBI_PC_64K) { 868 xive->pc_shift = 16; 869 } 870 if (val & CQ_PBI_VC_64K) { 871 xive->vc_shift = 16; 872 } 873 break; 874 case CQ_CFG_PB_GEN: /* PowerBus General Configuration */ 875 /* 876 * TODO: CQ_INT_ADDR_OPT for 1-block-per-chip mode 877 */ 878 break; 879 880 /* 881 * XIVE Virtualization Controller settings 882 */ 883 case VC_GLOBAL_CONFIG: 884 break; 885 886 /* 887 * XIVE Presenter Controller settings 888 */ 889 case PC_GLOBAL_CONFIG: 890 /* 891 * PC_GCONF_CHIPID_OVR 892 * Overrides Int command Chip ID with the Chip ID field (DEBUG) 893 */ 894 break; 895 case PC_TCTXT_CFG: 896 /* 897 * TODO: block group support 898 */ 899 break; 900 case PC_TCTXT_TRACK: 901 /* 902 * PC_TCTXT_TRACK_EN: 903 * enable block tracking and exchange of block ownership 904 * information between Interrupt controllers 905 */ 906 break; 907 908 /* 909 * Misc settings 910 */ 911 case VC_SBC_CONFIG: /* Store EOI configuration */ 912 /* 913 * Configure store EOI if required by firwmare (skiboot has removed 914 * support recently though) 915 */ 916 if (val & (VC_SBC_CONF_CPLX_CIST | VC_SBC_CONF_CIST_BOTH)) { 917 xive->ipi_source.esb_flags |= XIVE_SRC_STORE_EOI; 918 } 919 break; 920 921 case VC_EQC_CONFIG: /* TODO: silent escalation */ 922 case VC_AIB_TX_ORDER_TAG2: /* relax ordering */ 923 break; 924 925 /* 926 * XIVE BAR settings (XSCOM only) 927 */ 928 case CQ_RST_CTL: 929 /* bit4: resets all BAR registers */ 930 break; 931 932 case CQ_IC_BAR: /* IC BAR. 8 pages */ 933 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 934 if (!(val & CQ_IC_BAR_VALID)) { 935 xive->ic_base = 0; 936 if (xive->regs[reg] & CQ_IC_BAR_VALID) { 937 memory_region_del_subregion(&xive->ic_mmio, 938 &xive->ic_reg_mmio); 939 memory_region_del_subregion(&xive->ic_mmio, 940 &xive->ic_notify_mmio); 941 memory_region_del_subregion(&xive->ic_mmio, 942 &xive->ic_lsi_mmio); 943 memory_region_del_subregion(&xive->ic_mmio, 944 &xive->tm_indirect_mmio); 945 946 memory_region_del_subregion(sysmem, &xive->ic_mmio); 947 } 948 } else { 949 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 950 if (!(xive->regs[reg] & CQ_IC_BAR_VALID)) { 951 memory_region_add_subregion(sysmem, xive->ic_base, 952 &xive->ic_mmio); 953 954 memory_region_add_subregion(&xive->ic_mmio, 0, 955 &xive->ic_reg_mmio); 956 memory_region_add_subregion(&xive->ic_mmio, 957 1ul << xive->ic_shift, 958 &xive->ic_notify_mmio); 959 memory_region_add_subregion(&xive->ic_mmio, 960 2ul << xive->ic_shift, 961 &xive->ic_lsi_mmio); 962 memory_region_add_subregion(&xive->ic_mmio, 963 4ull << xive->ic_shift, 964 &xive->tm_indirect_mmio); 965 } 966 } 967 break; 968 969 case CQ_TM1_BAR: /* TM BAR. 4 pages. Map only once */ 970 case CQ_TM2_BAR: /* second TM BAR. for hotplug. Not modeled */ 971 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 972 if (!(val & CQ_TM_BAR_VALID)) { 973 xive->tm_base = 0; 974 if (xive->regs[reg] & CQ_TM_BAR_VALID && is_chip0) { 975 memory_region_del_subregion(sysmem, &xive->tm_mmio); 976 } 977 } else { 978 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 979 if (!(xive->regs[reg] & CQ_TM_BAR_VALID) && is_chip0) { 980 memory_region_add_subregion(sysmem, xive->tm_base, 981 &xive->tm_mmio); 982 } 983 } 984 break; 985 986 case CQ_PC_BARM: 987 xive->regs[reg] = val; 988 memory_region_set_size(&xive->pc_mmio, pnv_xive_pc_size(xive)); 989 break; 990 case CQ_PC_BAR: /* From 32M to 512G */ 991 if (!(val & CQ_PC_BAR_VALID)) { 992 xive->pc_base = 0; 993 if (xive->regs[reg] & CQ_PC_BAR_VALID) { 994 memory_region_del_subregion(sysmem, &xive->pc_mmio); 995 } 996 } else { 997 xive->pc_base = val & ~(CQ_PC_BAR_VALID); 998 if (!(xive->regs[reg] & CQ_PC_BAR_VALID)) { 999 memory_region_add_subregion(sysmem, xive->pc_base, 1000 &xive->pc_mmio); 1001 } 1002 } 1003 break; 1004 1005 case CQ_VC_BARM: 1006 xive->regs[reg] = val; 1007 memory_region_set_size(&xive->vc_mmio, pnv_xive_vc_size(xive)); 1008 break; 1009 case CQ_VC_BAR: /* From 64M to 4TB */ 1010 if (!(val & CQ_VC_BAR_VALID)) { 1011 xive->vc_base = 0; 1012 if (xive->regs[reg] & CQ_VC_BAR_VALID) { 1013 memory_region_del_subregion(sysmem, &xive->vc_mmio); 1014 } 1015 } else { 1016 xive->vc_base = val & ~(CQ_VC_BAR_VALID); 1017 if (!(xive->regs[reg] & CQ_VC_BAR_VALID)) { 1018 memory_region_add_subregion(sysmem, xive->vc_base, 1019 &xive->vc_mmio); 1020 } 1021 } 1022 break; 1023 1024 /* 1025 * XIVE Table settings. 1026 */ 1027 case CQ_TAR: /* Table Address */ 1028 break; 1029 case CQ_TDR: /* Table Data */ 1030 pnv_xive_table_set_data(xive, val); 1031 break; 1032 1033 /* 1034 * XIVE VC & PC Virtual Structure Table settings 1035 */ 1036 case VC_VSD_TABLE_ADDR: 1037 case PC_VSD_TABLE_ADDR: /* Virtual table selector */ 1038 break; 1039 case VC_VSD_TABLE_DATA: /* Virtual table setting */ 1040 case PC_VSD_TABLE_DATA: 1041 pnv_xive_vst_set_data(xive, val, offset == PC_VSD_TABLE_DATA); 1042 break; 1043 1044 /* 1045 * Interrupt fifo overflow in memory backing store (Not modeled) 1046 */ 1047 case VC_IRQ_CONFIG_IPI: 1048 case VC_IRQ_CONFIG_HW: 1049 case VC_IRQ_CONFIG_CASCADE1: 1050 case VC_IRQ_CONFIG_CASCADE2: 1051 case VC_IRQ_CONFIG_REDIST: 1052 case VC_IRQ_CONFIG_IPI_CASC: 1053 break; 1054 1055 /* 1056 * XIVE hardware thread enablement 1057 */ 1058 case PC_THREAD_EN_REG0: /* Physical Thread Enable */ 1059 case PC_THREAD_EN_REG1: /* Physical Thread Enable (fused core) */ 1060 break; 1061 1062 case PC_THREAD_EN_REG0_SET: 1063 xive->regs[PC_THREAD_EN_REG0 >> 3] |= val; 1064 break; 1065 case PC_THREAD_EN_REG1_SET: 1066 xive->regs[PC_THREAD_EN_REG1 >> 3] |= val; 1067 break; 1068 case PC_THREAD_EN_REG0_CLR: 1069 xive->regs[PC_THREAD_EN_REG0 >> 3] &= ~val; 1070 break; 1071 case PC_THREAD_EN_REG1_CLR: 1072 xive->regs[PC_THREAD_EN_REG1 >> 3] &= ~val; 1073 break; 1074 1075 /* 1076 * Indirect TIMA access set up. Defines the PIR of the HW thread 1077 * to use. 1078 */ 1079 case PC_TCTXT_INDIR0 ... PC_TCTXT_INDIR3: 1080 break; 1081 1082 /* 1083 * XIVE PC & VC cache updates for EAS, NVT and END 1084 */ 1085 case VC_IVC_SCRUB_MASK: 1086 case VC_IVC_SCRUB_TRIG: 1087 break; 1088 1089 case VC_EQC_CWATCH_SPEC: 1090 val &= ~VC_EQC_CWATCH_CONFLICT; /* HW resets this bit */ 1091 break; 1092 case VC_EQC_CWATCH_DAT1 ... VC_EQC_CWATCH_DAT3: 1093 break; 1094 case VC_EQC_CWATCH_DAT0: 1095 /* writing to DATA0 triggers the cache write */ 1096 xive->regs[reg] = val; 1097 pnv_xive_end_update(xive); 1098 break; 1099 case VC_EQC_SCRUB_MASK: 1100 case VC_EQC_SCRUB_TRIG: 1101 /* 1102 * The scrubbing registers flush the cache in RAM and can also 1103 * invalidate. 1104 */ 1105 break; 1106 1107 case PC_VPC_CWATCH_SPEC: 1108 val &= ~PC_VPC_CWATCH_CONFLICT; /* HW resets this bit */ 1109 break; 1110 case PC_VPC_CWATCH_DAT1 ... PC_VPC_CWATCH_DAT7: 1111 break; 1112 case PC_VPC_CWATCH_DAT0: 1113 /* writing to DATA0 triggers the cache write */ 1114 xive->regs[reg] = val; 1115 pnv_xive_nvt_update(xive); 1116 break; 1117 case PC_VPC_SCRUB_MASK: 1118 case PC_VPC_SCRUB_TRIG: 1119 /* 1120 * The scrubbing registers flush the cache in RAM and can also 1121 * invalidate. 1122 */ 1123 break; 1124 1125 1126 /* 1127 * XIVE PC & VC cache invalidation 1128 */ 1129 case PC_AT_KILL: 1130 break; 1131 case VC_AT_MACRO_KILL: 1132 break; 1133 case PC_AT_KILL_MASK: 1134 case VC_AT_MACRO_KILL_MASK: 1135 break; 1136 1137 default: 1138 xive_error(xive, "IC: invalid write to reg=0x%"HWADDR_PRIx, offset); 1139 return; 1140 } 1141 1142 xive->regs[reg] = val; 1143 } 1144 1145 static uint64_t pnv_xive_ic_reg_read(void *opaque, hwaddr offset, unsigned size) 1146 { 1147 PnvXive *xive = PNV_XIVE(opaque); 1148 uint64_t val = 0; 1149 uint32_t reg = offset >> 3; 1150 1151 switch (offset) { 1152 case CQ_CFG_PB_GEN: 1153 case CQ_IC_BAR: 1154 case CQ_TM1_BAR: 1155 case CQ_TM2_BAR: 1156 case CQ_PC_BAR: 1157 case CQ_PC_BARM: 1158 case CQ_VC_BAR: 1159 case CQ_VC_BARM: 1160 case CQ_TAR: 1161 case CQ_TDR: 1162 case CQ_PBI_CTL: 1163 1164 case PC_TCTXT_CFG: 1165 case PC_TCTXT_TRACK: 1166 case PC_TCTXT_INDIR0: 1167 case PC_TCTXT_INDIR1: 1168 case PC_TCTXT_INDIR2: 1169 case PC_TCTXT_INDIR3: 1170 case PC_GLOBAL_CONFIG: 1171 1172 case PC_VPC_SCRUB_MASK: 1173 1174 case VC_GLOBAL_CONFIG: 1175 case VC_AIB_TX_ORDER_TAG2: 1176 1177 case VC_IRQ_CONFIG_IPI: 1178 case VC_IRQ_CONFIG_HW: 1179 case VC_IRQ_CONFIG_CASCADE1: 1180 case VC_IRQ_CONFIG_CASCADE2: 1181 case VC_IRQ_CONFIG_REDIST: 1182 case VC_IRQ_CONFIG_IPI_CASC: 1183 1184 case VC_EQC_SCRUB_MASK: 1185 case VC_IVC_SCRUB_MASK: 1186 case VC_SBC_CONFIG: 1187 case VC_AT_MACRO_KILL_MASK: 1188 case VC_VSD_TABLE_ADDR: 1189 case PC_VSD_TABLE_ADDR: 1190 case VC_VSD_TABLE_DATA: 1191 case PC_VSD_TABLE_DATA: 1192 case PC_THREAD_EN_REG0: 1193 case PC_THREAD_EN_REG1: 1194 val = xive->regs[reg]; 1195 break; 1196 1197 /* 1198 * XIVE hardware thread enablement 1199 */ 1200 case PC_THREAD_EN_REG0_SET: 1201 case PC_THREAD_EN_REG0_CLR: 1202 val = xive->regs[PC_THREAD_EN_REG0 >> 3]; 1203 break; 1204 case PC_THREAD_EN_REG1_SET: 1205 case PC_THREAD_EN_REG1_CLR: 1206 val = xive->regs[PC_THREAD_EN_REG1 >> 3]; 1207 break; 1208 1209 case CQ_MSGSND: /* Identifies which cores have msgsnd enabled. */ 1210 val = 0xffffff0000000000; 1211 break; 1212 1213 /* 1214 * XIVE PC & VC cache updates for EAS, NVT and END 1215 */ 1216 case VC_EQC_CWATCH_SPEC: 1217 xive->regs[reg] = ~(VC_EQC_CWATCH_FULL | VC_EQC_CWATCH_CONFLICT); 1218 val = xive->regs[reg]; 1219 break; 1220 case VC_EQC_CWATCH_DAT0: 1221 /* 1222 * Load DATA registers from cache with data requested by the 1223 * SPEC register 1224 */ 1225 pnv_xive_end_cache_load(xive); 1226 val = xive->regs[reg]; 1227 break; 1228 case VC_EQC_CWATCH_DAT1 ... VC_EQC_CWATCH_DAT3: 1229 val = xive->regs[reg]; 1230 break; 1231 1232 case PC_VPC_CWATCH_SPEC: 1233 xive->regs[reg] = ~(PC_VPC_CWATCH_FULL | PC_VPC_CWATCH_CONFLICT); 1234 val = xive->regs[reg]; 1235 break; 1236 case PC_VPC_CWATCH_DAT0: 1237 /* 1238 * Load DATA registers from cache with data requested by the 1239 * SPEC register 1240 */ 1241 pnv_xive_nvt_cache_load(xive); 1242 val = xive->regs[reg]; 1243 break; 1244 case PC_VPC_CWATCH_DAT1 ... PC_VPC_CWATCH_DAT7: 1245 val = xive->regs[reg]; 1246 break; 1247 1248 case PC_VPC_SCRUB_TRIG: 1249 case VC_IVC_SCRUB_TRIG: 1250 case VC_EQC_SCRUB_TRIG: 1251 xive->regs[reg] &= ~VC_SCRUB_VALID; 1252 val = xive->regs[reg]; 1253 break; 1254 1255 /* 1256 * XIVE PC & VC cache invalidation 1257 */ 1258 case PC_AT_KILL: 1259 xive->regs[reg] &= ~PC_AT_KILL_VALID; 1260 val = xive->regs[reg]; 1261 break; 1262 case VC_AT_MACRO_KILL: 1263 xive->regs[reg] &= ~VC_KILL_VALID; 1264 val = xive->regs[reg]; 1265 break; 1266 1267 /* 1268 * XIVE synchronisation 1269 */ 1270 case VC_EQC_CONFIG: 1271 val = VC_EQC_SYNC_MASK; 1272 break; 1273 1274 default: 1275 xive_error(xive, "IC: invalid read reg=0x%"HWADDR_PRIx, offset); 1276 } 1277 1278 return val; 1279 } 1280 1281 static const MemoryRegionOps pnv_xive_ic_reg_ops = { 1282 .read = pnv_xive_ic_reg_read, 1283 .write = pnv_xive_ic_reg_write, 1284 .endianness = DEVICE_BIG_ENDIAN, 1285 .valid = { 1286 .min_access_size = 8, 1287 .max_access_size = 8, 1288 }, 1289 .impl = { 1290 .min_access_size = 8, 1291 .max_access_size = 8, 1292 }, 1293 }; 1294 1295 /* 1296 * IC - Notify MMIO port page (write only) 1297 */ 1298 #define PNV_XIVE_FORWARD_IPI 0x800 /* Forward IPI */ 1299 #define PNV_XIVE_FORWARD_HW 0x880 /* Forward HW */ 1300 #define PNV_XIVE_FORWARD_OS_ESC 0x900 /* Forward OS escalation */ 1301 #define PNV_XIVE_FORWARD_HW_ESC 0x980 /* Forward Hyp escalation */ 1302 #define PNV_XIVE_FORWARD_REDIS 0xa00 /* Forward Redistribution */ 1303 #define PNV_XIVE_RESERVED5 0xa80 /* Cache line 5 PowerBUS operation */ 1304 #define PNV_XIVE_RESERVED6 0xb00 /* Cache line 6 PowerBUS operation */ 1305 #define PNV_XIVE_RESERVED7 0xb80 /* Cache line 7 PowerBUS operation */ 1306 1307 /* VC synchronisation */ 1308 #define PNV_XIVE_SYNC_IPI 0xc00 /* Sync IPI */ 1309 #define PNV_XIVE_SYNC_HW 0xc80 /* Sync HW */ 1310 #define PNV_XIVE_SYNC_OS_ESC 0xd00 /* Sync OS escalation */ 1311 #define PNV_XIVE_SYNC_HW_ESC 0xd80 /* Sync Hyp escalation */ 1312 #define PNV_XIVE_SYNC_REDIS 0xe00 /* Sync Redistribution */ 1313 1314 /* PC synchronisation */ 1315 #define PNV_XIVE_SYNC_PULL 0xe80 /* Sync pull context */ 1316 #define PNV_XIVE_SYNC_PUSH 0xf00 /* Sync push context */ 1317 #define PNV_XIVE_SYNC_VPC 0xf80 /* Sync remove VPC store */ 1318 1319 static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr addr, uint64_t val) 1320 { 1321 uint8_t blk; 1322 uint32_t idx; 1323 1324 trace_pnv_xive_ic_hw_trigger(addr, val); 1325 1326 if (val & XIVE_TRIGGER_END) { 1327 xive_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1328 addr, val); 1329 return; 1330 } 1331 1332 /* 1333 * Forward the source event notification directly to the Router. 1334 * The source interrupt number should already be correctly encoded 1335 * with the chip block id by the sending device (PHB, PSI). 1336 */ 1337 blk = XIVE_EAS_BLOCK(val); 1338 idx = XIVE_EAS_INDEX(val); 1339 1340 xive_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx)); 1341 } 1342 1343 static void pnv_xive_ic_notify_write(void *opaque, hwaddr addr, uint64_t val, 1344 unsigned size) 1345 { 1346 PnvXive *xive = PNV_XIVE(opaque); 1347 1348 /* VC: HW triggers */ 1349 switch (addr) { 1350 case 0x000 ... 0x7FF: 1351 pnv_xive_ic_hw_trigger(opaque, addr, val); 1352 break; 1353 1354 /* VC: Forwarded IRQs */ 1355 case PNV_XIVE_FORWARD_IPI: 1356 case PNV_XIVE_FORWARD_HW: 1357 case PNV_XIVE_FORWARD_OS_ESC: 1358 case PNV_XIVE_FORWARD_HW_ESC: 1359 case PNV_XIVE_FORWARD_REDIS: 1360 /* TODO: forwarded IRQs. Should be like HW triggers */ 1361 xive_error(xive, "IC: forwarded at @0x%"HWADDR_PRIx" IRQ 0x%"PRIx64, 1362 addr, val); 1363 break; 1364 1365 /* VC syncs */ 1366 case PNV_XIVE_SYNC_IPI: 1367 case PNV_XIVE_SYNC_HW: 1368 case PNV_XIVE_SYNC_OS_ESC: 1369 case PNV_XIVE_SYNC_HW_ESC: 1370 case PNV_XIVE_SYNC_REDIS: 1371 break; 1372 1373 /* PC syncs */ 1374 case PNV_XIVE_SYNC_PULL: 1375 case PNV_XIVE_SYNC_PUSH: 1376 case PNV_XIVE_SYNC_VPC: 1377 break; 1378 1379 default: 1380 xive_error(xive, "IC: invalid notify write @%"HWADDR_PRIx, addr); 1381 } 1382 } 1383 1384 static uint64_t pnv_xive_ic_notify_read(void *opaque, hwaddr addr, 1385 unsigned size) 1386 { 1387 PnvXive *xive = PNV_XIVE(opaque); 1388 1389 /* loads are invalid */ 1390 xive_error(xive, "IC: invalid notify read @%"HWADDR_PRIx, addr); 1391 return -1; 1392 } 1393 1394 static const MemoryRegionOps pnv_xive_ic_notify_ops = { 1395 .read = pnv_xive_ic_notify_read, 1396 .write = pnv_xive_ic_notify_write, 1397 .endianness = DEVICE_BIG_ENDIAN, 1398 .valid = { 1399 .min_access_size = 8, 1400 .max_access_size = 8, 1401 }, 1402 .impl = { 1403 .min_access_size = 8, 1404 .max_access_size = 8, 1405 }, 1406 }; 1407 1408 /* 1409 * IC - LSI MMIO handlers (not modeled) 1410 */ 1411 1412 static void pnv_xive_ic_lsi_write(void *opaque, hwaddr addr, 1413 uint64_t val, unsigned size) 1414 { 1415 PnvXive *xive = PNV_XIVE(opaque); 1416 1417 xive_error(xive, "IC: LSI invalid write @%"HWADDR_PRIx, addr); 1418 } 1419 1420 static uint64_t pnv_xive_ic_lsi_read(void *opaque, hwaddr addr, unsigned size) 1421 { 1422 PnvXive *xive = PNV_XIVE(opaque); 1423 1424 xive_error(xive, "IC: LSI invalid read @%"HWADDR_PRIx, addr); 1425 return -1; 1426 } 1427 1428 static const MemoryRegionOps pnv_xive_ic_lsi_ops = { 1429 .read = pnv_xive_ic_lsi_read, 1430 .write = pnv_xive_ic_lsi_write, 1431 .endianness = DEVICE_BIG_ENDIAN, 1432 .valid = { 1433 .min_access_size = 8, 1434 .max_access_size = 8, 1435 }, 1436 .impl = { 1437 .min_access_size = 8, 1438 .max_access_size = 8, 1439 }, 1440 }; 1441 1442 /* 1443 * IC - Indirect TIMA MMIO handlers 1444 */ 1445 1446 /* 1447 * When the TIMA is accessed from the indirect page, the thread id of 1448 * the target CPU is configured in the PC_TCTXT_INDIR0 register before 1449 * use. This is used for resets and for debug purpose also. 1450 */ 1451 static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive) 1452 { 1453 PnvChip *chip = xive->chip; 1454 uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3]; 1455 PowerPCCPU *cpu = NULL; 1456 int pir; 1457 1458 if (!(tctxt_indir & PC_TCTXT_INDIR_VALID)) { 1459 xive_error(xive, "IC: no indirect TIMA access in progress"); 1460 return NULL; 1461 } 1462 1463 pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir); 1464 cpu = pnv_chip_find_cpu(chip, pir); 1465 if (!cpu) { 1466 xive_error(xive, "IC: invalid PIR %x for indirect access", pir); 1467 return NULL; 1468 } 1469 1470 /* Check that HW thread is XIVE enabled */ 1471 if (!pnv_xive_is_cpu_enabled(xive, cpu)) { 1472 xive_error(xive, "IC: CPU %x is not enabled", pir); 1473 } 1474 1475 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1476 } 1477 1478 static void xive_tm_indirect_write(void *opaque, hwaddr offset, 1479 uint64_t value, unsigned size) 1480 { 1481 XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); 1482 1483 xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); 1484 } 1485 1486 static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset, 1487 unsigned size) 1488 { 1489 XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); 1490 1491 return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); 1492 } 1493 1494 static const MemoryRegionOps xive_tm_indirect_ops = { 1495 .read = xive_tm_indirect_read, 1496 .write = xive_tm_indirect_write, 1497 .endianness = DEVICE_BIG_ENDIAN, 1498 .valid = { 1499 .min_access_size = 1, 1500 .max_access_size = 8, 1501 }, 1502 .impl = { 1503 .min_access_size = 1, 1504 .max_access_size = 8, 1505 }, 1506 }; 1507 1508 static void pnv_xive_tm_write(void *opaque, hwaddr offset, 1509 uint64_t value, unsigned size) 1510 { 1511 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1512 PnvXive *xive = pnv_xive_tm_get_xive(cpu); 1513 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1514 1515 xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size); 1516 } 1517 1518 static uint64_t pnv_xive_tm_read(void *opaque, hwaddr offset, unsigned size) 1519 { 1520 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1521 PnvXive *xive = pnv_xive_tm_get_xive(cpu); 1522 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1523 1524 return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size); 1525 } 1526 1527 const MemoryRegionOps pnv_xive_tm_ops = { 1528 .read = pnv_xive_tm_read, 1529 .write = pnv_xive_tm_write, 1530 .endianness = DEVICE_BIG_ENDIAN, 1531 .valid = { 1532 .min_access_size = 1, 1533 .max_access_size = 8, 1534 }, 1535 .impl = { 1536 .min_access_size = 1, 1537 .max_access_size = 8, 1538 }, 1539 }; 1540 1541 /* 1542 * Interrupt controller XSCOM region. 1543 */ 1544 static uint64_t pnv_xive_xscom_read(void *opaque, hwaddr addr, unsigned size) 1545 { 1546 switch (addr >> 3) { 1547 case X_VC_EQC_CONFIG: 1548 /* FIXME (skiboot): This is the only XSCOM load. Bizarre. */ 1549 return VC_EQC_SYNC_MASK; 1550 default: 1551 return pnv_xive_ic_reg_read(opaque, addr, size); 1552 } 1553 } 1554 1555 static void pnv_xive_xscom_write(void *opaque, hwaddr addr, 1556 uint64_t val, unsigned size) 1557 { 1558 pnv_xive_ic_reg_write(opaque, addr, val, size); 1559 } 1560 1561 static const MemoryRegionOps pnv_xive_xscom_ops = { 1562 .read = pnv_xive_xscom_read, 1563 .write = pnv_xive_xscom_write, 1564 .endianness = DEVICE_BIG_ENDIAN, 1565 .valid = { 1566 .min_access_size = 8, 1567 .max_access_size = 8, 1568 }, 1569 .impl = { 1570 .min_access_size = 8, 1571 .max_access_size = 8, 1572 } 1573 }; 1574 1575 /* 1576 * Virtualization Controller MMIO region containing the IPI and END ESB pages 1577 */ 1578 static uint64_t pnv_xive_vc_read(void *opaque, hwaddr offset, 1579 unsigned size) 1580 { 1581 PnvXive *xive = PNV_XIVE(opaque); 1582 uint64_t edt_index = offset >> pnv_xive_edt_shift(xive); 1583 uint64_t edt_type = 0; 1584 uint64_t edt_offset; 1585 MemTxResult result; 1586 AddressSpace *edt_as = NULL; 1587 uint64_t ret = -1; 1588 1589 if (edt_index < XIVE_TABLE_EDT_MAX) { 1590 edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[edt_index]); 1591 } 1592 1593 switch (edt_type) { 1594 case CQ_TDR_EDT_IPI: 1595 edt_as = &xive->ipi_as; 1596 break; 1597 case CQ_TDR_EDT_EQ: 1598 edt_as = &xive->end_as; 1599 break; 1600 default: 1601 xive_error(xive, "VC: invalid EDT type for read @%"HWADDR_PRIx, offset); 1602 return -1; 1603 } 1604 1605 /* Remap the offset for the targeted address space */ 1606 edt_offset = pnv_xive_edt_offset(xive, offset, edt_type); 1607 1608 ret = address_space_ldq(edt_as, edt_offset, MEMTXATTRS_UNSPECIFIED, 1609 &result); 1610 1611 if (result != MEMTX_OK) { 1612 xive_error(xive, "VC: %s read failed at @0x%"HWADDR_PRIx " -> @0x%" 1613 HWADDR_PRIx, edt_type == CQ_TDR_EDT_IPI ? "IPI" : "END", 1614 offset, edt_offset); 1615 return -1; 1616 } 1617 1618 return ret; 1619 } 1620 1621 static void pnv_xive_vc_write(void *opaque, hwaddr offset, 1622 uint64_t val, unsigned size) 1623 { 1624 PnvXive *xive = PNV_XIVE(opaque); 1625 uint64_t edt_index = offset >> pnv_xive_edt_shift(xive); 1626 uint64_t edt_type = 0; 1627 uint64_t edt_offset; 1628 MemTxResult result; 1629 AddressSpace *edt_as = NULL; 1630 1631 if (edt_index < XIVE_TABLE_EDT_MAX) { 1632 edt_type = GETFIELD(CQ_TDR_EDT_TYPE, xive->edt[edt_index]); 1633 } 1634 1635 switch (edt_type) { 1636 case CQ_TDR_EDT_IPI: 1637 edt_as = &xive->ipi_as; 1638 break; 1639 case CQ_TDR_EDT_EQ: 1640 edt_as = &xive->end_as; 1641 break; 1642 default: 1643 xive_error(xive, "VC: invalid EDT type for write @%"HWADDR_PRIx, 1644 offset); 1645 return; 1646 } 1647 1648 /* Remap the offset for the targeted address space */ 1649 edt_offset = pnv_xive_edt_offset(xive, offset, edt_type); 1650 1651 address_space_stq(edt_as, edt_offset, val, MEMTXATTRS_UNSPECIFIED, &result); 1652 if (result != MEMTX_OK) { 1653 xive_error(xive, "VC: write failed at @0x%"HWADDR_PRIx, edt_offset); 1654 } 1655 } 1656 1657 static const MemoryRegionOps pnv_xive_vc_ops = { 1658 .read = pnv_xive_vc_read, 1659 .write = pnv_xive_vc_write, 1660 .endianness = DEVICE_BIG_ENDIAN, 1661 .valid = { 1662 .min_access_size = 8, 1663 .max_access_size = 8, 1664 }, 1665 .impl = { 1666 .min_access_size = 8, 1667 .max_access_size = 8, 1668 }, 1669 }; 1670 1671 /* 1672 * Presenter Controller MMIO region. The Virtualization Controller 1673 * updates the IPB in the NVT table when required. Not modeled. 1674 */ 1675 static uint64_t pnv_xive_pc_read(void *opaque, hwaddr addr, 1676 unsigned size) 1677 { 1678 PnvXive *xive = PNV_XIVE(opaque); 1679 1680 xive_error(xive, "PC: invalid read @%"HWADDR_PRIx, addr); 1681 return -1; 1682 } 1683 1684 static void pnv_xive_pc_write(void *opaque, hwaddr addr, 1685 uint64_t value, unsigned size) 1686 { 1687 PnvXive *xive = PNV_XIVE(opaque); 1688 1689 xive_error(xive, "PC: invalid write to VC @%"HWADDR_PRIx, addr); 1690 } 1691 1692 static const MemoryRegionOps pnv_xive_pc_ops = { 1693 .read = pnv_xive_pc_read, 1694 .write = pnv_xive_pc_write, 1695 .endianness = DEVICE_BIG_ENDIAN, 1696 .valid = { 1697 .min_access_size = 8, 1698 .max_access_size = 8, 1699 }, 1700 .impl = { 1701 .min_access_size = 8, 1702 .max_access_size = 8, 1703 }, 1704 }; 1705 1706 static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, 1707 Monitor *mon) 1708 { 1709 uint8_t eq_blk = xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1); 1710 uint32_t eq_idx = xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1); 1711 1712 if (!xive_nvt_is_valid(nvt)) { 1713 return; 1714 } 1715 1716 monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx, 1717 eq_blk, eq_idx, 1718 xive_get_field32(NVT_W4_IPB, nvt->w4)); 1719 } 1720 1721 void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) 1722 { 1723 XiveRouter *xrtr = XIVE_ROUTER(xive); 1724 uint8_t blk = pnv_xive_block_id(xive); 1725 uint8_t chip_id = xive->chip->chip_id; 1726 uint32_t srcno0 = XIVE_EAS(blk, 0); 1727 uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk); 1728 XiveEAS eas; 1729 XiveEND end; 1730 XiveNVT nvt; 1731 int i; 1732 uint64_t xive_nvt_per_subpage; 1733 1734 monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk, 1735 srcno0, srcno0 + nr_ipis - 1); 1736 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); 1737 1738 monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk, 1739 srcno0, srcno0 + nr_ipis - 1); 1740 for (i = 0; i < nr_ipis; i++) { 1741 if (xive_router_get_eas(xrtr, blk, i, &eas)) { 1742 break; 1743 } 1744 if (!xive_eas_is_masked(&eas)) { 1745 xive_eas_pic_print_info(&eas, i, mon); 1746 } 1747 } 1748 1749 monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); 1750 i = 0; 1751 while (!xive_router_get_end(xrtr, blk, i, &end)) { 1752 xive_end_pic_print_info(&end, i++, mon); 1753 } 1754 1755 monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); 1756 i = 0; 1757 while (!xive_router_get_end(xrtr, blk, i, &end)) { 1758 xive_end_eas_pic_print_info(&end, i++, mon); 1759 } 1760 1761 monitor_printf(mon, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id, blk, 1762 0, XIVE_NVT_COUNT - 1); 1763 xive_nvt_per_subpage = pnv_xive_vst_per_subpage(xive, VST_TSEL_VPDT); 1764 for (i = 0; i < XIVE_NVT_COUNT; i += xive_nvt_per_subpage) { 1765 while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { 1766 xive_nvt_pic_print_info(&nvt, i++, mon); 1767 } 1768 } 1769 } 1770 1771 static void pnv_xive_reset(void *dev) 1772 { 1773 PnvXive *xive = PNV_XIVE(dev); 1774 XiveSource *xsrc = &xive->ipi_source; 1775 XiveENDSource *end_xsrc = &xive->end_source; 1776 1777 /* Default page size (Should be changed at runtime to 64k) */ 1778 xive->ic_shift = xive->vc_shift = xive->pc_shift = 12; 1779 1780 /* Clear subregions */ 1781 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 1782 memory_region_del_subregion(&xive->ipi_edt_mmio, &xsrc->esb_mmio); 1783 } 1784 1785 if (memory_region_is_mapped(&xive->ipi_edt_mmio)) { 1786 memory_region_del_subregion(&xive->ipi_mmio, &xive->ipi_edt_mmio); 1787 } 1788 1789 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 1790 memory_region_del_subregion(&xive->end_edt_mmio, &end_xsrc->esb_mmio); 1791 } 1792 1793 if (memory_region_is_mapped(&xive->end_edt_mmio)) { 1794 memory_region_del_subregion(&xive->end_mmio, &xive->end_edt_mmio); 1795 } 1796 } 1797 1798 static void pnv_xive_init(Object *obj) 1799 { 1800 PnvXive *xive = PNV_XIVE(obj); 1801 1802 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 1803 TYPE_XIVE_SOURCE); 1804 object_initialize_child(obj, "end_source", &xive->end_source, 1805 TYPE_XIVE_END_SOURCE); 1806 } 1807 1808 /* 1809 * Maximum number of IRQs and ENDs supported by HW 1810 */ 1811 #define PNV_XIVE_NR_IRQS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1812 #define PNV_XIVE_NR_ENDS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1813 1814 static void pnv_xive_realize(DeviceState *dev, Error **errp) 1815 { 1816 PnvXive *xive = PNV_XIVE(dev); 1817 PnvXiveClass *pxc = PNV_XIVE_GET_CLASS(dev); 1818 XiveSource *xsrc = &xive->ipi_source; 1819 XiveENDSource *end_xsrc = &xive->end_source; 1820 Error *local_err = NULL; 1821 1822 pxc->parent_realize(dev, &local_err); 1823 if (local_err) { 1824 error_propagate(errp, local_err); 1825 return; 1826 } 1827 1828 assert(xive->chip); 1829 1830 /* 1831 * The XiveSource and XiveENDSource objects are realized with the 1832 * maximum allowed HW configuration. The ESB MMIO regions will be 1833 * resized dynamically when the controller is configured by the FW 1834 * to limit accesses to resources not provisioned. 1835 */ 1836 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE_NR_IRQS, 1837 &error_fatal); 1838 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), &error_abort); 1839 if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { 1840 return; 1841 } 1842 1843 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE_NR_ENDS, 1844 &error_fatal); 1845 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 1846 &error_abort); 1847 if (!qdev_realize(DEVICE(end_xsrc), NULL, errp)) { 1848 return; 1849 } 1850 1851 /* Default page size. Generally changed at runtime to 64k */ 1852 xive->ic_shift = xive->vc_shift = xive->pc_shift = 12; 1853 1854 /* XSCOM region, used for initial configuration of the BARs */ 1855 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), &pnv_xive_xscom_ops, 1856 xive, "xscom-xive", PNV9_XSCOM_XIVE_SIZE << 3); 1857 1858 /* Interrupt controller MMIO regions */ 1859 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 1860 PNV9_XIVE_IC_SIZE); 1861 1862 memory_region_init_io(&xive->ic_reg_mmio, OBJECT(dev), &pnv_xive_ic_reg_ops, 1863 xive, "xive-ic-reg", 1 << xive->ic_shift); 1864 memory_region_init_io(&xive->ic_notify_mmio, OBJECT(dev), 1865 &pnv_xive_ic_notify_ops, 1866 xive, "xive-ic-notify", 1 << xive->ic_shift); 1867 1868 /* The Pervasive LSI trigger and EOI pages (not modeled) */ 1869 memory_region_init_io(&xive->ic_lsi_mmio, OBJECT(dev), &pnv_xive_ic_lsi_ops, 1870 xive, "xive-ic-lsi", 2 << xive->ic_shift); 1871 1872 /* Thread Interrupt Management Area (Indirect) */ 1873 memory_region_init_io(&xive->tm_indirect_mmio, OBJECT(dev), 1874 &xive_tm_indirect_ops, 1875 xive, "xive-tima-indirect", PNV9_XIVE_TM_SIZE); 1876 /* 1877 * Overall Virtualization Controller MMIO region containing the 1878 * IPI ESB pages and END ESB pages. The layout is defined by the 1879 * EDT "Domain table" and the accesses are dispatched using 1880 * address spaces for each. 1881 */ 1882 memory_region_init_io(&xive->vc_mmio, OBJECT(xive), &pnv_xive_vc_ops, xive, 1883 "xive-vc", PNV9_XIVE_VC_SIZE); 1884 1885 memory_region_init(&xive->ipi_mmio, OBJECT(xive), "xive-vc-ipi", 1886 PNV9_XIVE_VC_SIZE); 1887 address_space_init(&xive->ipi_as, &xive->ipi_mmio, "xive-vc-ipi"); 1888 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-vc-end", 1889 PNV9_XIVE_VC_SIZE); 1890 address_space_init(&xive->end_as, &xive->end_mmio, "xive-vc-end"); 1891 1892 /* 1893 * The MMIO windows exposing the IPI ESBs and the END ESBs in the 1894 * VC region. Their size is configured by the FW in the EDT table. 1895 */ 1896 memory_region_init(&xive->ipi_edt_mmio, OBJECT(xive), "xive-vc-ipi-edt", 0); 1897 memory_region_init(&xive->end_edt_mmio, OBJECT(xive), "xive-vc-end-edt", 0); 1898 1899 /* Presenter Controller MMIO region (not modeled) */ 1900 memory_region_init_io(&xive->pc_mmio, OBJECT(xive), &pnv_xive_pc_ops, xive, 1901 "xive-pc", PNV9_XIVE_PC_SIZE); 1902 1903 /* Thread Interrupt Management Area (Direct) */ 1904 memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops, 1905 xive, "xive-tima", PNV9_XIVE_TM_SIZE); 1906 1907 qemu_register_reset(pnv_xive_reset, dev); 1908 } 1909 1910 static int pnv_xive_dt_xscom(PnvXScomInterface *dev, void *fdt, 1911 int xscom_offset) 1912 { 1913 const char compat[] = "ibm,power9-xive-x"; 1914 char *name; 1915 int offset; 1916 uint32_t lpc_pcba = PNV9_XSCOM_XIVE_BASE; 1917 uint32_t reg[] = { 1918 cpu_to_be32(lpc_pcba), 1919 cpu_to_be32(PNV9_XSCOM_XIVE_SIZE) 1920 }; 1921 1922 name = g_strdup_printf("xive@%x", lpc_pcba); 1923 offset = fdt_add_subnode(fdt, xscom_offset, name); 1924 _FDT(offset); 1925 g_free(name); 1926 1927 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 1928 _FDT((fdt_setprop(fdt, offset, "compatible", compat, 1929 sizeof(compat)))); 1930 return 0; 1931 } 1932 1933 static Property pnv_xive_properties[] = { 1934 DEFINE_PROP_UINT64("ic-bar", PnvXive, ic_base, 0), 1935 DEFINE_PROP_UINT64("vc-bar", PnvXive, vc_base, 0), 1936 DEFINE_PROP_UINT64("pc-bar", PnvXive, pc_base, 0), 1937 DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0), 1938 /* The PnvChip id identifies the XIVE interrupt controller. */ 1939 DEFINE_PROP_LINK("chip", PnvXive, chip, TYPE_PNV_CHIP, PnvChip *), 1940 DEFINE_PROP_END_OF_LIST(), 1941 }; 1942 1943 static void pnv_xive_class_init(ObjectClass *klass, void *data) 1944 { 1945 DeviceClass *dc = DEVICE_CLASS(klass); 1946 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 1947 XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); 1948 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1949 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 1950 PnvXiveClass *pxc = PNV_XIVE_CLASS(klass); 1951 1952 xdc->dt_xscom = pnv_xive_dt_xscom; 1953 1954 dc->desc = "PowerNV XIVE Interrupt Controller"; 1955 device_class_set_parent_realize(dc, pnv_xive_realize, &pxc->parent_realize); 1956 dc->realize = pnv_xive_realize; 1957 device_class_set_props(dc, pnv_xive_properties); 1958 1959 xrc->get_eas = pnv_xive_get_eas; 1960 xrc->get_end = pnv_xive_get_end; 1961 xrc->write_end = pnv_xive_write_end; 1962 xrc->get_nvt = pnv_xive_get_nvt; 1963 xrc->write_nvt = pnv_xive_write_nvt; 1964 xrc->get_block_id = pnv_xive_get_block_id; 1965 1966 xnc->notify = pnv_xive_notify; 1967 xpc->match_nvt = pnv_xive_match_nvt; 1968 }; 1969 1970 static const TypeInfo pnv_xive_info = { 1971 .name = TYPE_PNV_XIVE, 1972 .parent = TYPE_XIVE_ROUTER, 1973 .instance_init = pnv_xive_init, 1974 .instance_size = sizeof(PnvXive), 1975 .class_init = pnv_xive_class_init, 1976 .class_size = sizeof(PnvXiveClass), 1977 .interfaces = (InterfaceInfo[]) { 1978 { TYPE_PNV_XSCOM_INTERFACE }, 1979 { } 1980 } 1981 }; 1982 1983 static void pnv_xive_register_types(void) 1984 { 1985 type_register_static(&pnv_xive_info); 1986 } 1987 1988 type_init(pnv_xive_register_types) 1989