1 /* 2 * Arm PrimeCell PL190 Vector Interrupt Controller 3 * 4 * Copyright (c) 2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/irq.h" 12 #include "hw/sysbus.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 16 /* The number of virtual priority levels. 16 user vectors plus the 17 unvectored IRQ. Chained interrupts would require an additional level 18 if implemented. */ 19 20 #define PL190_NUM_PRIO 17 21 22 #define TYPE_PL190 "pl190" 23 #define PL190(obj) OBJECT_CHECK(PL190State, (obj), TYPE_PL190) 24 25 typedef struct PL190State { 26 SysBusDevice parent_obj; 27 28 MemoryRegion iomem; 29 uint32_t level; 30 uint32_t soft_level; 31 uint32_t irq_enable; 32 uint32_t fiq_select; 33 uint8_t vect_control[16]; 34 uint32_t vect_addr[PL190_NUM_PRIO]; 35 /* Mask containing interrupts with higher priority than this one. */ 36 uint32_t prio_mask[PL190_NUM_PRIO + 1]; 37 int protected; 38 /* Current priority level. */ 39 int priority; 40 int prev_prio[PL190_NUM_PRIO]; 41 qemu_irq irq; 42 qemu_irq fiq; 43 } PL190State; 44 45 static const unsigned char pl190_id[] = 46 { 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 }; 47 48 static inline uint32_t pl190_irq_level(PL190State *s) 49 { 50 return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select; 51 } 52 53 /* Update interrupts. */ 54 static void pl190_update(PL190State *s) 55 { 56 uint32_t level = pl190_irq_level(s); 57 int set; 58 59 set = (level & s->prio_mask[s->priority]) != 0; 60 qemu_set_irq(s->irq, set); 61 set = ((s->level | s->soft_level) & s->fiq_select) != 0; 62 qemu_set_irq(s->fiq, set); 63 } 64 65 static void pl190_set_irq(void *opaque, int irq, int level) 66 { 67 PL190State *s = (PL190State *)opaque; 68 69 if (level) 70 s->level |= 1u << irq; 71 else 72 s->level &= ~(1u << irq); 73 pl190_update(s); 74 } 75 76 static void pl190_update_vectors(PL190State *s) 77 { 78 uint32_t mask; 79 int i; 80 int n; 81 82 mask = 0; 83 for (i = 0; i < 16; i++) 84 { 85 s->prio_mask[i] = mask; 86 if (s->vect_control[i] & 0x20) 87 { 88 n = s->vect_control[i] & 0x1f; 89 mask |= 1 << n; 90 } 91 } 92 s->prio_mask[16] = mask; 93 pl190_update(s); 94 } 95 96 static uint64_t pl190_read(void *opaque, hwaddr offset, 97 unsigned size) 98 { 99 PL190State *s = (PL190State *)opaque; 100 int i; 101 102 if (offset >= 0xfe0 && offset < 0x1000) { 103 return pl190_id[(offset - 0xfe0) >> 2]; 104 } 105 if (offset >= 0x100 && offset < 0x140) { 106 return s->vect_addr[(offset - 0x100) >> 2]; 107 } 108 if (offset >= 0x200 && offset < 0x240) { 109 return s->vect_control[(offset - 0x200) >> 2]; 110 } 111 switch (offset >> 2) { 112 case 0: /* IRQSTATUS */ 113 return pl190_irq_level(s); 114 case 1: /* FIQSATUS */ 115 return (s->level | s->soft_level) & s->fiq_select; 116 case 2: /* RAWINTR */ 117 return s->level | s->soft_level; 118 case 3: /* INTSELECT */ 119 return s->fiq_select; 120 case 4: /* INTENABLE */ 121 return s->irq_enable; 122 case 6: /* SOFTINT */ 123 return s->soft_level; 124 case 8: /* PROTECTION */ 125 return s->protected; 126 case 12: /* VECTADDR */ 127 /* Read vector address at the start of an ISR. Increases the 128 * current priority level to that of the current interrupt. 129 * 130 * Since an enabled interrupt X at priority P causes prio_mask[Y] 131 * to have bit X set for all Y > P, this loop will stop with 132 * i == the priority of the highest priority set interrupt. 133 */ 134 for (i = 0; i < s->priority; i++) { 135 if ((s->level | s->soft_level) & s->prio_mask[i + 1]) { 136 break; 137 } 138 } 139 140 /* Reading this value with no pending interrupts is undefined. 141 We return the default address. */ 142 if (i == PL190_NUM_PRIO) 143 return s->vect_addr[16]; 144 if (i < s->priority) 145 { 146 s->prev_prio[i] = s->priority; 147 s->priority = i; 148 pl190_update(s); 149 } 150 return s->vect_addr[s->priority]; 151 case 13: /* DEFVECTADDR */ 152 return s->vect_addr[16]; 153 default: 154 qemu_log_mask(LOG_GUEST_ERROR, 155 "pl190_read: Bad offset %x\n", (int)offset); 156 return 0; 157 } 158 } 159 160 static void pl190_write(void *opaque, hwaddr offset, 161 uint64_t val, unsigned size) 162 { 163 PL190State *s = (PL190State *)opaque; 164 165 if (offset >= 0x100 && offset < 0x140) { 166 s->vect_addr[(offset - 0x100) >> 2] = val; 167 pl190_update_vectors(s); 168 return; 169 } 170 if (offset >= 0x200 && offset < 0x240) { 171 s->vect_control[(offset - 0x200) >> 2] = val; 172 pl190_update_vectors(s); 173 return; 174 } 175 switch (offset >> 2) { 176 case 0: /* SELECT */ 177 /* This is a readonly register, but linux tries to write to it 178 anyway. Ignore the write. */ 179 break; 180 case 3: /* INTSELECT */ 181 s->fiq_select = val; 182 break; 183 case 4: /* INTENABLE */ 184 s->irq_enable |= val; 185 break; 186 case 5: /* INTENCLEAR */ 187 s->irq_enable &= ~val; 188 break; 189 case 6: /* SOFTINT */ 190 s->soft_level |= val; 191 break; 192 case 7: /* SOFTINTCLEAR */ 193 s->soft_level &= ~val; 194 break; 195 case 8: /* PROTECTION */ 196 /* TODO: Protection (supervisor only access) is not implemented. */ 197 s->protected = val & 1; 198 break; 199 case 12: /* VECTADDR */ 200 /* Restore the previous priority level. The value written is 201 ignored. */ 202 if (s->priority < PL190_NUM_PRIO) 203 s->priority = s->prev_prio[s->priority]; 204 break; 205 case 13: /* DEFVECTADDR */ 206 s->vect_addr[16] = val; 207 break; 208 case 0xc0: /* ITCR */ 209 if (val) { 210 qemu_log_mask(LOG_UNIMP, "pl190: Test mode not implemented\n"); 211 } 212 break; 213 default: 214 qemu_log_mask(LOG_GUEST_ERROR, 215 "pl190_write: Bad offset %x\n", (int)offset); 216 return; 217 } 218 pl190_update(s); 219 } 220 221 static const MemoryRegionOps pl190_ops = { 222 .read = pl190_read, 223 .write = pl190_write, 224 .endianness = DEVICE_NATIVE_ENDIAN, 225 }; 226 227 static void pl190_reset(DeviceState *d) 228 { 229 PL190State *s = PL190(d); 230 int i; 231 232 for (i = 0; i < 16; i++) { 233 s->vect_addr[i] = 0; 234 s->vect_control[i] = 0; 235 } 236 s->vect_addr[16] = 0; 237 s->prio_mask[17] = 0xffffffff; 238 s->priority = PL190_NUM_PRIO; 239 pl190_update_vectors(s); 240 } 241 242 static void pl190_init(Object *obj) 243 { 244 DeviceState *dev = DEVICE(obj); 245 PL190State *s = PL190(obj); 246 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 247 248 memory_region_init_io(&s->iomem, obj, &pl190_ops, s, "pl190", 0x1000); 249 sysbus_init_mmio(sbd, &s->iomem); 250 qdev_init_gpio_in(dev, pl190_set_irq, 32); 251 sysbus_init_irq(sbd, &s->irq); 252 sysbus_init_irq(sbd, &s->fiq); 253 } 254 255 static const VMStateDescription vmstate_pl190 = { 256 .name = "pl190", 257 .version_id = 1, 258 .minimum_version_id = 1, 259 .fields = (VMStateField[]) { 260 VMSTATE_UINT32(level, PL190State), 261 VMSTATE_UINT32(soft_level, PL190State), 262 VMSTATE_UINT32(irq_enable, PL190State), 263 VMSTATE_UINT32(fiq_select, PL190State), 264 VMSTATE_UINT8_ARRAY(vect_control, PL190State, 16), 265 VMSTATE_UINT32_ARRAY(vect_addr, PL190State, PL190_NUM_PRIO), 266 VMSTATE_UINT32_ARRAY(prio_mask, PL190State, PL190_NUM_PRIO+1), 267 VMSTATE_INT32(protected, PL190State), 268 VMSTATE_INT32(priority, PL190State), 269 VMSTATE_INT32_ARRAY(prev_prio, PL190State, PL190_NUM_PRIO), 270 VMSTATE_END_OF_LIST() 271 } 272 }; 273 274 static void pl190_class_init(ObjectClass *klass, void *data) 275 { 276 DeviceClass *dc = DEVICE_CLASS(klass); 277 278 dc->reset = pl190_reset; 279 dc->vmsd = &vmstate_pl190; 280 } 281 282 static const TypeInfo pl190_info = { 283 .name = TYPE_PL190, 284 .parent = TYPE_SYS_BUS_DEVICE, 285 .instance_size = sizeof(PL190State), 286 .instance_init = pl190_init, 287 .class_init = pl190_class_init, 288 }; 289 290 static void pl190_register_types(void) 291 { 292 type_register_static(&pl190_info); 293 } 294 295 type_init(pl190_register_types) 296