1 /* 2 * KVM in-kernel OpenPIC 3 * 4 * Copyright 2013 Freescale Semiconductor, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include <sys/ioctl.h> 26 #include "exec/address-spaces.h" 27 #include "hw/hw.h" 28 #include "hw/ppc/openpic.h" 29 #include "hw/pci/msi.h" 30 #include "hw/sysbus.h" 31 #include "sysemu/kvm.h" 32 #include "qemu/log.h" 33 34 #define KVM_OPENPIC(obj) \ 35 OBJECT_CHECK(KVMOpenPICState, (obj), TYPE_KVM_OPENPIC) 36 37 typedef struct KVMOpenPICState { 38 /*< private >*/ 39 SysBusDevice parent_obj; 40 /*< public >*/ 41 42 MemoryRegion mem; 43 MemoryListener mem_listener; 44 uint32_t fd; 45 uint32_t model; 46 } KVMOpenPICState; 47 48 static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level) 49 { 50 kvm_set_irq(kvm_state, n_IRQ, level); 51 } 52 53 static void kvm_openpic_reset(DeviceState *d) 54 { 55 qemu_log_mask(LOG_UNIMP, "%s: unimplemented\n", __func__); 56 } 57 58 static void kvm_openpic_write(void *opaque, hwaddr addr, uint64_t val, 59 unsigned size) 60 { 61 KVMOpenPICState *opp = opaque; 62 struct kvm_device_attr attr; 63 uint32_t val32 = val; 64 int ret; 65 66 attr.group = KVM_DEV_MPIC_GRP_REGISTER; 67 attr.attr = addr; 68 attr.addr = (uint64_t)(unsigned long)&val32; 69 70 ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr); 71 if (ret < 0) { 72 qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__, 73 strerror(errno), attr.attr); 74 } 75 } 76 77 static uint64_t kvm_openpic_read(void *opaque, hwaddr addr, unsigned size) 78 { 79 KVMOpenPICState *opp = opaque; 80 struct kvm_device_attr attr; 81 uint32_t val = 0xdeadbeef; 82 int ret; 83 84 attr.group = KVM_DEV_MPIC_GRP_REGISTER; 85 attr.attr = addr; 86 attr.addr = (uint64_t)(unsigned long)&val; 87 88 ret = ioctl(opp->fd, KVM_GET_DEVICE_ATTR, &attr); 89 if (ret < 0) { 90 qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__, 91 strerror(errno), attr.attr); 92 return 0; 93 } 94 95 return val; 96 } 97 98 static const MemoryRegionOps kvm_openpic_mem_ops = { 99 .write = kvm_openpic_write, 100 .read = kvm_openpic_read, 101 .endianness = DEVICE_BIG_ENDIAN, 102 .impl = { 103 .min_access_size = 4, 104 .max_access_size = 4, 105 }, 106 }; 107 108 static void kvm_openpic_region_add(MemoryListener *listener, 109 MemoryRegionSection *section) 110 { 111 KVMOpenPICState *opp = container_of(listener, KVMOpenPICState, 112 mem_listener); 113 struct kvm_device_attr attr; 114 uint64_t reg_base; 115 int ret; 116 117 if (section->address_space != &address_space_memory) { 118 abort(); 119 } 120 121 /* Ignore events on regions that are not us */ 122 if (section->mr != &opp->mem) { 123 return; 124 } 125 126 reg_base = section->offset_within_address_space; 127 128 attr.group = KVM_DEV_MPIC_GRP_MISC; 129 attr.attr = KVM_DEV_MPIC_BASE_ADDR; 130 attr.addr = (uint64_t)(unsigned long)®_base; 131 132 ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr); 133 if (ret < 0) { 134 fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__, 135 strerror(errno), reg_base); 136 } 137 } 138 139 static void kvm_openpic_region_del(MemoryListener *listener, 140 MemoryRegionSection *section) 141 { 142 KVMOpenPICState *opp = container_of(listener, KVMOpenPICState, 143 mem_listener); 144 struct kvm_device_attr attr; 145 uint64_t reg_base = 0; 146 int ret; 147 148 /* Ignore events on regions that are not us */ 149 if (section->mr != &opp->mem) { 150 return; 151 } 152 153 attr.group = KVM_DEV_MPIC_GRP_MISC; 154 attr.attr = KVM_DEV_MPIC_BASE_ADDR; 155 attr.addr = (uint64_t)(unsigned long)®_base; 156 157 ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr); 158 if (ret < 0) { 159 fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__, 160 strerror(errno), reg_base); 161 } 162 } 163 164 static void kvm_openpic_init(Object *obj) 165 { 166 KVMOpenPICState *opp = KVM_OPENPIC(obj); 167 168 memory_region_init_io(&opp->mem, OBJECT(opp), &kvm_openpic_mem_ops, opp, 169 "kvm-openpic", 0x40000); 170 } 171 172 static void kvm_openpic_realize(DeviceState *dev, Error **errp) 173 { 174 SysBusDevice *d = SYS_BUS_DEVICE(dev); 175 KVMOpenPICState *opp = KVM_OPENPIC(dev); 176 KVMState *s = kvm_state; 177 int kvm_openpic_model; 178 struct kvm_create_device cd = {0}; 179 int ret, i; 180 181 if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) { 182 error_setg(errp, "Kernel is lacking Device Control API"); 183 return; 184 } 185 186 switch (opp->model) { 187 case OPENPIC_MODEL_FSL_MPIC_20: 188 kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20; 189 break; 190 191 case OPENPIC_MODEL_FSL_MPIC_42: 192 kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42; 193 break; 194 195 default: 196 error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model); 197 return; 198 } 199 200 cd.type = kvm_openpic_model; 201 ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd); 202 if (ret < 0) { 203 error_setg(errp, "Can't create device %d: %s", 204 cd.type, strerror(errno)); 205 return; 206 } 207 opp->fd = cd.fd; 208 209 sysbus_init_mmio(d, &opp->mem); 210 qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ); 211 212 opp->mem_listener.region_add = kvm_openpic_region_add; 213 opp->mem_listener.region_del = kvm_openpic_region_del; 214 memory_listener_register(&opp->mem_listener, &address_space_memory); 215 216 /* indicate pic capabilities */ 217 msi_supported = true; 218 kvm_kernel_irqchip = true; 219 kvm_async_interrupts_allowed = true; 220 221 /* set up irq routing */ 222 kvm_init_irq_routing(kvm_state); 223 for (i = 0; i < 256; ++i) { 224 kvm_irqchip_add_irq_route(kvm_state, i, 0, i); 225 } 226 227 kvm_irqfds_allowed = true; 228 kvm_msi_via_irqfd_allowed = true; 229 kvm_gsi_routing_allowed = true; 230 231 kvm_irqchip_commit_routes(s); 232 } 233 234 int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs) 235 { 236 KVMOpenPICState *opp = KVM_OPENPIC(d); 237 238 return kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_MPIC, 0, opp->fd, 239 kvm_arch_vcpu_id(cs)); 240 } 241 242 static Property kvm_openpic_properties[] = { 243 DEFINE_PROP_UINT32("model", KVMOpenPICState, model, 244 OPENPIC_MODEL_FSL_MPIC_20), 245 DEFINE_PROP_END_OF_LIST(), 246 }; 247 248 static void kvm_openpic_class_init(ObjectClass *oc, void *data) 249 { 250 DeviceClass *dc = DEVICE_CLASS(oc); 251 252 dc->realize = kvm_openpic_realize; 253 dc->props = kvm_openpic_properties; 254 dc->reset = kvm_openpic_reset; 255 } 256 257 static const TypeInfo kvm_openpic_info = { 258 .name = TYPE_KVM_OPENPIC, 259 .parent = TYPE_SYS_BUS_DEVICE, 260 .instance_size = sizeof(KVMOpenPICState), 261 .instance_init = kvm_openpic_init, 262 .class_init = kvm_openpic_class_init, 263 }; 264 265 static void kvm_openpic_register_types(void) 266 { 267 type_register_static(&kvm_openpic_info); 268 } 269 270 type_init(kvm_openpic_register_types) 271