1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Authors: Stafford Horne <shorne@gmail.com> 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 #include "qapi/error.h" 13 #include "hw/hw.h" 14 #include "hw/sysbus.h" 15 #include "exec/memory.h" 16 17 #define TYPE_OR1K_OMPIC "or1k-ompic" 18 #define OR1K_OMPIC(obj) OBJECT_CHECK(OR1KOMPICState, (obj), TYPE_OR1K_OMPIC) 19 20 #define OMPIC_CTRL_IRQ_ACK (1 << 31) 21 #define OMPIC_CTRL_IRQ_GEN (1 << 30) 22 #define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff) 23 24 #define OMPIC_REG(addr) (((addr) >> 2) & 0x1) 25 #define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f) 26 #define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f) 27 28 #define OMPIC_STATUS_IRQ_PENDING (1 << 30) 29 #define OMPIC_STATUS_SRC(cpu) (((cpu) & 0x3fff) << 16) 30 #define OMPIC_STATUS_DATA(data) ((data) & 0xffff) 31 32 #define OMPIC_CONTROL 0 33 #define OMPIC_STATUS 1 34 35 #define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory */ 36 #define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per cpu */ 37 38 typedef struct OR1KOMPICState OR1KOMPICState; 39 typedef struct OR1KOMPICCPUState OR1KOMPICCPUState; 40 41 struct OR1KOMPICCPUState { 42 qemu_irq irq; 43 uint32_t status; 44 uint32_t control; 45 }; 46 47 struct OR1KOMPICState { 48 SysBusDevice parent_obj; 49 MemoryRegion mr; 50 51 OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS]; 52 53 uint32_t num_cpus; 54 }; 55 56 static uint64_t ompic_read(void *opaque, hwaddr addr, unsigned size) 57 { 58 OR1KOMPICState *s = opaque; 59 int src_cpu = OMPIC_SRC_CPU(addr); 60 61 /* We can only write to control control, write control + update status */ 62 if (OMPIC_REG(addr) == OMPIC_CONTROL) { 63 return s->cpus[src_cpu].control; 64 } else { 65 return s->cpus[src_cpu].status; 66 } 67 68 } 69 70 static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) 71 { 72 OR1KOMPICState *s = opaque; 73 /* We can only write to control control, write control + update status */ 74 if (OMPIC_REG(addr) == OMPIC_CONTROL) { 75 int src_cpu = OMPIC_SRC_CPU(addr); 76 77 s->cpus[src_cpu].control = data; 78 79 if (data & OMPIC_CTRL_IRQ_GEN) { 80 int dst_cpu = OMPIC_CTRL_DST(data); 81 82 s->cpus[dst_cpu].status = OMPIC_STATUS_IRQ_PENDING | 83 OMPIC_STATUS_SRC(src_cpu) | 84 OMPIC_STATUS_DATA(data); 85 86 qemu_irq_raise(s->cpus[dst_cpu].irq); 87 } 88 if (data & OMPIC_CTRL_IRQ_ACK) { 89 s->cpus[src_cpu].status &= ~OMPIC_STATUS_IRQ_PENDING; 90 qemu_irq_lower(s->cpus[src_cpu].irq); 91 } 92 } 93 } 94 95 static const MemoryRegionOps ompic_ops = { 96 .read = ompic_read, 97 .write = ompic_write, 98 .endianness = DEVICE_NATIVE_ENDIAN, 99 .impl = { 100 .max_access_size = 8, 101 }, 102 }; 103 104 static void or1k_ompic_init(Object *obj) 105 { 106 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 107 OR1KOMPICState *s = OR1K_OMPIC(obj); 108 109 memory_region_init_io(&s->mr, OBJECT(s), &ompic_ops, s, 110 "or1k-ompic", OMPIC_ADDRSPACE_SZ); 111 sysbus_init_mmio(sbd, &s->mr); 112 } 113 114 static void or1k_ompic_realize(DeviceState *dev, Error **errp) 115 { 116 OR1KOMPICState *s = OR1K_OMPIC(dev); 117 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 118 int i; 119 120 if (s->num_cpus > OMPIC_MAX_CPUS) { 121 error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus); 122 return; 123 } 124 /* Init IRQ sources for all CPUs */ 125 for (i = 0; i < s->num_cpus; i++) { 126 sysbus_init_irq(sbd, &s->cpus[i].irq); 127 } 128 } 129 130 static Property or1k_ompic_properties[] = { 131 DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1), 132 DEFINE_PROP_END_OF_LIST(), 133 }; 134 135 static const VMStateDescription vmstate_or1k_ompic_cpu = { 136 .name = "or1k_ompic_cpu", 137 .version_id = 1, 138 .minimum_version_id = 1, 139 .fields = (VMStateField[]) { 140 VMSTATE_UINT32(status, OR1KOMPICCPUState), 141 VMSTATE_UINT32(control, OR1KOMPICCPUState), 142 VMSTATE_END_OF_LIST() 143 } 144 }; 145 146 static const VMStateDescription vmstate_or1k_ompic = { 147 .name = TYPE_OR1K_OMPIC, 148 .version_id = 1, 149 .minimum_version_id = 1, 150 .fields = (VMStateField[]) { 151 VMSTATE_STRUCT_ARRAY(cpus, OR1KOMPICState, OMPIC_MAX_CPUS, 1, 152 vmstate_or1k_ompic_cpu, OR1KOMPICCPUState), 153 VMSTATE_UINT32(num_cpus, OR1KOMPICState), 154 VMSTATE_END_OF_LIST() 155 } 156 }; 157 158 static void or1k_ompic_class_init(ObjectClass *klass, void *data) 159 { 160 DeviceClass *dc = DEVICE_CLASS(klass); 161 162 dc->props = or1k_ompic_properties; 163 dc->realize = or1k_ompic_realize; 164 dc->vmsd = &vmstate_or1k_ompic; 165 } 166 167 static const TypeInfo or1k_ompic_info = { 168 .name = TYPE_OR1K_OMPIC, 169 .parent = TYPE_SYS_BUS_DEVICE, 170 .instance_size = sizeof(OR1KOMPICState), 171 .instance_init = or1k_ompic_init, 172 .class_init = or1k_ompic_class_init, 173 }; 174 175 static void or1k_ompic_register_types(void) 176 { 177 type_register_static(&or1k_ompic_info); 178 } 179 180 type_init(or1k_ompic_register_types) 181