1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Authors: Stafford Horne <shorne@gmail.com> 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qapi/error.h" 12 #include "hw/hw.h" 13 #include "hw/sysbus.h" 14 #include "exec/memory.h" 15 16 #define TYPE_OR1K_OMPIC "or1k-ompic" 17 #define OR1K_OMPIC(obj) OBJECT_CHECK(OR1KOMPICState, (obj), TYPE_OR1K_OMPIC) 18 19 #define OMPIC_CTRL_IRQ_ACK (1 << 31) 20 #define OMPIC_CTRL_IRQ_GEN (1 << 30) 21 #define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff) 22 23 #define OMPIC_REG(addr) (((addr) >> 2) & 0x1) 24 #define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f) 25 #define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f) 26 27 #define OMPIC_STATUS_IRQ_PENDING (1 << 30) 28 #define OMPIC_STATUS_SRC(cpu) (((cpu) & 0x3fff) << 16) 29 #define OMPIC_STATUS_DATA(data) ((data) & 0xffff) 30 31 #define OMPIC_CONTROL 0 32 #define OMPIC_STATUS 1 33 34 #define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory */ 35 #define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per cpu */ 36 37 typedef struct OR1KOMPICState OR1KOMPICState; 38 typedef struct OR1KOMPICCPUState OR1KOMPICCPUState; 39 40 struct OR1KOMPICCPUState { 41 qemu_irq irq; 42 uint32_t status; 43 uint32_t control; 44 }; 45 46 struct OR1KOMPICState { 47 SysBusDevice parent_obj; 48 MemoryRegion mr; 49 50 OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS]; 51 52 uint32_t num_cpus; 53 }; 54 55 static uint64_t ompic_read(void *opaque, hwaddr addr, unsigned size) 56 { 57 OR1KOMPICState *s = opaque; 58 int src_cpu = OMPIC_SRC_CPU(addr); 59 60 /* We can only write to control control, write control + update status */ 61 if (OMPIC_REG(addr) == OMPIC_CONTROL) { 62 return s->cpus[src_cpu].control; 63 } else { 64 return s->cpus[src_cpu].status; 65 } 66 67 } 68 69 static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) 70 { 71 OR1KOMPICState *s = opaque; 72 /* We can only write to control control, write control + update status */ 73 if (OMPIC_REG(addr) == OMPIC_CONTROL) { 74 int src_cpu = OMPIC_SRC_CPU(addr); 75 76 s->cpus[src_cpu].control = data; 77 78 if (data & OMPIC_CTRL_IRQ_GEN) { 79 int dst_cpu = OMPIC_CTRL_DST(data); 80 81 s->cpus[dst_cpu].status = OMPIC_STATUS_IRQ_PENDING | 82 OMPIC_STATUS_SRC(src_cpu) | 83 OMPIC_STATUS_DATA(data); 84 85 qemu_irq_raise(s->cpus[dst_cpu].irq); 86 } 87 if (data & OMPIC_CTRL_IRQ_ACK) { 88 s->cpus[src_cpu].status &= ~OMPIC_STATUS_IRQ_PENDING; 89 qemu_irq_lower(s->cpus[src_cpu].irq); 90 } 91 } 92 } 93 94 static const MemoryRegionOps ompic_ops = { 95 .read = ompic_read, 96 .write = ompic_write, 97 .endianness = DEVICE_NATIVE_ENDIAN, 98 .impl = { 99 .max_access_size = 8, 100 }, 101 }; 102 103 static void or1k_ompic_init(Object *obj) 104 { 105 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 106 OR1KOMPICState *s = OR1K_OMPIC(obj); 107 108 memory_region_init_io(&s->mr, OBJECT(s), &ompic_ops, s, 109 "or1k-ompic", OMPIC_ADDRSPACE_SZ); 110 sysbus_init_mmio(sbd, &s->mr); 111 } 112 113 static void or1k_ompic_realize(DeviceState *dev, Error **errp) 114 { 115 OR1KOMPICState *s = OR1K_OMPIC(dev); 116 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 117 int i; 118 119 if (s->num_cpus > OMPIC_MAX_CPUS) { 120 error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus); 121 return; 122 } 123 /* Init IRQ sources for all CPUs */ 124 for (i = 0; i < s->num_cpus; i++) { 125 sysbus_init_irq(sbd, &s->cpus[i].irq); 126 } 127 } 128 129 static Property or1k_ompic_properties[] = { 130 DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1), 131 DEFINE_PROP_END_OF_LIST(), 132 }; 133 134 static const VMStateDescription vmstate_or1k_ompic_cpu = { 135 .name = "or1k_ompic_cpu", 136 .version_id = 1, 137 .minimum_version_id = 1, 138 .fields = (VMStateField[]) { 139 VMSTATE_UINT32(status, OR1KOMPICCPUState), 140 VMSTATE_UINT32(control, OR1KOMPICCPUState), 141 VMSTATE_END_OF_LIST() 142 } 143 }; 144 145 static const VMStateDescription vmstate_or1k_ompic = { 146 .name = TYPE_OR1K_OMPIC, 147 .version_id = 1, 148 .minimum_version_id = 1, 149 .fields = (VMStateField[]) { 150 VMSTATE_STRUCT_ARRAY(cpus, OR1KOMPICState, OMPIC_MAX_CPUS, 1, 151 vmstate_or1k_ompic_cpu, OR1KOMPICCPUState), 152 VMSTATE_UINT32(num_cpus, OR1KOMPICState), 153 VMSTATE_END_OF_LIST() 154 } 155 }; 156 157 static void or1k_ompic_class_init(ObjectClass *klass, void *data) 158 { 159 DeviceClass *dc = DEVICE_CLASS(klass); 160 161 dc->props = or1k_ompic_properties; 162 dc->realize = or1k_ompic_realize; 163 dc->vmsd = &vmstate_or1k_ompic; 164 } 165 166 static const TypeInfo or1k_ompic_info = { 167 .name = TYPE_OR1K_OMPIC, 168 .parent = TYPE_SYS_BUS_DEVICE, 169 .instance_size = sizeof(OR1KOMPICState), 170 .instance_init = or1k_ompic_init, 171 .class_init = or1k_ompic_class_init, 172 }; 173 174 static void or1k_ompic_register_types(void) 175 { 176 type_register_static(&or1k_ompic_info); 177 } 178 179 type_init(or1k_ompic_register_types) 180