1 /* 2 * TI OMAP interrupt controller emulation. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * Copyright (C) 2007-2008 Nokia Corporation 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 or 10 * (at your option) version 3 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "hw/hw.h" 21 #include "hw/arm/omap.h" 22 #include "hw/sysbus.h" 23 24 /* Interrupt Handlers */ 25 struct omap_intr_handler_bank_s { 26 uint32_t irqs; 27 uint32_t inputs; 28 uint32_t mask; 29 uint32_t fiq; 30 uint32_t sens_edge; 31 uint32_t swi; 32 unsigned char priority[32]; 33 }; 34 35 #define TYPE_OMAP_INTC "common-omap-intc" 36 #define OMAP_INTC(obj) \ 37 OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC) 38 39 struct omap_intr_handler_s { 40 SysBusDevice parent_obj; 41 42 qemu_irq *pins; 43 qemu_irq parent_intr[2]; 44 MemoryRegion mmio; 45 void *iclk; 46 void *fclk; 47 unsigned char nbanks; 48 int level_only; 49 uint32_t size; 50 51 uint8_t revision; 52 53 /* state */ 54 uint32_t new_agr[2]; 55 int sir_intr[2]; 56 int autoidle; 57 uint32_t mask; 58 struct omap_intr_handler_bank_s bank[3]; 59 }; 60 61 static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) 62 { 63 int i, j, sir_intr, p_intr, p; 64 uint32_t level; 65 sir_intr = 0; 66 p_intr = 255; 67 68 /* Find the interrupt line with the highest dynamic priority. 69 * Note: 0 denotes the hightest priority. 70 * If all interrupts have the same priority, the default order is IRQ_N, 71 * IRQ_N-1,...,IRQ_0. */ 72 for (j = 0; j < s->nbanks; ++j) { 73 level = s->bank[j].irqs & ~s->bank[j].mask & 74 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); 75 76 while (level != 0) { 77 i = ctz32(level); 78 p = s->bank[j].priority[i]; 79 if (p <= p_intr) { 80 p_intr = p; 81 sir_intr = 32 * j + i; 82 } 83 level &= level - 1; 84 } 85 } 86 s->sir_intr[is_fiq] = sir_intr; 87 } 88 89 static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) 90 { 91 int i; 92 uint32_t has_intr = 0; 93 94 for (i = 0; i < s->nbanks; ++i) 95 has_intr |= s->bank[i].irqs & ~s->bank[i].mask & 96 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); 97 98 if (s->new_agr[is_fiq] & has_intr & s->mask) { 99 s->new_agr[is_fiq] = 0; 100 omap_inth_sir_update(s, is_fiq); 101 qemu_set_irq(s->parent_intr[is_fiq], 1); 102 } 103 } 104 105 #define INT_FALLING_EDGE 0 106 #define INT_LOW_LEVEL 1 107 108 static void omap_set_intr(void *opaque, int irq, int req) 109 { 110 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; 111 uint32_t rise; 112 113 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; 114 int n = irq & 31; 115 116 if (req) { 117 rise = ~bank->irqs & (1 << n); 118 if (~bank->sens_edge & (1 << n)) 119 rise &= ~bank->inputs; 120 121 bank->inputs |= (1 << n); 122 if (rise) { 123 bank->irqs |= rise; 124 omap_inth_update(ih, 0); 125 omap_inth_update(ih, 1); 126 } 127 } else { 128 rise = bank->sens_edge & bank->irqs & (1 << n); 129 bank->irqs &= ~rise; 130 bank->inputs &= ~(1 << n); 131 } 132 } 133 134 /* Simplified version with no edge detection */ 135 static void omap_set_intr_noedge(void *opaque, int irq, int req) 136 { 137 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; 138 uint32_t rise; 139 140 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; 141 int n = irq & 31; 142 143 if (req) { 144 rise = ~bank->inputs & (1 << n); 145 if (rise) { 146 bank->irqs |= bank->inputs |= rise; 147 omap_inth_update(ih, 0); 148 omap_inth_update(ih, 1); 149 } 150 } else 151 bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi; 152 } 153 154 static uint64_t omap_inth_read(void *opaque, hwaddr addr, 155 unsigned size) 156 { 157 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; 158 int i, offset = addr; 159 int bank_no = offset >> 8; 160 int line_no; 161 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; 162 offset &= 0xff; 163 164 switch (offset) { 165 case 0x00: /* ITR */ 166 return bank->irqs; 167 168 case 0x04: /* MIR */ 169 return bank->mask; 170 171 case 0x10: /* SIR_IRQ_CODE */ 172 case 0x14: /* SIR_FIQ_CODE */ 173 if (bank_no != 0) 174 break; 175 line_no = s->sir_intr[(offset - 0x10) >> 2]; 176 bank = &s->bank[line_no >> 5]; 177 i = line_no & 31; 178 if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) 179 bank->irqs &= ~(1 << i); 180 return line_no; 181 182 case 0x18: /* CONTROL_REG */ 183 if (bank_no != 0) 184 break; 185 return 0; 186 187 case 0x1c: /* ILR0 */ 188 case 0x20: /* ILR1 */ 189 case 0x24: /* ILR2 */ 190 case 0x28: /* ILR3 */ 191 case 0x2c: /* ILR4 */ 192 case 0x30: /* ILR5 */ 193 case 0x34: /* ILR6 */ 194 case 0x38: /* ILR7 */ 195 case 0x3c: /* ILR8 */ 196 case 0x40: /* ILR9 */ 197 case 0x44: /* ILR10 */ 198 case 0x48: /* ILR11 */ 199 case 0x4c: /* ILR12 */ 200 case 0x50: /* ILR13 */ 201 case 0x54: /* ILR14 */ 202 case 0x58: /* ILR15 */ 203 case 0x5c: /* ILR16 */ 204 case 0x60: /* ILR17 */ 205 case 0x64: /* ILR18 */ 206 case 0x68: /* ILR19 */ 207 case 0x6c: /* ILR20 */ 208 case 0x70: /* ILR21 */ 209 case 0x74: /* ILR22 */ 210 case 0x78: /* ILR23 */ 211 case 0x7c: /* ILR24 */ 212 case 0x80: /* ILR25 */ 213 case 0x84: /* ILR26 */ 214 case 0x88: /* ILR27 */ 215 case 0x8c: /* ILR28 */ 216 case 0x90: /* ILR29 */ 217 case 0x94: /* ILR30 */ 218 case 0x98: /* ILR31 */ 219 i = (offset - 0x1c) >> 2; 220 return (bank->priority[i] << 2) | 221 (((bank->sens_edge >> i) & 1) << 1) | 222 ((bank->fiq >> i) & 1); 223 224 case 0x9c: /* ISR */ 225 return 0x00000000; 226 227 } 228 OMAP_BAD_REG(addr); 229 return 0; 230 } 231 232 static void omap_inth_write(void *opaque, hwaddr addr, 233 uint64_t value, unsigned size) 234 { 235 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; 236 int i, offset = addr; 237 int bank_no = offset >> 8; 238 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; 239 offset &= 0xff; 240 241 switch (offset) { 242 case 0x00: /* ITR */ 243 /* Important: ignore the clearing if the IRQ is level-triggered and 244 the input bit is 1 */ 245 bank->irqs &= value | (bank->inputs & bank->sens_edge); 246 return; 247 248 case 0x04: /* MIR */ 249 bank->mask = value; 250 omap_inth_update(s, 0); 251 omap_inth_update(s, 1); 252 return; 253 254 case 0x10: /* SIR_IRQ_CODE */ 255 case 0x14: /* SIR_FIQ_CODE */ 256 OMAP_RO_REG(addr); 257 break; 258 259 case 0x18: /* CONTROL_REG */ 260 if (bank_no != 0) 261 break; 262 if (value & 2) { 263 qemu_set_irq(s->parent_intr[1], 0); 264 s->new_agr[1] = ~0; 265 omap_inth_update(s, 1); 266 } 267 if (value & 1) { 268 qemu_set_irq(s->parent_intr[0], 0); 269 s->new_agr[0] = ~0; 270 omap_inth_update(s, 0); 271 } 272 return; 273 274 case 0x1c: /* ILR0 */ 275 case 0x20: /* ILR1 */ 276 case 0x24: /* ILR2 */ 277 case 0x28: /* ILR3 */ 278 case 0x2c: /* ILR4 */ 279 case 0x30: /* ILR5 */ 280 case 0x34: /* ILR6 */ 281 case 0x38: /* ILR7 */ 282 case 0x3c: /* ILR8 */ 283 case 0x40: /* ILR9 */ 284 case 0x44: /* ILR10 */ 285 case 0x48: /* ILR11 */ 286 case 0x4c: /* ILR12 */ 287 case 0x50: /* ILR13 */ 288 case 0x54: /* ILR14 */ 289 case 0x58: /* ILR15 */ 290 case 0x5c: /* ILR16 */ 291 case 0x60: /* ILR17 */ 292 case 0x64: /* ILR18 */ 293 case 0x68: /* ILR19 */ 294 case 0x6c: /* ILR20 */ 295 case 0x70: /* ILR21 */ 296 case 0x74: /* ILR22 */ 297 case 0x78: /* ILR23 */ 298 case 0x7c: /* ILR24 */ 299 case 0x80: /* ILR25 */ 300 case 0x84: /* ILR26 */ 301 case 0x88: /* ILR27 */ 302 case 0x8c: /* ILR28 */ 303 case 0x90: /* ILR29 */ 304 case 0x94: /* ILR30 */ 305 case 0x98: /* ILR31 */ 306 i = (offset - 0x1c) >> 2; 307 bank->priority[i] = (value >> 2) & 0x1f; 308 bank->sens_edge &= ~(1 << i); 309 bank->sens_edge |= ((value >> 1) & 1) << i; 310 bank->fiq &= ~(1 << i); 311 bank->fiq |= (value & 1) << i; 312 return; 313 314 case 0x9c: /* ISR */ 315 for (i = 0; i < 32; i ++) 316 if (value & (1 << i)) { 317 omap_set_intr(s, 32 * bank_no + i, 1); 318 return; 319 } 320 return; 321 } 322 OMAP_BAD_REG(addr); 323 } 324 325 static const MemoryRegionOps omap_inth_mem_ops = { 326 .read = omap_inth_read, 327 .write = omap_inth_write, 328 .endianness = DEVICE_NATIVE_ENDIAN, 329 .valid = { 330 .min_access_size = 4, 331 .max_access_size = 4, 332 }, 333 }; 334 335 static void omap_inth_reset(DeviceState *dev) 336 { 337 struct omap_intr_handler_s *s = OMAP_INTC(dev); 338 int i; 339 340 for (i = 0; i < s->nbanks; ++i){ 341 s->bank[i].irqs = 0x00000000; 342 s->bank[i].mask = 0xffffffff; 343 s->bank[i].sens_edge = 0x00000000; 344 s->bank[i].fiq = 0x00000000; 345 s->bank[i].inputs = 0x00000000; 346 s->bank[i].swi = 0x00000000; 347 memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority)); 348 349 if (s->level_only) 350 s->bank[i].sens_edge = 0xffffffff; 351 } 352 353 s->new_agr[0] = ~0; 354 s->new_agr[1] = ~0; 355 s->sir_intr[0] = 0; 356 s->sir_intr[1] = 0; 357 s->autoidle = 0; 358 s->mask = ~0; 359 360 qemu_set_irq(s->parent_intr[0], 0); 361 qemu_set_irq(s->parent_intr[1], 0); 362 } 363 364 static int omap_intc_init(SysBusDevice *sbd) 365 { 366 DeviceState *dev = DEVICE(sbd); 367 struct omap_intr_handler_s *s = OMAP_INTC(dev); 368 369 if (!s->iclk) { 370 hw_error("omap-intc: clk not connected\n"); 371 } 372 s->nbanks = 1; 373 sysbus_init_irq(sbd, &s->parent_intr[0]); 374 sysbus_init_irq(sbd, &s->parent_intr[1]); 375 qdev_init_gpio_in(dev, omap_set_intr, s->nbanks * 32); 376 memory_region_init_io(&s->mmio, OBJECT(s), &omap_inth_mem_ops, s, 377 "omap-intc", s->size); 378 sysbus_init_mmio(sbd, &s->mmio); 379 return 0; 380 } 381 382 static Property omap_intc_properties[] = { 383 DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100), 384 DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk), 385 DEFINE_PROP_END_OF_LIST(), 386 }; 387 388 static void omap_intc_class_init(ObjectClass *klass, void *data) 389 { 390 DeviceClass *dc = DEVICE_CLASS(klass); 391 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 392 393 k->init = omap_intc_init; 394 dc->reset = omap_inth_reset; 395 dc->props = omap_intc_properties; 396 /* Reason: pointer property "clk" */ 397 dc->cannot_instantiate_with_device_add_yet = true; 398 } 399 400 static const TypeInfo omap_intc_info = { 401 .name = "omap-intc", 402 .parent = TYPE_OMAP_INTC, 403 .class_init = omap_intc_class_init, 404 }; 405 406 static uint64_t omap2_inth_read(void *opaque, hwaddr addr, 407 unsigned size) 408 { 409 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; 410 int offset = addr; 411 int bank_no, line_no; 412 struct omap_intr_handler_bank_s *bank = NULL; 413 414 if ((offset & 0xf80) == 0x80) { 415 bank_no = (offset & 0x60) >> 5; 416 if (bank_no < s->nbanks) { 417 offset &= ~0x60; 418 bank = &s->bank[bank_no]; 419 } else { 420 OMAP_BAD_REG(addr); 421 return 0; 422 } 423 } 424 425 switch (offset) { 426 case 0x00: /* INTC_REVISION */ 427 return s->revision; 428 429 case 0x10: /* INTC_SYSCONFIG */ 430 return (s->autoidle >> 2) & 1; 431 432 case 0x14: /* INTC_SYSSTATUS */ 433 return 1; /* RESETDONE */ 434 435 case 0x40: /* INTC_SIR_IRQ */ 436 return s->sir_intr[0]; 437 438 case 0x44: /* INTC_SIR_FIQ */ 439 return s->sir_intr[1]; 440 441 case 0x48: /* INTC_CONTROL */ 442 return (!s->mask) << 2; /* GLOBALMASK */ 443 444 case 0x4c: /* INTC_PROTECTION */ 445 return 0; 446 447 case 0x50: /* INTC_IDLE */ 448 return s->autoidle & 3; 449 450 /* Per-bank registers */ 451 case 0x80: /* INTC_ITR */ 452 return bank->inputs; 453 454 case 0x84: /* INTC_MIR */ 455 return bank->mask; 456 457 case 0x88: /* INTC_MIR_CLEAR */ 458 case 0x8c: /* INTC_MIR_SET */ 459 return 0; 460 461 case 0x90: /* INTC_ISR_SET */ 462 return bank->swi; 463 464 case 0x94: /* INTC_ISR_CLEAR */ 465 return 0; 466 467 case 0x98: /* INTC_PENDING_IRQ */ 468 return bank->irqs & ~bank->mask & ~bank->fiq; 469 470 case 0x9c: /* INTC_PENDING_FIQ */ 471 return bank->irqs & ~bank->mask & bank->fiq; 472 473 /* Per-line registers */ 474 case 0x100 ... 0x300: /* INTC_ILR */ 475 bank_no = (offset - 0x100) >> 7; 476 if (bank_no > s->nbanks) 477 break; 478 bank = &s->bank[bank_no]; 479 line_no = (offset & 0x7f) >> 2; 480 return (bank->priority[line_no] << 2) | 481 ((bank->fiq >> line_no) & 1); 482 } 483 OMAP_BAD_REG(addr); 484 return 0; 485 } 486 487 static void omap2_inth_write(void *opaque, hwaddr addr, 488 uint64_t value, unsigned size) 489 { 490 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; 491 int offset = addr; 492 int bank_no, line_no; 493 struct omap_intr_handler_bank_s *bank = NULL; 494 495 if ((offset & 0xf80) == 0x80) { 496 bank_no = (offset & 0x60) >> 5; 497 if (bank_no < s->nbanks) { 498 offset &= ~0x60; 499 bank = &s->bank[bank_no]; 500 } else { 501 OMAP_BAD_REG(addr); 502 return; 503 } 504 } 505 506 switch (offset) { 507 case 0x10: /* INTC_SYSCONFIG */ 508 s->autoidle &= 4; 509 s->autoidle |= (value & 1) << 2; 510 if (value & 2) { /* SOFTRESET */ 511 omap_inth_reset(DEVICE(s)); 512 } 513 return; 514 515 case 0x48: /* INTC_CONTROL */ 516 s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */ 517 if (value & 2) { /* NEWFIQAGR */ 518 qemu_set_irq(s->parent_intr[1], 0); 519 s->new_agr[1] = ~0; 520 omap_inth_update(s, 1); 521 } 522 if (value & 1) { /* NEWIRQAGR */ 523 qemu_set_irq(s->parent_intr[0], 0); 524 s->new_agr[0] = ~0; 525 omap_inth_update(s, 0); 526 } 527 return; 528 529 case 0x4c: /* INTC_PROTECTION */ 530 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges 531 * for every register, see Chapter 3 and 4 for privileged mode. */ 532 if (value & 1) 533 fprintf(stderr, "%s: protection mode enable attempt\n", 534 __FUNCTION__); 535 return; 536 537 case 0x50: /* INTC_IDLE */ 538 s->autoidle &= ~3; 539 s->autoidle |= value & 3; 540 return; 541 542 /* Per-bank registers */ 543 case 0x84: /* INTC_MIR */ 544 bank->mask = value; 545 omap_inth_update(s, 0); 546 omap_inth_update(s, 1); 547 return; 548 549 case 0x88: /* INTC_MIR_CLEAR */ 550 bank->mask &= ~value; 551 omap_inth_update(s, 0); 552 omap_inth_update(s, 1); 553 return; 554 555 case 0x8c: /* INTC_MIR_SET */ 556 bank->mask |= value; 557 return; 558 559 case 0x90: /* INTC_ISR_SET */ 560 bank->irqs |= bank->swi |= value; 561 omap_inth_update(s, 0); 562 omap_inth_update(s, 1); 563 return; 564 565 case 0x94: /* INTC_ISR_CLEAR */ 566 bank->swi &= ~value; 567 bank->irqs = bank->swi & bank->inputs; 568 return; 569 570 /* Per-line registers */ 571 case 0x100 ... 0x300: /* INTC_ILR */ 572 bank_no = (offset - 0x100) >> 7; 573 if (bank_no > s->nbanks) 574 break; 575 bank = &s->bank[bank_no]; 576 line_no = (offset & 0x7f) >> 2; 577 bank->priority[line_no] = (value >> 2) & 0x3f; 578 bank->fiq &= ~(1 << line_no); 579 bank->fiq |= (value & 1) << line_no; 580 return; 581 582 case 0x00: /* INTC_REVISION */ 583 case 0x14: /* INTC_SYSSTATUS */ 584 case 0x40: /* INTC_SIR_IRQ */ 585 case 0x44: /* INTC_SIR_FIQ */ 586 case 0x80: /* INTC_ITR */ 587 case 0x98: /* INTC_PENDING_IRQ */ 588 case 0x9c: /* INTC_PENDING_FIQ */ 589 OMAP_RO_REG(addr); 590 return; 591 } 592 OMAP_BAD_REG(addr); 593 } 594 595 static const MemoryRegionOps omap2_inth_mem_ops = { 596 .read = omap2_inth_read, 597 .write = omap2_inth_write, 598 .endianness = DEVICE_NATIVE_ENDIAN, 599 .valid = { 600 .min_access_size = 4, 601 .max_access_size = 4, 602 }, 603 }; 604 605 static int omap2_intc_init(SysBusDevice *sbd) 606 { 607 DeviceState *dev = DEVICE(sbd); 608 struct omap_intr_handler_s *s = OMAP_INTC(dev); 609 610 if (!s->iclk) { 611 hw_error("omap2-intc: iclk not connected\n"); 612 } 613 if (!s->fclk) { 614 hw_error("omap2-intc: fclk not connected\n"); 615 } 616 s->level_only = 1; 617 s->nbanks = 3; 618 sysbus_init_irq(sbd, &s->parent_intr[0]); 619 sysbus_init_irq(sbd, &s->parent_intr[1]); 620 qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32); 621 memory_region_init_io(&s->mmio, OBJECT(s), &omap2_inth_mem_ops, s, 622 "omap2-intc", 0x1000); 623 sysbus_init_mmio(sbd, &s->mmio); 624 return 0; 625 } 626 627 static Property omap2_intc_properties[] = { 628 DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s, 629 revision, 0x21), 630 DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk), 631 DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk), 632 DEFINE_PROP_END_OF_LIST(), 633 }; 634 635 static void omap2_intc_class_init(ObjectClass *klass, void *data) 636 { 637 DeviceClass *dc = DEVICE_CLASS(klass); 638 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 639 640 k->init = omap2_intc_init; 641 dc->reset = omap_inth_reset; 642 dc->props = omap2_intc_properties; 643 /* Reason: pointer property "iclk", "fclk" */ 644 dc->cannot_instantiate_with_device_add_yet = true; 645 } 646 647 static const TypeInfo omap2_intc_info = { 648 .name = "omap2-intc", 649 .parent = TYPE_OMAP_INTC, 650 .class_init = omap2_intc_class_init, 651 }; 652 653 static const TypeInfo omap_intc_type_info = { 654 .name = TYPE_OMAP_INTC, 655 .parent = TYPE_SYS_BUS_DEVICE, 656 .instance_size = sizeof(struct omap_intr_handler_s), 657 .abstract = true, 658 }; 659 660 static void omap_intc_register_types(void) 661 { 662 type_register_static(&omap_intc_type_info); 663 type_register_static(&omap_intc_info); 664 type_register_static(&omap2_intc_info); 665 } 666 667 type_init(omap_intc_register_types) 668