1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Loongson IPI interrupt common support 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "hw/sysbus.h" 10 #include "hw/intc/loongson_ipi_common.h" 11 #include "hw/irq.h" 12 #include "qemu/log.h" 13 #include "migration/vmstate.h" 14 #include "trace.h" 15 16 MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, 17 unsigned size, MemTxAttrs attrs) 18 { 19 IPICore *s = opaque; 20 uint64_t ret = 0; 21 int index = 0; 22 23 addr &= 0xff; 24 switch (addr) { 25 case CORE_STATUS_OFF: 26 ret = s->status; 27 break; 28 case CORE_EN_OFF: 29 ret = s->en; 30 break; 31 case CORE_SET_OFF: 32 ret = 0; 33 break; 34 case CORE_CLEAR_OFF: 35 ret = 0; 36 break; 37 case CORE_BUF_20 ... CORE_BUF_38 + 4: 38 index = (addr - CORE_BUF_20) >> 2; 39 ret = s->buf[index]; 40 break; 41 default: 42 qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr); 43 break; 44 } 45 46 trace_loongson_ipi_read(size, (uint64_t)addr, ret); 47 *data = ret; 48 49 return MEMTX_OK; 50 } 51 52 static MemTxResult loongson_ipi_iocsr_readl(void *opaque, hwaddr addr, 53 uint64_t *data, unsigned size, 54 MemTxAttrs attrs) 55 { 56 LoongsonIPICommonState *ipi = opaque; 57 IPICore *s; 58 59 if (attrs.requester_id >= ipi->num_cpu) { 60 return MEMTX_DECODE_ERROR; 61 } 62 63 s = &ipi->cpu[attrs.requester_id]; 64 return loongson_ipi_core_readl(s, addr, data, size, attrs); 65 } 66 67 static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu, 68 uint64_t val, hwaddr addr, MemTxAttrs attrs) 69 { 70 LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); 71 int i, mask = 0, data = 0; 72 AddressSpace *iocsr_as = licc->get_iocsr_as(cpu); 73 74 if (!iocsr_as) { 75 return MEMTX_DECODE_ERROR; 76 } 77 78 /* 79 * bit 27-30 is mask for byte writing, 80 * if the mask is 0, we need not to do anything. 81 */ 82 if ((val >> 27) & 0xf) { 83 data = address_space_ldl_le(iocsr_as, addr, attrs, NULL); 84 for (i = 0; i < 4; i++) { 85 /* get mask for byte writing */ 86 if (val & (0x1 << (27 + i))) { 87 mask |= 0xff << (i * 8); 88 } 89 } 90 } 91 92 data &= mask; 93 data |= (val >> 32) & ~mask; 94 address_space_stl_le(iocsr_as, addr, data, attrs, NULL); 95 96 return MEMTX_OK; 97 } 98 99 static MemTxResult mail_send(LoongsonIPICommonState *ipi, 100 uint64_t val, MemTxAttrs attrs) 101 { 102 LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); 103 uint32_t cpuid; 104 hwaddr addr; 105 CPUState *cs; 106 107 cpuid = extract32(val, 16, 10); 108 cs = licc->cpu_by_arch_id(cpuid); 109 if (cs == NULL) { 110 return MEMTX_DECODE_ERROR; 111 } 112 113 /* override requester_id */ 114 addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); 115 attrs.requester_id = cs->cpu_index; 116 return send_ipi_data(ipi, cs, val, addr, attrs); 117 } 118 119 static MemTxResult any_send(LoongsonIPICommonState *ipi, 120 uint64_t val, MemTxAttrs attrs) 121 { 122 LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); 123 uint32_t cpuid; 124 hwaddr addr; 125 CPUState *cs; 126 127 cpuid = extract32(val, 16, 10); 128 cs = licc->cpu_by_arch_id(cpuid); 129 if (cs == NULL) { 130 return MEMTX_DECODE_ERROR; 131 } 132 133 /* override requester_id */ 134 addr = val & 0xffff; 135 attrs.requester_id = cs->cpu_index; 136 return send_ipi_data(ipi, cs, val, addr, attrs); 137 } 138 139 MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, 140 unsigned size, MemTxAttrs attrs) 141 { 142 IPICore *s = opaque; 143 LoongsonIPICommonState *ipi = s->ipi; 144 LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi); 145 int index = 0; 146 uint32_t cpuid; 147 uint8_t vector; 148 CPUState *cs; 149 150 addr &= 0xff; 151 trace_loongson_ipi_write(size, (uint64_t)addr, val); 152 switch (addr) { 153 case CORE_STATUS_OFF: 154 qemu_log_mask(LOG_GUEST_ERROR, "can not be written"); 155 break; 156 case CORE_EN_OFF: 157 s->en = val; 158 break; 159 case CORE_SET_OFF: 160 s->status |= val; 161 if (s->status != 0 && (s->status & s->en) != 0) { 162 qemu_irq_raise(s->irq); 163 } 164 break; 165 case CORE_CLEAR_OFF: 166 s->status &= ~val; 167 if (s->status == 0 && s->en != 0) { 168 qemu_irq_lower(s->irq); 169 } 170 break; 171 case CORE_BUF_20 ... CORE_BUF_38 + 4: 172 index = (addr - CORE_BUF_20) >> 2; 173 s->buf[index] = val; 174 break; 175 case IOCSR_IPI_SEND: 176 cpuid = extract32(val, 16, 10); 177 /* IPI status vector */ 178 vector = extract8(val, 0, 5); 179 cs = licc->cpu_by_arch_id(cpuid); 180 if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { 181 return MEMTX_DECODE_ERROR; 182 } 183 loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, 184 BIT(vector), 4, attrs); 185 break; 186 default: 187 qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); 188 break; 189 } 190 191 return MEMTX_OK; 192 } 193 194 static MemTxResult loongson_ipi_iocsr_writel(void *opaque, hwaddr addr, 195 uint64_t val, unsigned size, 196 MemTxAttrs attrs) 197 { 198 LoongsonIPICommonState *ipi = opaque; 199 IPICore *s; 200 201 if (attrs.requester_id >= ipi->num_cpu) { 202 return MEMTX_DECODE_ERROR; 203 } 204 205 s = &ipi->cpu[attrs.requester_id]; 206 return loongson_ipi_core_writel(s, addr, val, size, attrs); 207 } 208 209 static const MemoryRegionOps loongson_ipi_iocsr_ops = { 210 .read_with_attrs = loongson_ipi_iocsr_readl, 211 .write_with_attrs = loongson_ipi_iocsr_writel, 212 .impl.min_access_size = 4, 213 .impl.max_access_size = 4, 214 .valid.min_access_size = 4, 215 .valid.max_access_size = 8, 216 .endianness = DEVICE_LITTLE_ENDIAN, 217 }; 218 219 /* mail send and any send only support writeq */ 220 static MemTxResult loongson_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, 221 unsigned size, MemTxAttrs attrs) 222 { 223 LoongsonIPICommonState *ipi = opaque; 224 MemTxResult ret = MEMTX_OK; 225 226 addr &= 0xfff; 227 switch (addr) { 228 case MAIL_SEND_OFFSET: 229 ret = mail_send(ipi, val, attrs); 230 break; 231 case ANY_SEND_OFFSET: 232 ret = any_send(ipi, val, attrs); 233 break; 234 default: 235 break; 236 } 237 238 return ret; 239 } 240 241 static const MemoryRegionOps loongson_ipi64_ops = { 242 .write_with_attrs = loongson_ipi_writeq, 243 .impl.min_access_size = 8, 244 .impl.max_access_size = 8, 245 .valid.min_access_size = 8, 246 .valid.max_access_size = 8, 247 .endianness = DEVICE_LITTLE_ENDIAN, 248 }; 249 250 static void loongson_ipi_common_realize(DeviceState *dev, Error **errp) 251 { 252 LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); 253 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 254 255 memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), 256 &loongson_ipi_iocsr_ops, 257 s, "loongson_ipi_iocsr", 0x48); 258 259 /* loongson_ipi_iocsr performs re-entrant IO through ipi_send */ 260 s->ipi_iocsr_mem.disable_reentrancy_guard = true; 261 262 sysbus_init_mmio(sbd, &s->ipi_iocsr_mem); 263 264 memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev), 265 &loongson_ipi64_ops, 266 s, "loongson_ipi64_iocsr", 0x118); 267 sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem); 268 } 269 270 static void loongson_ipi_common_unrealize(DeviceState *dev) 271 { 272 LoongsonIPICommonState *s = LOONGSON_IPI_COMMON(dev); 273 274 g_free(s->cpu); 275 } 276 277 static const VMStateDescription vmstate_ipi_core = { 278 .name = "ipi-single", 279 .version_id = 2, 280 .minimum_version_id = 2, 281 .fields = (const VMStateField[]) { 282 VMSTATE_UINT32(status, IPICore), 283 VMSTATE_UINT32(en, IPICore), 284 VMSTATE_UINT32(set, IPICore), 285 VMSTATE_UINT32(clear, IPICore), 286 VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), 287 VMSTATE_END_OF_LIST() 288 } 289 }; 290 291 static const VMStateDescription vmstate_loongson_ipi_common = { 292 .name = "loongson_ipi", 293 .version_id = 2, 294 .minimum_version_id = 2, 295 .fields = (const VMStateField[]) { 296 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongsonIPICommonState, 297 num_cpu, vmstate_ipi_core, 298 IPICore), 299 VMSTATE_END_OF_LIST() 300 } 301 }; 302 303 static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) 304 { 305 DeviceClass *dc = DEVICE_CLASS(klass); 306 LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); 307 308 device_class_set_parent_realize(dc, loongson_ipi_common_realize, 309 &licc->parent_realize); 310 device_class_set_parent_unrealize(dc, loongson_ipi_common_unrealize, 311 &licc->parent_unrealize); 312 dc->vmsd = &vmstate_loongson_ipi_common; 313 } 314 315 static const TypeInfo loongarch_ipi_common_types[] = { 316 { 317 .name = TYPE_LOONGSON_IPI_COMMON, 318 .parent = TYPE_SYS_BUS_DEVICE, 319 .instance_size = sizeof(LoongsonIPICommonState), 320 .class_size = sizeof(LoongsonIPICommonClass), 321 .class_init = loongson_ipi_common_class_init, 322 .abstract = true, 323 } 324 }; 325 326 DEFINE_TYPES(loongarch_ipi_common_types) 327