1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Loongson 3A5000 ext interrupt controller emulation 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/module.h" 10 #include "qemu/log.h" 11 #include "qapi/error.h" 12 #include "hw/irq.h" 13 #include "hw/sysbus.h" 14 #include "hw/loongarch/virt.h" 15 #include "hw/qdev-properties.h" 16 #include "exec/address-spaces.h" 17 #include "hw/intc/loongarch_extioi.h" 18 #include "migration/vmstate.h" 19 #include "trace.h" 20 21 22 static void extioi_update_irq(LoongArchExtIOI *s, int irq, int level) 23 { 24 int ipnum, cpu, found, irq_index, irq_mask; 25 26 ipnum = s->sw_ipmap[irq / 32]; 27 cpu = s->sw_coremap[irq]; 28 irq_index = irq / 32; 29 irq_mask = 1 << (irq & 0x1f); 30 31 if (level) { 32 /* if not enable return false */ 33 if (((s->enable[irq_index]) & irq_mask) == 0) { 34 return; 35 } 36 s->cpu[cpu].coreisr[irq_index] |= irq_mask; 37 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS); 38 set_bit(irq, s->cpu[cpu].sw_isr[ipnum]); 39 if (found < EXTIOI_IRQS) { 40 /* other irq is handling, need not update parent irq level */ 41 return; 42 } 43 } else { 44 s->cpu[cpu].coreisr[irq_index] &= ~irq_mask; 45 clear_bit(irq, s->cpu[cpu].sw_isr[ipnum]); 46 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS); 47 if (found < EXTIOI_IRQS) { 48 /* other irq is handling, need not update parent irq level */ 49 return; 50 } 51 } 52 qemu_set_irq(s->cpu[cpu].parent_irq[ipnum], level); 53 } 54 55 static void extioi_setirq(void *opaque, int irq, int level) 56 { 57 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 58 trace_loongarch_extioi_setirq(irq, level); 59 if (level) { 60 /* 61 * s->isr should be used in vmstate structure, 62 * but it not support 'unsigned long', 63 * so we have to switch it. 64 */ 65 set_bit(irq, (unsigned long *)s->isr); 66 } else { 67 clear_bit(irq, (unsigned long *)s->isr); 68 } 69 extioi_update_irq(s, irq, level); 70 } 71 72 static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data, 73 unsigned size, MemTxAttrs attrs) 74 { 75 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 76 unsigned long offset = addr & 0xffff; 77 uint32_t index, cpu; 78 79 switch (offset) { 80 case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: 81 index = (offset - EXTIOI_NODETYPE_START) >> 2; 82 *data = s->nodetype[index]; 83 break; 84 case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: 85 index = (offset - EXTIOI_IPMAP_START) >> 2; 86 *data = s->ipmap[index]; 87 break; 88 case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: 89 index = (offset - EXTIOI_ENABLE_START) >> 2; 90 *data = s->enable[index]; 91 break; 92 case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: 93 index = (offset - EXTIOI_BOUNCE_START) >> 2; 94 *data = s->bounce[index]; 95 break; 96 case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: 97 index = (offset - EXTIOI_COREISR_START) >> 2; 98 /* using attrs to get current cpu index */ 99 cpu = attrs.requester_id; 100 *data = s->cpu[cpu].coreisr[index]; 101 break; 102 case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: 103 index = (offset - EXTIOI_COREMAP_START) >> 2; 104 *data = s->coremap[index]; 105 break; 106 default: 107 break; 108 } 109 110 trace_loongarch_extioi_readw(addr, *data); 111 return MEMTX_OK; 112 } 113 114 static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\ 115 uint32_t mask, int level) 116 { 117 uint32_t val; 118 int irq; 119 120 val = mask & s->isr[index]; 121 irq = ctz32(val); 122 while (irq != 32) { 123 /* 124 * enable bit change from 0 to 1, 125 * need to update irq by pending bits 126 */ 127 extioi_update_irq(s, irq + index * 32, level); 128 val &= ~(1 << irq); 129 irq = ctz32(val); 130 } 131 } 132 133 static inline void extioi_update_sw_coremap(LoongArchExtIOI *s, int irq, 134 uint64_t val, bool notify) 135 { 136 int i, cpu; 137 138 /* 139 * loongarch only support little endian, 140 * so we paresd the value with little endian. 141 */ 142 val = cpu_to_le64(val); 143 144 for (i = 0; i < 4; i++) { 145 cpu = val & 0xff; 146 cpu = ctz32(cpu); 147 cpu = (cpu >= 4) ? 0 : cpu; 148 val = val >> 8; 149 150 if (s->sw_coremap[irq + i] == cpu) { 151 continue; 152 } 153 154 if (notify && test_bit(irq, (unsigned long *)s->isr)) { 155 /* 156 * lower irq at old cpu and raise irq at new cpu 157 */ 158 extioi_update_irq(s, irq + i, 0); 159 s->sw_coremap[irq + i] = cpu; 160 extioi_update_irq(s, irq + i, 1); 161 } else { 162 s->sw_coremap[irq + i] = cpu; 163 } 164 } 165 } 166 167 static inline void extioi_update_sw_ipmap(LoongArchExtIOI *s, int index, 168 uint64_t val) 169 { 170 int i; 171 uint8_t ipnum; 172 173 /* 174 * loongarch only support little endian, 175 * so we paresd the value with little endian. 176 */ 177 val = cpu_to_le64(val); 178 for (i = 0; i < 4; i++) { 179 ipnum = val & 0xff; 180 ipnum = ctz32(ipnum); 181 ipnum = (ipnum >= 4) ? 0 : ipnum; 182 s->sw_ipmap[index * 4 + i] = ipnum; 183 val = val >> 8; 184 } 185 } 186 187 static MemTxResult extioi_writew(void *opaque, hwaddr addr, 188 uint64_t val, unsigned size, 189 MemTxAttrs attrs) 190 { 191 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 192 int cpu, index, old_data, irq; 193 uint32_t offset; 194 195 trace_loongarch_extioi_writew(addr, val); 196 offset = addr & 0xffff; 197 198 switch (offset) { 199 case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: 200 index = (offset - EXTIOI_NODETYPE_START) >> 2; 201 s->nodetype[index] = val; 202 break; 203 case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: 204 /* 205 * ipmap cannot be set at runtime, can be set only at the beginning 206 * of intr driver, need not update upper irq level 207 */ 208 index = (offset - EXTIOI_IPMAP_START) >> 2; 209 s->ipmap[index] = val; 210 extioi_update_sw_ipmap(s, index, val); 211 break; 212 case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: 213 index = (offset - EXTIOI_ENABLE_START) >> 2; 214 old_data = s->enable[index]; 215 s->enable[index] = val; 216 217 /* unmask irq */ 218 val = s->enable[index] & ~old_data; 219 extioi_enable_irq(s, index, val, 1); 220 221 /* mask irq */ 222 val = ~s->enable[index] & old_data; 223 extioi_enable_irq(s, index, val, 0); 224 break; 225 case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: 226 /* do not emulate hw bounced irq routing */ 227 index = (offset - EXTIOI_BOUNCE_START) >> 2; 228 s->bounce[index] = val; 229 break; 230 case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: 231 index = (offset - EXTIOI_COREISR_START) >> 2; 232 /* using attrs to get current cpu index */ 233 cpu = attrs.requester_id; 234 old_data = s->cpu[cpu].coreisr[index]; 235 s->cpu[cpu].coreisr[index] = old_data & ~val; 236 /* write 1 to clear interrupt */ 237 old_data &= val; 238 irq = ctz32(old_data); 239 while (irq != 32) { 240 extioi_update_irq(s, irq + index * 32, 0); 241 old_data &= ~(1 << irq); 242 irq = ctz32(old_data); 243 } 244 break; 245 case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: 246 irq = offset - EXTIOI_COREMAP_START; 247 index = irq / 4; 248 s->coremap[index] = val; 249 250 extioi_update_sw_coremap(s, irq, val, true); 251 break; 252 default: 253 break; 254 } 255 return MEMTX_OK; 256 } 257 258 static const MemoryRegionOps extioi_ops = { 259 .read_with_attrs = extioi_readw, 260 .write_with_attrs = extioi_writew, 261 .impl.min_access_size = 4, 262 .impl.max_access_size = 4, 263 .valid.min_access_size = 4, 264 .valid.max_access_size = 8, 265 .endianness = DEVICE_LITTLE_ENDIAN, 266 }; 267 268 static void loongarch_extioi_realize(DeviceState *dev, Error **errp) 269 { 270 LoongArchExtIOI *s = LOONGARCH_EXTIOI(dev); 271 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 272 int i, pin; 273 274 if (s->num_cpu == 0) { 275 error_setg(errp, "num-cpu must be at least 1"); 276 return; 277 } 278 279 for (i = 0; i < EXTIOI_IRQS; i++) { 280 sysbus_init_irq(sbd, &s->irq[i]); 281 } 282 283 qdev_init_gpio_in(dev, extioi_setirq, EXTIOI_IRQS); 284 memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops, 285 s, "extioi_system_mem", 0x900); 286 sysbus_init_mmio(sbd, &s->extioi_system_mem); 287 s->cpu = g_new0(ExtIOICore, s->num_cpu); 288 if (s->cpu == NULL) { 289 error_setg(errp, "Memory allocation for ExtIOICore faile"); 290 return; 291 } 292 293 for (i = 0; i < s->num_cpu; i++) { 294 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 295 qdev_init_gpio_out(dev, &s->cpu[i].parent_irq[pin], 1); 296 } 297 } 298 } 299 300 static void loongarch_extioi_finalize(Object *obj) 301 { 302 LoongArchExtIOI *s = LOONGARCH_EXTIOI(obj); 303 304 g_free(s->cpu); 305 } 306 307 static int vmstate_extioi_post_load(void *opaque, int version_id) 308 { 309 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 310 int i, start_irq; 311 312 for (i = 0; i < (EXTIOI_IRQS / 4); i++) { 313 start_irq = i * 4; 314 extioi_update_sw_coremap(s, start_irq, s->coremap[i], false); 315 } 316 317 for (i = 0; i < (EXTIOI_IRQS_IPMAP_SIZE / 4); i++) { 318 extioi_update_sw_ipmap(s, i, s->ipmap[i]); 319 } 320 321 return 0; 322 } 323 324 static const VMStateDescription vmstate_extioi_core = { 325 .name = "extioi-core", 326 .version_id = 1, 327 .minimum_version_id = 1, 328 .fields = (const VMStateField[]) { 329 VMSTATE_UINT32_ARRAY(coreisr, ExtIOICore, EXTIOI_IRQS_GROUP_COUNT), 330 VMSTATE_END_OF_LIST() 331 } 332 }; 333 334 static const VMStateDescription vmstate_loongarch_extioi = { 335 .name = TYPE_LOONGARCH_EXTIOI, 336 .version_id = 2, 337 .minimum_version_id = 2, 338 .post_load = vmstate_extioi_post_load, 339 .fields = (const VMStateField[]) { 340 VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT), 341 VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI, 342 EXTIOI_IRQS_NODETYPE_COUNT / 2), 343 VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32), 344 VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32), 345 VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4), 346 VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4), 347 348 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu, 349 vmstate_extioi_core, ExtIOICore), 350 VMSTATE_END_OF_LIST() 351 } 352 }; 353 354 static Property extioi_properties[] = { 355 DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1), 356 DEFINE_PROP_END_OF_LIST(), 357 }; 358 359 static void loongarch_extioi_class_init(ObjectClass *klass, void *data) 360 { 361 DeviceClass *dc = DEVICE_CLASS(klass); 362 363 dc->realize = loongarch_extioi_realize; 364 device_class_set_props(dc, extioi_properties); 365 dc->vmsd = &vmstate_loongarch_extioi; 366 } 367 368 static const TypeInfo loongarch_extioi_info = { 369 .name = TYPE_LOONGARCH_EXTIOI, 370 .parent = TYPE_SYS_BUS_DEVICE, 371 .instance_size = sizeof(struct LoongArchExtIOI), 372 .class_init = loongarch_extioi_class_init, 373 .instance_finalize = loongarch_extioi_finalize, 374 }; 375 376 static void loongarch_extioi_register_types(void) 377 { 378 type_register_static(&loongarch_extioi_info); 379 } 380 381 type_init(loongarch_extioi_register_types) 382