1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Loongson 3A5000 ext interrupt controller emulation 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/module.h" 10 #include "qemu/log.h" 11 #include "qapi/error.h" 12 #include "hw/irq.h" 13 #include "hw/sysbus.h" 14 #include "hw/loongarch/virt.h" 15 #include "hw/qdev-properties.h" 16 #include "exec/address-spaces.h" 17 #include "hw/intc/loongarch_extioi.h" 18 #include "migration/vmstate.h" 19 #include "trace.h" 20 21 22 static void extioi_update_irq(LoongArchExtIOI *s, int irq, int level) 23 { 24 int ipnum, cpu, found, irq_index, irq_mask; 25 26 ipnum = s->sw_ipmap[irq / 32]; 27 cpu = s->sw_coremap[irq]; 28 irq_index = irq / 32; 29 irq_mask = 1 << (irq & 0x1f); 30 31 if (level) { 32 /* if not enable return false */ 33 if (((s->enable[irq_index]) & irq_mask) == 0) { 34 return; 35 } 36 s->cpu[cpu].coreisr[irq_index] |= irq_mask; 37 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS); 38 set_bit(irq, s->cpu[cpu].sw_isr[ipnum]); 39 if (found < EXTIOI_IRQS) { 40 /* other irq is handling, need not update parent irq level */ 41 return; 42 } 43 } else { 44 s->cpu[cpu].coreisr[irq_index] &= ~irq_mask; 45 clear_bit(irq, s->cpu[cpu].sw_isr[ipnum]); 46 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS); 47 if (found < EXTIOI_IRQS) { 48 /* other irq is handling, need not update parent irq level */ 49 return; 50 } 51 } 52 qemu_set_irq(s->cpu[cpu].parent_irq[ipnum], level); 53 } 54 55 static void extioi_setirq(void *opaque, int irq, int level) 56 { 57 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 58 trace_loongarch_extioi_setirq(irq, level); 59 if (level) { 60 set_bit32(irq, s->isr); 61 } else { 62 clear_bit32(irq, s->isr); 63 } 64 extioi_update_irq(s, irq, level); 65 } 66 67 static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data, 68 unsigned size, MemTxAttrs attrs) 69 { 70 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 71 unsigned long offset = addr & 0xffff; 72 uint32_t index, cpu; 73 74 switch (offset) { 75 case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: 76 index = (offset - EXTIOI_NODETYPE_START) >> 2; 77 *data = s->nodetype[index]; 78 break; 79 case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: 80 index = (offset - EXTIOI_IPMAP_START) >> 2; 81 *data = s->ipmap[index]; 82 break; 83 case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: 84 index = (offset - EXTIOI_ENABLE_START) >> 2; 85 *data = s->enable[index]; 86 break; 87 case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: 88 index = (offset - EXTIOI_BOUNCE_START) >> 2; 89 *data = s->bounce[index]; 90 break; 91 case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: 92 index = (offset - EXTIOI_COREISR_START) >> 2; 93 /* using attrs to get current cpu index */ 94 cpu = attrs.requester_id; 95 *data = s->cpu[cpu].coreisr[index]; 96 break; 97 case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: 98 index = (offset - EXTIOI_COREMAP_START) >> 2; 99 *data = s->coremap[index]; 100 break; 101 default: 102 break; 103 } 104 105 trace_loongarch_extioi_readw(addr, *data); 106 return MEMTX_OK; 107 } 108 109 static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\ 110 uint32_t mask, int level) 111 { 112 uint32_t val; 113 int irq; 114 115 val = mask & s->isr[index]; 116 irq = ctz32(val); 117 while (irq != 32) { 118 /* 119 * enable bit change from 0 to 1, 120 * need to update irq by pending bits 121 */ 122 extioi_update_irq(s, irq + index * 32, level); 123 val &= ~(1 << irq); 124 irq = ctz32(val); 125 } 126 } 127 128 static inline void extioi_update_sw_coremap(LoongArchExtIOI *s, int irq, 129 uint64_t val, bool notify) 130 { 131 int i, cpu; 132 133 /* 134 * loongarch only support little endian, 135 * so we paresd the value with little endian. 136 */ 137 val = cpu_to_le64(val); 138 139 for (i = 0; i < 4; i++) { 140 cpu = val & 0xff; 141 val = val >> 8; 142 143 if (!(s->status & BIT(EXTIOI_ENABLE_CPU_ENCODE))) { 144 cpu = ctz32(cpu); 145 cpu = (cpu >= 4) ? 0 : cpu; 146 } 147 148 if (s->sw_coremap[irq + i] == cpu) { 149 continue; 150 } 151 152 if (notify && test_bit32(irq + i, s->isr)) { 153 /* 154 * lower irq at old cpu and raise irq at new cpu 155 */ 156 extioi_update_irq(s, irq + i, 0); 157 s->sw_coremap[irq + i] = cpu; 158 extioi_update_irq(s, irq + i, 1); 159 } else { 160 s->sw_coremap[irq + i] = cpu; 161 } 162 } 163 } 164 165 static inline void extioi_update_sw_ipmap(LoongArchExtIOI *s, int index, 166 uint64_t val) 167 { 168 int i; 169 uint8_t ipnum; 170 171 /* 172 * loongarch only support little endian, 173 * so we paresd the value with little endian. 174 */ 175 val = cpu_to_le64(val); 176 for (i = 0; i < 4; i++) { 177 ipnum = val & 0xff; 178 ipnum = ctz32(ipnum); 179 ipnum = (ipnum >= 4) ? 0 : ipnum; 180 s->sw_ipmap[index * 4 + i] = ipnum; 181 val = val >> 8; 182 } 183 } 184 185 static MemTxResult extioi_writew(void *opaque, hwaddr addr, 186 uint64_t val, unsigned size, 187 MemTxAttrs attrs) 188 { 189 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 190 int cpu, index, old_data, irq; 191 uint32_t offset; 192 193 trace_loongarch_extioi_writew(addr, val); 194 offset = addr & 0xffff; 195 196 switch (offset) { 197 case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: 198 index = (offset - EXTIOI_NODETYPE_START) >> 2; 199 s->nodetype[index] = val; 200 break; 201 case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: 202 /* 203 * ipmap cannot be set at runtime, can be set only at the beginning 204 * of intr driver, need not update upper irq level 205 */ 206 index = (offset - EXTIOI_IPMAP_START) >> 2; 207 s->ipmap[index] = val; 208 extioi_update_sw_ipmap(s, index, val); 209 break; 210 case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: 211 index = (offset - EXTIOI_ENABLE_START) >> 2; 212 old_data = s->enable[index]; 213 s->enable[index] = val; 214 215 /* unmask irq */ 216 val = s->enable[index] & ~old_data; 217 extioi_enable_irq(s, index, val, 1); 218 219 /* mask irq */ 220 val = ~s->enable[index] & old_data; 221 extioi_enable_irq(s, index, val, 0); 222 break; 223 case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: 224 /* do not emulate hw bounced irq routing */ 225 index = (offset - EXTIOI_BOUNCE_START) >> 2; 226 s->bounce[index] = val; 227 break; 228 case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: 229 index = (offset - EXTIOI_COREISR_START) >> 2; 230 /* using attrs to get current cpu index */ 231 cpu = attrs.requester_id; 232 old_data = s->cpu[cpu].coreisr[index]; 233 s->cpu[cpu].coreisr[index] = old_data & ~val; 234 /* write 1 to clear interrupt */ 235 old_data &= val; 236 irq = ctz32(old_data); 237 while (irq != 32) { 238 extioi_update_irq(s, irq + index * 32, 0); 239 old_data &= ~(1 << irq); 240 irq = ctz32(old_data); 241 } 242 break; 243 case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: 244 irq = offset - EXTIOI_COREMAP_START; 245 index = irq / 4; 246 s->coremap[index] = val; 247 248 extioi_update_sw_coremap(s, irq, val, true); 249 break; 250 default: 251 break; 252 } 253 return MEMTX_OK; 254 } 255 256 static const MemoryRegionOps extioi_ops = { 257 .read_with_attrs = extioi_readw, 258 .write_with_attrs = extioi_writew, 259 .impl.min_access_size = 4, 260 .impl.max_access_size = 4, 261 .valid.min_access_size = 4, 262 .valid.max_access_size = 8, 263 .endianness = DEVICE_LITTLE_ENDIAN, 264 }; 265 266 static MemTxResult extioi_virt_readw(void *opaque, hwaddr addr, uint64_t *data, 267 unsigned size, MemTxAttrs attrs) 268 { 269 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 270 271 switch (addr) { 272 case EXTIOI_VIRT_FEATURES: 273 *data = s->features; 274 break; 275 case EXTIOI_VIRT_CONFIG: 276 *data = s->status; 277 break; 278 default: 279 g_assert_not_reached(); 280 } 281 282 return MEMTX_OK; 283 } 284 285 static MemTxResult extioi_virt_writew(void *opaque, hwaddr addr, 286 uint64_t val, unsigned size, 287 MemTxAttrs attrs) 288 { 289 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 290 291 switch (addr) { 292 case EXTIOI_VIRT_FEATURES: 293 return MEMTX_ACCESS_ERROR; 294 295 case EXTIOI_VIRT_CONFIG: 296 /* 297 * extioi features can only be set at disabled status 298 */ 299 if ((s->status & BIT(EXTIOI_ENABLE)) && val) { 300 return MEMTX_ACCESS_ERROR; 301 } 302 303 s->status = val & s->features; 304 break; 305 default: 306 g_assert_not_reached(); 307 } 308 return MEMTX_OK; 309 } 310 311 static const MemoryRegionOps extioi_virt_ops = { 312 .read_with_attrs = extioi_virt_readw, 313 .write_with_attrs = extioi_virt_writew, 314 .impl.min_access_size = 4, 315 .impl.max_access_size = 4, 316 .valid.min_access_size = 4, 317 .valid.max_access_size = 8, 318 .endianness = DEVICE_LITTLE_ENDIAN, 319 }; 320 321 static void loongarch_extioi_common_realize(DeviceState *dev, Error **errp) 322 { 323 LoongArchExtIOICommonState *s = (LoongArchExtIOICommonState *)dev; 324 325 if (s->num_cpu == 0) { 326 error_setg(errp, "num-cpu must be at least 1"); 327 return; 328 } 329 } 330 331 static void loongarch_extioi_realize(DeviceState *dev, Error **errp) 332 { 333 LoongArchExtIOI *s = LOONGARCH_EXTIOI(dev); 334 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 335 Error *local_err = NULL; 336 int i, pin; 337 338 loongarch_extioi_common_realize(dev, &local_err); 339 if (local_err) { 340 error_propagate(errp, local_err); 341 return; 342 } 343 344 for (i = 0; i < EXTIOI_IRQS; i++) { 345 sysbus_init_irq(sbd, &s->irq[i]); 346 } 347 348 qdev_init_gpio_in(dev, extioi_setirq, EXTIOI_IRQS); 349 memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops, 350 s, "extioi_system_mem", 0x900); 351 sysbus_init_mmio(sbd, &s->extioi_system_mem); 352 353 if (s->features & BIT(EXTIOI_HAS_VIRT_EXTENSION)) { 354 memory_region_init_io(&s->virt_extend, OBJECT(s), &extioi_virt_ops, 355 s, "extioi_virt", EXTIOI_VIRT_SIZE); 356 sysbus_init_mmio(sbd, &s->virt_extend); 357 s->features |= EXTIOI_VIRT_HAS_FEATURES; 358 } else { 359 s->status |= BIT(EXTIOI_ENABLE); 360 } 361 362 s->cpu = g_new0(ExtIOICore, s->num_cpu); 363 if (s->cpu == NULL) { 364 error_setg(errp, "Memory allocation for ExtIOICore faile"); 365 return; 366 } 367 368 for (i = 0; i < s->num_cpu; i++) { 369 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 370 qdev_init_gpio_out(dev, &s->cpu[i].parent_irq[pin], 1); 371 } 372 } 373 } 374 375 static void loongarch_extioi_unrealize(DeviceState *dev) 376 { 377 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI(dev); 378 379 g_free(s->cpu); 380 } 381 382 static void loongarch_extioi_reset(DeviceState *d) 383 { 384 LoongArchExtIOI *s = LOONGARCH_EXTIOI(d); 385 386 s->status = 0; 387 } 388 389 static int vmstate_extioi_post_load(void *opaque, int version_id) 390 { 391 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 392 int i, start_irq; 393 394 for (i = 0; i < (EXTIOI_IRQS / 4); i++) { 395 start_irq = i * 4; 396 extioi_update_sw_coremap(s, start_irq, s->coremap[i], false); 397 } 398 399 for (i = 0; i < (EXTIOI_IRQS_IPMAP_SIZE / 4); i++) { 400 extioi_update_sw_ipmap(s, i, s->ipmap[i]); 401 } 402 403 return 0; 404 } 405 406 static int loongarch_extioi_common_post_load(void *opaque, int version_id) 407 { 408 return vmstate_extioi_post_load(opaque, version_id); 409 } 410 411 static const VMStateDescription vmstate_extioi_core = { 412 .name = "extioi-core", 413 .version_id = 1, 414 .minimum_version_id = 1, 415 .fields = (const VMStateField[]) { 416 VMSTATE_UINT32_ARRAY(coreisr, ExtIOICore, EXTIOI_IRQS_GROUP_COUNT), 417 VMSTATE_END_OF_LIST() 418 } 419 }; 420 421 static const VMStateDescription vmstate_loongarch_extioi = { 422 .name = "loongarch.extioi", 423 .version_id = 3, 424 .minimum_version_id = 3, 425 .post_load = loongarch_extioi_common_post_load, 426 .fields = (const VMStateField[]) { 427 VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOICommonState, 428 EXTIOI_IRQS_GROUP_COUNT), 429 VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOICommonState, 430 EXTIOI_IRQS_NODETYPE_COUNT / 2), 431 VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOICommonState, 432 EXTIOI_IRQS / 32), 433 VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOICommonState, 434 EXTIOI_IRQS / 32), 435 VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOICommonState, 436 EXTIOI_IRQS_IPMAP_SIZE / 4), 437 VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOICommonState, 438 EXTIOI_IRQS / 4), 439 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOICommonState, 440 num_cpu, vmstate_extioi_core, ExtIOICore), 441 VMSTATE_UINT32(features, LoongArchExtIOICommonState), 442 VMSTATE_UINT32(status, LoongArchExtIOICommonState), 443 VMSTATE_END_OF_LIST() 444 } 445 }; 446 447 static const Property extioi_properties[] = { 448 DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOICommonState, num_cpu, 1), 449 DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState, 450 features, EXTIOI_HAS_VIRT_EXTENSION, 0), 451 DEFINE_PROP_END_OF_LIST(), 452 }; 453 454 static void loongarch_extioi_class_init(ObjectClass *klass, void *data) 455 { 456 DeviceClass *dc = DEVICE_CLASS(klass); 457 458 dc->realize = loongarch_extioi_realize; 459 dc->unrealize = loongarch_extioi_unrealize; 460 device_class_set_legacy_reset(dc, loongarch_extioi_reset); 461 device_class_set_props(dc, extioi_properties); 462 dc->vmsd = &vmstate_loongarch_extioi; 463 } 464 465 static const TypeInfo loongarch_extioi_info = { 466 .name = TYPE_LOONGARCH_EXTIOI, 467 .parent = TYPE_SYS_BUS_DEVICE, 468 .instance_size = sizeof(struct LoongArchExtIOI), 469 .class_init = loongarch_extioi_class_init, 470 }; 471 472 static void loongarch_extioi_register_types(void) 473 { 474 type_register_static(&loongarch_extioi_info); 475 } 476 477 type_init(loongarch_extioi_register_types) 478