1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Loongson 3A5000 ext interrupt controller emulation 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/module.h" 10 #include "qemu/log.h" 11 #include "qapi/error.h" 12 #include "hw/irq.h" 13 #include "hw/sysbus.h" 14 #include "hw/loongarch/virt.h" 15 #include "hw/qdev-properties.h" 16 #include "exec/address-spaces.h" 17 #include "hw/intc/loongarch_extioi.h" 18 #include "migration/vmstate.h" 19 #include "trace.h" 20 21 22 static void extioi_update_irq(LoongArchExtIOI *s, int irq, int level) 23 { 24 int ipnum, cpu, found, irq_index, irq_mask; 25 26 ipnum = s->sw_ipmap[irq / 32]; 27 cpu = s->sw_coremap[irq]; 28 irq_index = irq / 32; 29 irq_mask = 1 << (irq & 0x1f); 30 31 if (level) { 32 /* if not enable return false */ 33 if (((s->enable[irq_index]) & irq_mask) == 0) { 34 return; 35 } 36 s->cpu[cpu].coreisr[irq_index] |= irq_mask; 37 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS); 38 set_bit(irq, s->cpu[cpu].sw_isr[ipnum]); 39 if (found < EXTIOI_IRQS) { 40 /* other irq is handling, need not update parent irq level */ 41 return; 42 } 43 } else { 44 s->cpu[cpu].coreisr[irq_index] &= ~irq_mask; 45 clear_bit(irq, s->cpu[cpu].sw_isr[ipnum]); 46 found = find_first_bit(s->cpu[cpu].sw_isr[ipnum], EXTIOI_IRQS); 47 if (found < EXTIOI_IRQS) { 48 /* other irq is handling, need not update parent irq level */ 49 return; 50 } 51 } 52 qemu_set_irq(s->cpu[cpu].parent_irq[ipnum], level); 53 } 54 55 static void extioi_setirq(void *opaque, int irq, int level) 56 { 57 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 58 trace_loongarch_extioi_setirq(irq, level); 59 if (level) { 60 /* 61 * s->isr should be used in vmstate structure, 62 * but it not support 'unsigned long', 63 * so we have to switch it. 64 */ 65 set_bit(irq, (unsigned long *)s->isr); 66 } else { 67 clear_bit(irq, (unsigned long *)s->isr); 68 } 69 extioi_update_irq(s, irq, level); 70 } 71 72 static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data, 73 unsigned size, MemTxAttrs attrs) 74 { 75 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 76 unsigned long offset = addr & 0xffff; 77 uint32_t index, cpu; 78 79 switch (offset) { 80 case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: 81 index = (offset - EXTIOI_NODETYPE_START) >> 2; 82 *data = s->nodetype[index]; 83 break; 84 case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: 85 index = (offset - EXTIOI_IPMAP_START) >> 2; 86 *data = s->ipmap[index]; 87 break; 88 case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: 89 index = (offset - EXTIOI_ENABLE_START) >> 2; 90 *data = s->enable[index]; 91 break; 92 case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: 93 index = (offset - EXTIOI_BOUNCE_START) >> 2; 94 *data = s->bounce[index]; 95 break; 96 case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: 97 index = (offset - EXTIOI_COREISR_START) >> 2; 98 /* using attrs to get current cpu index */ 99 cpu = attrs.requester_id; 100 *data = s->cpu[cpu].coreisr[index]; 101 break; 102 case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: 103 index = (offset - EXTIOI_COREMAP_START) >> 2; 104 *data = s->coremap[index]; 105 break; 106 default: 107 break; 108 } 109 110 trace_loongarch_extioi_readw(addr, *data); 111 return MEMTX_OK; 112 } 113 114 static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\ 115 uint32_t mask, int level) 116 { 117 uint32_t val; 118 int irq; 119 120 val = mask & s->isr[index]; 121 irq = ctz32(val); 122 while (irq != 32) { 123 /* 124 * enable bit change from 0 to 1, 125 * need to update irq by pending bits 126 */ 127 extioi_update_irq(s, irq + index * 32, level); 128 val &= ~(1 << irq); 129 irq = ctz32(val); 130 } 131 } 132 133 static MemTxResult extioi_writew(void *opaque, hwaddr addr, 134 uint64_t val, unsigned size, 135 MemTxAttrs attrs) 136 { 137 LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); 138 int i, cpu, index, old_data, irq; 139 uint32_t offset; 140 141 trace_loongarch_extioi_writew(addr, val); 142 offset = addr & 0xffff; 143 144 switch (offset) { 145 case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: 146 index = (offset - EXTIOI_NODETYPE_START) >> 2; 147 s->nodetype[index] = val; 148 break; 149 case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: 150 /* 151 * ipmap cannot be set at runtime, can be set only at the beginning 152 * of intr driver, need not update upper irq level 153 */ 154 index = (offset - EXTIOI_IPMAP_START) >> 2; 155 s->ipmap[index] = val; 156 /* 157 * loongarch only support little endian, 158 * so we paresd the value with little endian. 159 */ 160 val = cpu_to_le64(val); 161 for (i = 0; i < 4; i++) { 162 uint8_t ipnum; 163 ipnum = val & 0xff; 164 ipnum = ctz32(ipnum); 165 ipnum = (ipnum >= 4) ? 0 : ipnum; 166 s->sw_ipmap[index * 4 + i] = ipnum; 167 val = val >> 8; 168 } 169 170 break; 171 case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: 172 index = (offset - EXTIOI_ENABLE_START) >> 2; 173 old_data = s->enable[index]; 174 s->enable[index] = val; 175 176 /* unmask irq */ 177 val = s->enable[index] & ~old_data; 178 extioi_enable_irq(s, index, val, 1); 179 180 /* mask irq */ 181 val = ~s->enable[index] & old_data; 182 extioi_enable_irq(s, index, val, 0); 183 break; 184 case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: 185 /* do not emulate hw bounced irq routing */ 186 index = (offset - EXTIOI_BOUNCE_START) >> 2; 187 s->bounce[index] = val; 188 break; 189 case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: 190 index = (offset - EXTIOI_COREISR_START) >> 2; 191 /* using attrs to get current cpu index */ 192 cpu = attrs.requester_id; 193 old_data = s->cpu[cpu].coreisr[index]; 194 s->cpu[cpu].coreisr[index] = old_data & ~val; 195 /* write 1 to clear interrupt */ 196 old_data &= val; 197 irq = ctz32(old_data); 198 while (irq != 32) { 199 extioi_update_irq(s, irq + index * 32, 0); 200 old_data &= ~(1 << irq); 201 irq = ctz32(old_data); 202 } 203 break; 204 case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: 205 irq = offset - EXTIOI_COREMAP_START; 206 index = irq / 4; 207 s->coremap[index] = val; 208 /* 209 * loongarch only support little endian, 210 * so we paresd the value with little endian. 211 */ 212 val = cpu_to_le64(val); 213 214 for (i = 0; i < 4; i++) { 215 cpu = val & 0xff; 216 cpu = ctz32(cpu); 217 cpu = (cpu >= 4) ? 0 : cpu; 218 val = val >> 8; 219 220 if (s->sw_coremap[irq + i] == cpu) { 221 continue; 222 } 223 224 if (test_bit(irq, (unsigned long *)s->isr)) { 225 /* 226 * lower irq at old cpu and raise irq at new cpu 227 */ 228 extioi_update_irq(s, irq + i, 0); 229 s->sw_coremap[irq + i] = cpu; 230 extioi_update_irq(s, irq + i, 1); 231 } else { 232 s->sw_coremap[irq + i] = cpu; 233 } 234 } 235 break; 236 default: 237 break; 238 } 239 return MEMTX_OK; 240 } 241 242 static const MemoryRegionOps extioi_ops = { 243 .read_with_attrs = extioi_readw, 244 .write_with_attrs = extioi_writew, 245 .impl.min_access_size = 4, 246 .impl.max_access_size = 4, 247 .valid.min_access_size = 4, 248 .valid.max_access_size = 8, 249 .endianness = DEVICE_LITTLE_ENDIAN, 250 }; 251 252 static void loongarch_extioi_realize(DeviceState *dev, Error **errp) 253 { 254 LoongArchExtIOI *s = LOONGARCH_EXTIOI(dev); 255 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 256 int i, pin; 257 258 if (s->num_cpu == 0) { 259 error_setg(errp, "num-cpu must be at least 1"); 260 return; 261 } 262 263 for (i = 0; i < EXTIOI_IRQS; i++) { 264 sysbus_init_irq(sbd, &s->irq[i]); 265 } 266 267 qdev_init_gpio_in(dev, extioi_setirq, EXTIOI_IRQS); 268 memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops, 269 s, "extioi_system_mem", 0x900); 270 sysbus_init_mmio(sbd, &s->extioi_system_mem); 271 s->cpu = g_new0(ExtIOICore, s->num_cpu); 272 if (s->cpu == NULL) { 273 error_setg(errp, "Memory allocation for ExtIOICore faile"); 274 return; 275 } 276 277 for (i = 0; i < s->num_cpu; i++) { 278 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 279 qdev_init_gpio_out(dev, &s->cpu[i].parent_irq[pin], 1); 280 } 281 } 282 } 283 284 static void loongarch_extioi_finalize(Object *obj) 285 { 286 LoongArchExtIOI *s = LOONGARCH_EXTIOI(obj); 287 288 g_free(s->cpu); 289 } 290 291 static const VMStateDescription vmstate_extioi_core = { 292 .name = "extioi-core", 293 .version_id = 1, 294 .minimum_version_id = 1, 295 .fields = (const VMStateField[]) { 296 VMSTATE_UINT32_ARRAY(coreisr, ExtIOICore, EXTIOI_IRQS_GROUP_COUNT), 297 VMSTATE_END_OF_LIST() 298 } 299 }; 300 301 static const VMStateDescription vmstate_loongarch_extioi = { 302 .name = TYPE_LOONGARCH_EXTIOI, 303 .version_id = 2, 304 .minimum_version_id = 2, 305 .fields = (const VMStateField[]) { 306 VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT), 307 VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI, 308 EXTIOI_IRQS_NODETYPE_COUNT / 2), 309 VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32), 310 VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32), 311 VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4), 312 VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4), 313 VMSTATE_UINT8_ARRAY(sw_ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE), 314 VMSTATE_UINT8_ARRAY(sw_coremap, LoongArchExtIOI, EXTIOI_IRQS), 315 316 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu, 317 vmstate_extioi_core, ExtIOICore), 318 VMSTATE_END_OF_LIST() 319 } 320 }; 321 322 static Property extioi_properties[] = { 323 DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1), 324 DEFINE_PROP_END_OF_LIST(), 325 }; 326 327 static void loongarch_extioi_class_init(ObjectClass *klass, void *data) 328 { 329 DeviceClass *dc = DEVICE_CLASS(klass); 330 331 dc->realize = loongarch_extioi_realize; 332 device_class_set_props(dc, extioi_properties); 333 dc->vmsd = &vmstate_loongarch_extioi; 334 } 335 336 static const TypeInfo loongarch_extioi_info = { 337 .name = TYPE_LOONGARCH_EXTIOI, 338 .parent = TYPE_SYS_BUS_DEVICE, 339 .instance_size = sizeof(struct LoongArchExtIOI), 340 .class_init = loongarch_extioi_class_init, 341 .instance_finalize = loongarch_extioi_finalize, 342 }; 343 344 static void loongarch_extioi_register_types(void) 345 { 346 type_register_static(&loongarch_extioi_info); 347 } 348 349 type_init(loongarch_extioi_register_types) 350