1 /* 2 * IOAPIC emulation logic - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * Copyright (c) 2009 Xiantao Zhang, Intel 6 * Copyright (c) 2011 Jan Kiszka, Siemens AG 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "monitor/monitor.h" 25 #include "hw/i386/ioapic.h" 26 #include "hw/i386/ioapic_internal.h" 27 #include "hw/sysbus.h" 28 29 /* ioapic_no count start from 0 to MAX_IOAPICS, 30 * remove as static variable from ioapic_common_init. 31 * now as a global variable, let child to increase the counter 32 * then we can drop the 'instance_no' argument 33 * and convert to our QOM's realize function 34 */ 35 int ioapic_no; 36 37 static void ioapic_irr_dump(Monitor *mon, const char *name, uint32_t bitmap) 38 { 39 int i; 40 41 monitor_printf(mon, "%-10s ", name); 42 if (bitmap == 0) { 43 monitor_printf(mon, "(none)\n"); 44 return; 45 } 46 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 47 if (bitmap & (1 << i)) { 48 monitor_printf(mon, "%-2u ", i); 49 } 50 } 51 monitor_printf(mon, "\n"); 52 } 53 54 void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s) 55 { 56 static const char *delm_str[] = { 57 "fixed", "lowest", "SMI", "...", "NMI", "INIT", "...", "extINT"}; 58 uint32_t remote_irr = 0; 59 int i; 60 61 monitor_printf(mon, "ioapic ver=0x%x id=0x%02x sel=0x%02x", 62 s->version, s->id, s->ioregsel); 63 if (s->ioregsel) { 64 monitor_printf(mon, " (redir[%u])\n", 65 (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1); 66 } else { 67 monitor_printf(mon, "\n"); 68 } 69 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 70 uint64_t entry = s->ioredtbl[i]; 71 uint32_t delm = (uint32_t)((entry & IOAPIC_LVT_DELIV_MODE) >> 72 IOAPIC_LVT_DELIV_MODE_SHIFT); 73 monitor_printf(mon, "pin %-2u 0x%016"PRIx64" dest=%"PRIx64 74 " vec=%-3"PRIu64" %s %-5s %-6s %-6s %s\n", 75 i, entry, 76 (entry >> IOAPIC_LVT_DEST_SHIFT) & 77 (entry & IOAPIC_LVT_DEST_MODE ? 0xff : 0xf), 78 entry & IOAPIC_VECTOR_MASK, 79 entry & IOAPIC_LVT_POLARITY ? "active-lo" : "active-hi", 80 entry & IOAPIC_LVT_TRIGGER_MODE ? "level" : "edge", 81 entry & IOAPIC_LVT_MASKED ? "masked" : "", 82 delm_str[delm], 83 entry & IOAPIC_LVT_DEST_MODE ? "logical" : "physical"); 84 85 remote_irr |= entry & IOAPIC_LVT_TRIGGER_MODE ? 86 (entry & IOAPIC_LVT_REMOTE_IRR ? (1 << i) : 0) : 0; 87 } 88 ioapic_irr_dump(mon, "IRR", s->irr); 89 ioapic_irr_dump(mon, "Remote IRR", remote_irr); 90 } 91 92 void ioapic_reset_common(DeviceState *dev) 93 { 94 IOAPICCommonState *s = IOAPIC_COMMON(dev); 95 int i; 96 97 s->id = 0; 98 s->ioregsel = 0; 99 s->irr = 0; 100 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 101 s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT; 102 } 103 } 104 105 static int ioapic_dispatch_pre_save(void *opaque) 106 { 107 IOAPICCommonState *s = IOAPIC_COMMON(opaque); 108 IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s); 109 110 if (info->pre_save) { 111 info->pre_save(s); 112 } 113 114 return 0; 115 } 116 117 static int ioapic_dispatch_post_load(void *opaque, int version_id) 118 { 119 IOAPICCommonState *s = IOAPIC_COMMON(opaque); 120 IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s); 121 122 if (info->post_load) { 123 info->post_load(s); 124 } 125 return 0; 126 } 127 128 static void ioapic_common_realize(DeviceState *dev, Error **errp) 129 { 130 IOAPICCommonState *s = IOAPIC_COMMON(dev); 131 IOAPICCommonClass *info; 132 133 if (ioapic_no >= MAX_IOAPICS) { 134 error_setg(errp, "Only %d ioapics allowed", MAX_IOAPICS); 135 return; 136 } 137 138 info = IOAPIC_COMMON_GET_CLASS(s); 139 info->realize(dev, errp); 140 141 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io_memory); 142 ioapic_no++; 143 } 144 145 static const VMStateDescription vmstate_ioapic_common = { 146 .name = "ioapic", 147 .version_id = 3, 148 .minimum_version_id = 1, 149 .pre_save = ioapic_dispatch_pre_save, 150 .post_load = ioapic_dispatch_post_load, 151 .fields = (VMStateField[]) { 152 VMSTATE_UINT8(id, IOAPICCommonState), 153 VMSTATE_UINT8(ioregsel, IOAPICCommonState), 154 VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */ 155 VMSTATE_UINT32_V(irr, IOAPICCommonState, 2), 156 VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICCommonState, IOAPIC_NUM_PINS), 157 VMSTATE_END_OF_LIST() 158 } 159 }; 160 161 static void ioapic_common_class_init(ObjectClass *klass, void *data) 162 { 163 DeviceClass *dc = DEVICE_CLASS(klass); 164 165 dc->realize = ioapic_common_realize; 166 dc->vmsd = &vmstate_ioapic_common; 167 } 168 169 static const TypeInfo ioapic_common_type = { 170 .name = TYPE_IOAPIC_COMMON, 171 .parent = TYPE_SYS_BUS_DEVICE, 172 .instance_size = sizeof(IOAPICCommonState), 173 .class_size = sizeof(IOAPICCommonClass), 174 .class_init = ioapic_common_class_init, 175 .abstract = true, 176 }; 177 178 static void ioapic_common_register_types(void) 179 { 180 type_register_static(&ioapic_common_type); 181 } 182 183 type_init(ioapic_common_register_types) 184