1 /* 2 * IOAPIC emulation logic - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * Copyright (c) 2009 Xiantao Zhang, Intel 6 * Copyright (c) 2011 Jan Kiszka, Siemens AG 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "monitor/monitor.h" 24 #include "hw/i386/ioapic.h" 25 #include "hw/i386/ioapic_internal.h" 26 #include "hw/sysbus.h" 27 28 /* ioapic_no count start from 0 to MAX_IOAPICS, 29 * remove as static variable from ioapic_common_init. 30 * now as a global variable, let child to increase the counter 31 * then we can drop the 'instance_no' argument 32 * and convert to our QOM's realize function 33 */ 34 int ioapic_no; 35 36 static void ioapic_irr_dump(Monitor *mon, const char *name, uint32_t bitmap) 37 { 38 int i; 39 40 monitor_printf(mon, "%-10s ", name); 41 if (bitmap == 0) { 42 monitor_printf(mon, "(none)\n"); 43 return; 44 } 45 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 46 if (bitmap & (1 << i)) { 47 monitor_printf(mon, "%-2u ", i); 48 } 49 } 50 monitor_printf(mon, "\n"); 51 } 52 53 void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s) 54 { 55 static const char *delm_str[] = { 56 "fixed", "lowest", "SMI", "...", "NMI", "INIT", "...", "extINT"}; 57 uint32_t remote_irr = 0; 58 int i; 59 60 monitor_printf(mon, "ioapic id=0x%02x sel=0x%02x", s->id, s->ioregsel); 61 if (s->ioregsel) { 62 monitor_printf(mon, " (redir[%u])\n", 63 (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1); 64 } else { 65 monitor_printf(mon, "\n"); 66 } 67 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 68 uint64_t entry = s->ioredtbl[i]; 69 uint32_t delm = (uint32_t)((entry & IOAPIC_LVT_DELIV_MODE) >> 70 IOAPIC_LVT_DELIV_MODE_SHIFT); 71 monitor_printf(mon, "pin %-2u 0x%016"PRIx64" dest=%"PRIx64 72 " vec=%-3"PRIu64" %s %-5s %-6s %-6s %s\n", 73 i, entry, 74 (entry >> IOAPIC_LVT_DEST_SHIFT) & 75 (entry & IOAPIC_LVT_DEST_MODE ? 0xff : 0xf), 76 entry & IOAPIC_VECTOR_MASK, 77 entry & IOAPIC_LVT_POLARITY ? "active-lo" : "active-hi", 78 entry & IOAPIC_LVT_TRIGGER_MODE ? "level" : "edge", 79 entry & IOAPIC_LVT_MASKED ? "masked" : "", 80 delm_str[delm], 81 entry & IOAPIC_LVT_DEST_MODE ? "logical" : "physical"); 82 83 remote_irr |= entry & IOAPIC_LVT_TRIGGER_MODE ? 84 (entry & IOAPIC_LVT_REMOTE_IRR ? (1 << i) : 0) : 0; 85 } 86 ioapic_irr_dump(mon, "IRR", s->irr); 87 ioapic_irr_dump(mon, "Remote IRR", remote_irr); 88 } 89 90 void ioapic_reset_common(DeviceState *dev) 91 { 92 IOAPICCommonState *s = IOAPIC_COMMON(dev); 93 int i; 94 95 s->id = 0; 96 s->ioregsel = 0; 97 s->irr = 0; 98 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 99 s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT; 100 } 101 } 102 103 static void ioapic_dispatch_pre_save(void *opaque) 104 { 105 IOAPICCommonState *s = IOAPIC_COMMON(opaque); 106 IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s); 107 108 if (info->pre_save) { 109 info->pre_save(s); 110 } 111 } 112 113 static int ioapic_dispatch_post_load(void *opaque, int version_id) 114 { 115 IOAPICCommonState *s = IOAPIC_COMMON(opaque); 116 IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s); 117 118 if (info->post_load) { 119 info->post_load(s); 120 } 121 return 0; 122 } 123 124 static void ioapic_common_realize(DeviceState *dev, Error **errp) 125 { 126 IOAPICCommonState *s = IOAPIC_COMMON(dev); 127 IOAPICCommonClass *info; 128 129 if (ioapic_no >= MAX_IOAPICS) { 130 error_setg(errp, "Only %d ioapics allowed", MAX_IOAPICS); 131 return; 132 } 133 134 info = IOAPIC_COMMON_GET_CLASS(s); 135 info->realize(dev, errp); 136 137 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io_memory); 138 ioapic_no++; 139 } 140 141 static const VMStateDescription vmstate_ioapic_common = { 142 .name = "ioapic", 143 .version_id = 3, 144 .minimum_version_id = 1, 145 .pre_save = ioapic_dispatch_pre_save, 146 .post_load = ioapic_dispatch_post_load, 147 .fields = (VMStateField[]) { 148 VMSTATE_UINT8(id, IOAPICCommonState), 149 VMSTATE_UINT8(ioregsel, IOAPICCommonState), 150 VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */ 151 VMSTATE_UINT32_V(irr, IOAPICCommonState, 2), 152 VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICCommonState, IOAPIC_NUM_PINS), 153 VMSTATE_END_OF_LIST() 154 } 155 }; 156 157 static void ioapic_common_class_init(ObjectClass *klass, void *data) 158 { 159 DeviceClass *dc = DEVICE_CLASS(klass); 160 161 dc->realize = ioapic_common_realize; 162 dc->vmsd = &vmstate_ioapic_common; 163 } 164 165 static const TypeInfo ioapic_common_type = { 166 .name = TYPE_IOAPIC_COMMON, 167 .parent = TYPE_SYS_BUS_DEVICE, 168 .instance_size = sizeof(IOAPICCommonState), 169 .class_size = sizeof(IOAPICCommonClass), 170 .class_init = ioapic_common_class_init, 171 .abstract = true, 172 }; 173 174 static void ioapic_common_register_types(void) 175 { 176 type_register_static(&ioapic_common_type); 177 } 178 179 type_init(ioapic_common_register_types) 180