1 /* 2 * IOAPIC emulation logic - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * Copyright (c) 2009 Xiantao Zhang, Intel 6 * Copyright (c) 2011 Jan Kiszka, Siemens AG 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "monitor/monitor.h" 25 #include "hw/i386/ioapic.h" 26 #include "hw/i386/ioapic_internal.h" 27 #include "hw/intc/intc.h" 28 #include "hw/sysbus.h" 29 30 /* ioapic_no count start from 0 to MAX_IOAPICS, 31 * remove as static variable from ioapic_common_init. 32 * now as a global variable, let child to increase the counter 33 * then we can drop the 'instance_no' argument 34 * and convert to our QOM's realize function 35 */ 36 int ioapic_no; 37 38 static void ioapic_irr_dump(Monitor *mon, const char *name, uint32_t bitmap) 39 { 40 int i; 41 42 monitor_printf(mon, "%-10s ", name); 43 if (bitmap == 0) { 44 monitor_printf(mon, "(none)\n"); 45 return; 46 } 47 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 48 if (bitmap & (1 << i)) { 49 monitor_printf(mon, "%-2u ", i); 50 } 51 } 52 monitor_printf(mon, "\n"); 53 } 54 55 void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s) 56 { 57 static const char *delm_str[] = { 58 "fixed", "lowest", "SMI", "...", "NMI", "INIT", "...", "extINT"}; 59 uint32_t remote_irr = 0; 60 int i; 61 62 monitor_printf(mon, "ioapic ver=0x%x id=0x%02x sel=0x%02x", 63 s->version, s->id, s->ioregsel); 64 if (s->ioregsel) { 65 monitor_printf(mon, " (redir[%u])\n", 66 (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1); 67 } else { 68 monitor_printf(mon, "\n"); 69 } 70 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 71 uint64_t entry = s->ioredtbl[i]; 72 uint32_t delm = (uint32_t)((entry & IOAPIC_LVT_DELIV_MODE) >> 73 IOAPIC_LVT_DELIV_MODE_SHIFT); 74 monitor_printf(mon, "pin %-2u 0x%016"PRIx64" dest=%"PRIx64 75 " vec=%-3"PRIu64" %s %-5s %-6s %-6s %s\n", 76 i, entry, 77 (entry >> IOAPIC_LVT_DEST_SHIFT) & 78 (entry & IOAPIC_LVT_DEST_MODE ? 0xff : 0xf), 79 entry & IOAPIC_VECTOR_MASK, 80 entry & IOAPIC_LVT_POLARITY ? "active-lo" : "active-hi", 81 entry & IOAPIC_LVT_TRIGGER_MODE ? "level" : "edge", 82 entry & IOAPIC_LVT_MASKED ? "masked" : "", 83 delm_str[delm], 84 entry & IOAPIC_LVT_DEST_MODE ? "logical" : "physical"); 85 86 remote_irr |= entry & IOAPIC_LVT_TRIGGER_MODE ? 87 (entry & IOAPIC_LVT_REMOTE_IRR ? (1 << i) : 0) : 0; 88 } 89 ioapic_irr_dump(mon, "IRR", s->irr); 90 ioapic_irr_dump(mon, "Remote IRR", remote_irr); 91 } 92 93 void ioapic_reset_common(DeviceState *dev) 94 { 95 IOAPICCommonState *s = IOAPIC_COMMON(dev); 96 int i; 97 98 s->id = 0; 99 s->ioregsel = 0; 100 s->irr = 0; 101 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 102 s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT; 103 } 104 } 105 106 static int ioapic_dispatch_pre_save(void *opaque) 107 { 108 IOAPICCommonState *s = IOAPIC_COMMON(opaque); 109 IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s); 110 111 if (info->pre_save) { 112 info->pre_save(s); 113 } 114 115 return 0; 116 } 117 118 static int ioapic_dispatch_post_load(void *opaque, int version_id) 119 { 120 IOAPICCommonState *s = IOAPIC_COMMON(opaque); 121 IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s); 122 123 if (info->post_load) { 124 info->post_load(s); 125 } 126 return 0; 127 } 128 129 static void ioapic_common_realize(DeviceState *dev, Error **errp) 130 { 131 IOAPICCommonState *s = IOAPIC_COMMON(dev); 132 IOAPICCommonClass *info; 133 134 if (ioapic_no >= MAX_IOAPICS) { 135 error_setg(errp, "Only %d ioapics allowed", MAX_IOAPICS); 136 return; 137 } 138 139 info = IOAPIC_COMMON_GET_CLASS(s); 140 info->realize(dev, errp); 141 142 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io_memory); 143 ioapic_no++; 144 } 145 146 static void ioapic_print_info(InterruptStatsProvider *obj, 147 Monitor *mon) 148 { 149 IOAPICCommonState *s = IOAPIC_COMMON(obj); 150 151 ioapic_dispatch_pre_save(s); 152 ioapic_print_redtbl(mon, s); 153 } 154 155 static const VMStateDescription vmstate_ioapic_common = { 156 .name = "ioapic", 157 .version_id = 3, 158 .minimum_version_id = 1, 159 .pre_save = ioapic_dispatch_pre_save, 160 .post_load = ioapic_dispatch_post_load, 161 .fields = (VMStateField[]) { 162 VMSTATE_UINT8(id, IOAPICCommonState), 163 VMSTATE_UINT8(ioregsel, IOAPICCommonState), 164 VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */ 165 VMSTATE_UINT32_V(irr, IOAPICCommonState, 2), 166 VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICCommonState, IOAPIC_NUM_PINS), 167 VMSTATE_END_OF_LIST() 168 } 169 }; 170 171 static void ioapic_common_class_init(ObjectClass *klass, void *data) 172 { 173 DeviceClass *dc = DEVICE_CLASS(klass); 174 InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass); 175 176 dc->realize = ioapic_common_realize; 177 dc->vmsd = &vmstate_ioapic_common; 178 ic->print_info = ioapic_print_info; 179 } 180 181 static const TypeInfo ioapic_common_type = { 182 .name = TYPE_IOAPIC_COMMON, 183 .parent = TYPE_SYS_BUS_DEVICE, 184 .instance_size = sizeof(IOAPICCommonState), 185 .class_size = sizeof(IOAPICCommonClass), 186 .class_init = ioapic_common_class_init, 187 .abstract = true, 188 .interfaces = (InterfaceInfo[]) { 189 { TYPE_INTERRUPT_STATS_PROVIDER }, 190 { } 191 }, 192 }; 193 194 static void ioapic_common_register_types(void) 195 { 196 type_register_static(&ioapic_common_type); 197 } 198 199 type_init(ioapic_common_register_types) 200