1 /* 2 * ioapic.c IOAPIC emulation logic 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * Split the ioapic logic from apic.c 7 * Xiantao Zhang <xiantao.zhang@intel.com> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "monitor/monitor.h" 26 #include "hw/hw.h" 27 #include "hw/i386/pc.h" 28 #include "hw/i386/apic.h" 29 #include "hw/i386/ioapic.h" 30 #include "hw/i386/ioapic_internal.h" 31 #include "hw/pci/msi.h" 32 #include "sysemu/kvm.h" 33 #include "hw/i386/apic-msidef.h" 34 #include "hw/i386/x86-iommu.h" 35 #include "trace.h" 36 37 #define APIC_DELIVERY_MODE_SHIFT 8 38 #define APIC_POLARITY_SHIFT 14 39 #define APIC_TRIG_MODE_SHIFT 15 40 41 static IOAPICCommonState *ioapics[MAX_IOAPICS]; 42 43 /* global variable from ioapic_common.c */ 44 extern int ioapic_no; 45 46 struct ioapic_entry_info { 47 /* fields parsed from IOAPIC entries */ 48 uint8_t masked; 49 uint8_t trig_mode; 50 uint16_t dest_idx; 51 uint8_t dest_mode; 52 uint8_t delivery_mode; 53 uint8_t vector; 54 55 /* MSI message generated from above parsed fields */ 56 uint32_t addr; 57 uint32_t data; 58 }; 59 60 static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info) 61 { 62 memset(info, 0, sizeof(*info)); 63 info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1; 64 info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1; 65 /* 66 * By default, this would be dest_id[8] + reserved[8]. When IR 67 * is enabled, this would be interrupt_index[15] + 68 * interrupt_format[1]. This field never means anything, but 69 * only used to generate corresponding MSI. 70 */ 71 info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff; 72 info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; 73 info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \ 74 & IOAPIC_DM_MASK; 75 if (info->delivery_mode == IOAPIC_DM_EXTINT) { 76 info->vector = pic_read_irq(isa_pic); 77 } else { 78 info->vector = entry & IOAPIC_VECTOR_MASK; 79 } 80 81 info->addr = APIC_DEFAULT_ADDRESS | \ 82 (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \ 83 (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT); 84 info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \ 85 (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \ 86 (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT); 87 } 88 89 static void ioapic_service(IOAPICCommonState *s) 90 { 91 AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as; 92 struct ioapic_entry_info info; 93 uint8_t i; 94 uint32_t mask; 95 uint64_t entry; 96 97 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 98 mask = 1 << i; 99 if (s->irr & mask) { 100 int coalesce = 0; 101 102 entry = s->ioredtbl[i]; 103 ioapic_entry_parse(entry, &info); 104 if (!info.masked) { 105 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { 106 s->irr &= ~mask; 107 } else { 108 coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR; 109 trace_ioapic_set_remote_irr(i); 110 s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; 111 } 112 113 if (coalesce) { 114 /* We are level triggered interrupts, and the 115 * guest should be still working on previous one, 116 * so skip it. */ 117 continue; 118 } 119 120 #ifdef CONFIG_KVM 121 if (kvm_irqchip_is_split()) { 122 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) { 123 kvm_set_irq(kvm_state, i, 1); 124 kvm_set_irq(kvm_state, i, 0); 125 } else { 126 kvm_set_irq(kvm_state, i, 1); 127 } 128 continue; 129 } 130 #endif 131 132 /* No matter whether IR is enabled, we translate 133 * the IOAPIC message into a MSI one, and its 134 * address space will decide whether we need a 135 * translation. */ 136 stl_le_phys(ioapic_as, info.addr, info.data); 137 } 138 } 139 } 140 } 141 142 static void ioapic_set_irq(void *opaque, int vector, int level) 143 { 144 IOAPICCommonState *s = opaque; 145 146 /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps 147 * to GSI 2. GSI maps to ioapic 1-1. This is not 148 * the cleanest way of doing it but it should work. */ 149 150 trace_ioapic_set_irq(vector, level); 151 ioapic_stat_update_irq(s, vector, level); 152 if (vector == 0) { 153 vector = 2; 154 } 155 if (vector < IOAPIC_NUM_PINS) { 156 uint32_t mask = 1 << vector; 157 uint64_t entry = s->ioredtbl[vector]; 158 159 if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) == 160 IOAPIC_TRIGGER_LEVEL) { 161 /* level triggered */ 162 if (level) { 163 s->irr |= mask; 164 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) { 165 ioapic_service(s); 166 } 167 } else { 168 s->irr &= ~mask; 169 } 170 } else { 171 /* According to the 82093AA manual, we must ignore edge requests 172 * if the input pin is masked. */ 173 if (level && !(entry & IOAPIC_LVT_MASKED)) { 174 s->irr |= mask; 175 ioapic_service(s); 176 } 177 } 178 } 179 } 180 181 static void ioapic_update_kvm_routes(IOAPICCommonState *s) 182 { 183 #ifdef CONFIG_KVM 184 int i; 185 186 if (kvm_irqchip_is_split()) { 187 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 188 MSIMessage msg; 189 struct ioapic_entry_info info; 190 ioapic_entry_parse(s->ioredtbl[i], &info); 191 msg.address = info.addr; 192 msg.data = info.data; 193 kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL); 194 } 195 kvm_irqchip_commit_routes(kvm_state); 196 } 197 #endif 198 } 199 200 #ifdef CONFIG_KVM 201 static void ioapic_iec_notifier(void *private, bool global, 202 uint32_t index, uint32_t mask) 203 { 204 IOAPICCommonState *s = (IOAPICCommonState *)private; 205 /* For simplicity, we just update all the routes */ 206 ioapic_update_kvm_routes(s); 207 } 208 #endif 209 210 void ioapic_eoi_broadcast(int vector) 211 { 212 IOAPICCommonState *s; 213 uint64_t entry; 214 int i, n; 215 216 trace_ioapic_eoi_broadcast(vector); 217 218 for (i = 0; i < MAX_IOAPICS; i++) { 219 s = ioapics[i]; 220 if (!s) { 221 continue; 222 } 223 for (n = 0; n < IOAPIC_NUM_PINS; n++) { 224 entry = s->ioredtbl[n]; 225 if ((entry & IOAPIC_LVT_REMOTE_IRR) 226 && (entry & IOAPIC_VECTOR_MASK) == vector) { 227 trace_ioapic_clear_remote_irr(n, vector); 228 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR; 229 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { 230 ioapic_service(s); 231 } 232 } 233 } 234 } 235 } 236 237 static uint64_t 238 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size) 239 { 240 IOAPICCommonState *s = opaque; 241 int index; 242 uint32_t val = 0; 243 244 addr &= 0xff; 245 246 switch (addr) { 247 case IOAPIC_IOREGSEL: 248 val = s->ioregsel; 249 break; 250 case IOAPIC_IOWIN: 251 if (size != 4) { 252 break; 253 } 254 switch (s->ioregsel) { 255 case IOAPIC_REG_ID: 256 case IOAPIC_REG_ARB: 257 val = s->id << IOAPIC_ID_SHIFT; 258 break; 259 case IOAPIC_REG_VER: 260 val = s->version | 261 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); 262 break; 263 default: 264 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; 265 if (index >= 0 && index < IOAPIC_NUM_PINS) { 266 if (s->ioregsel & 1) { 267 val = s->ioredtbl[index] >> 32; 268 } else { 269 val = s->ioredtbl[index] & 0xffffffff; 270 } 271 } 272 } 273 break; 274 } 275 276 trace_ioapic_mem_read(addr, s->ioregsel, size, val); 277 278 return val; 279 } 280 281 /* 282 * This is to satisfy the hack in Linux kernel. One hack of it is to 283 * simulate clearing the Remote IRR bit of IOAPIC entry using the 284 * following: 285 * 286 * "For IO-APIC's with EOI register, we use that to do an explicit EOI. 287 * Otherwise, we simulate the EOI message manually by changing the trigger 288 * mode to edge and then back to level, with RTE being masked during 289 * this." 290 * 291 * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701) 292 * 293 * This is based on the assumption that, Remote IRR bit will be 294 * cleared by IOAPIC hardware when configured as edge-triggered 295 * interrupts. 296 * 297 * Without this, level-triggered interrupts in IR mode might fail to 298 * work correctly. 299 */ 300 static inline void 301 ioapic_fix_edge_remote_irr(uint64_t *entry) 302 { 303 if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) { 304 /* Edge-triggered interrupts, make sure remote IRR is zero */ 305 *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR); 306 } 307 } 308 309 static void 310 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, 311 unsigned int size) 312 { 313 IOAPICCommonState *s = opaque; 314 int index; 315 316 addr &= 0xff; 317 trace_ioapic_mem_write(addr, s->ioregsel, size, val); 318 319 switch (addr) { 320 case IOAPIC_IOREGSEL: 321 s->ioregsel = val; 322 break; 323 case IOAPIC_IOWIN: 324 if (size != 4) { 325 break; 326 } 327 switch (s->ioregsel) { 328 case IOAPIC_REG_ID: 329 s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK; 330 break; 331 case IOAPIC_REG_VER: 332 case IOAPIC_REG_ARB: 333 break; 334 default: 335 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; 336 if (index >= 0 && index < IOAPIC_NUM_PINS) { 337 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS; 338 if (s->ioregsel & 1) { 339 s->ioredtbl[index] &= 0xffffffff; 340 s->ioredtbl[index] |= (uint64_t)val << 32; 341 } else { 342 s->ioredtbl[index] &= ~0xffffffffULL; 343 s->ioredtbl[index] |= val; 344 } 345 /* restore RO bits */ 346 s->ioredtbl[index] &= IOAPIC_RW_BITS; 347 s->ioredtbl[index] |= ro_bits; 348 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); 349 ioapic_service(s); 350 } 351 } 352 break; 353 case IOAPIC_EOI: 354 /* Explicit EOI is only supported for IOAPIC version 0x20 */ 355 if (size != 4 || s->version != 0x20) { 356 break; 357 } 358 ioapic_eoi_broadcast(val); 359 break; 360 } 361 362 ioapic_update_kvm_routes(s); 363 } 364 365 static const MemoryRegionOps ioapic_io_ops = { 366 .read = ioapic_mem_read, 367 .write = ioapic_mem_write, 368 .endianness = DEVICE_NATIVE_ENDIAN, 369 }; 370 371 static void ioapic_machine_done_notify(Notifier *notifier, void *data) 372 { 373 #ifdef CONFIG_KVM 374 IOAPICCommonState *s = container_of(notifier, IOAPICCommonState, 375 machine_done); 376 377 if (kvm_irqchip_is_split()) { 378 X86IOMMUState *iommu = x86_iommu_get_default(); 379 if (iommu) { 380 /* Register this IOAPIC with IOMMU IEC notifier, so that 381 * when there are IR invalidates, we can be notified to 382 * update kernel IR cache. */ 383 x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s); 384 } 385 } 386 #endif 387 } 388 389 #define IOAPIC_VER_DEF 0x20 390 391 static void ioapic_realize(DeviceState *dev, Error **errp) 392 { 393 IOAPICCommonState *s = IOAPIC_COMMON(dev); 394 395 if (s->version != 0x11 && s->version != 0x20) { 396 error_setg(errp, "IOAPIC only supports version 0x11 or 0x20 " 397 "(default: 0x%x).", IOAPIC_VER_DEF); 398 return; 399 } 400 401 memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s, 402 "ioapic", 0x1000); 403 404 qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS); 405 406 ioapics[ioapic_no] = s; 407 s->machine_done.notify = ioapic_machine_done_notify; 408 qemu_add_machine_init_done_notifier(&s->machine_done); 409 } 410 411 static Property ioapic_properties[] = { 412 DEFINE_PROP_UINT8("version", IOAPICCommonState, version, IOAPIC_VER_DEF), 413 DEFINE_PROP_END_OF_LIST(), 414 }; 415 416 static void ioapic_class_init(ObjectClass *klass, void *data) 417 { 418 IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass); 419 DeviceClass *dc = DEVICE_CLASS(klass); 420 421 k->realize = ioapic_realize; 422 /* 423 * If APIC is in kernel, we need to update the kernel cache after 424 * migration, otherwise first 24 gsi routes will be invalid. 425 */ 426 k->post_load = ioapic_update_kvm_routes; 427 dc->reset = ioapic_reset_common; 428 dc->props = ioapic_properties; 429 } 430 431 static const TypeInfo ioapic_info = { 432 .name = TYPE_IOAPIC, 433 .parent = TYPE_IOAPIC_COMMON, 434 .instance_size = sizeof(IOAPICCommonState), 435 .class_init = ioapic_class_init, 436 }; 437 438 static void ioapic_register_types(void) 439 { 440 type_register_static(&ioapic_info); 441 } 442 443 type_init(ioapic_register_types) 444