1 /* 2 * ioapic.c IOAPIC emulation logic 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * Split the ioapic logic from apic.c 7 * Xiantao Zhang <xiantao.zhang@intel.com> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "monitor/monitor.h" 25 #include "hw/hw.h" 26 #include "hw/i386/pc.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/ioapic.h" 29 #include "hw/i386/ioapic_internal.h" 30 #include "include/hw/pci/msi.h" 31 #include "sysemu/kvm.h" 32 33 //#define DEBUG_IOAPIC 34 35 #ifdef DEBUG_IOAPIC 36 #define DPRINTF(fmt, ...) \ 37 do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0) 38 #else 39 #define DPRINTF(fmt, ...) 40 #endif 41 42 #define APIC_DELIVERY_MODE_SHIFT 8 43 #define APIC_POLARITY_SHIFT 14 44 #define APIC_TRIG_MODE_SHIFT 15 45 46 static IOAPICCommonState *ioapics[MAX_IOAPICS]; 47 48 /* global variable from ioapic_common.c */ 49 extern int ioapic_no; 50 51 static void ioapic_service(IOAPICCommonState *s) 52 { 53 uint8_t i; 54 uint8_t trig_mode; 55 uint8_t vector; 56 uint8_t delivery_mode; 57 uint32_t mask; 58 uint64_t entry; 59 uint8_t dest; 60 uint8_t dest_mode; 61 62 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 63 mask = 1 << i; 64 if (s->irr & mask) { 65 int coalesce = 0; 66 67 entry = s->ioredtbl[i]; 68 if (!(entry & IOAPIC_LVT_MASKED)) { 69 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1); 70 dest = entry >> IOAPIC_LVT_DEST_SHIFT; 71 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; 72 delivery_mode = 73 (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK; 74 if (trig_mode == IOAPIC_TRIGGER_EDGE) { 75 s->irr &= ~mask; 76 } else { 77 coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR; 78 s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; 79 } 80 if (delivery_mode == IOAPIC_DM_EXTINT) { 81 vector = pic_read_irq(isa_pic); 82 } else { 83 vector = entry & IOAPIC_VECTOR_MASK; 84 } 85 #ifdef CONFIG_KVM 86 if (kvm_irqchip_is_split()) { 87 if (trig_mode == IOAPIC_TRIGGER_EDGE) { 88 kvm_set_irq(kvm_state, i, 1); 89 kvm_set_irq(kvm_state, i, 0); 90 } else { 91 if (!coalesce) { 92 kvm_set_irq(kvm_state, i, 1); 93 } 94 } 95 continue; 96 } 97 #else 98 (void)coalesce; 99 #endif 100 apic_deliver_irq(dest, dest_mode, delivery_mode, vector, 101 trig_mode); 102 } 103 } 104 } 105 } 106 107 static void ioapic_set_irq(void *opaque, int vector, int level) 108 { 109 IOAPICCommonState *s = opaque; 110 111 /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps 112 * to GSI 2. GSI maps to ioapic 1-1. This is not 113 * the cleanest way of doing it but it should work. */ 114 115 DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector); 116 if (vector == 0) { 117 vector = 2; 118 } 119 if (vector >= 0 && vector < IOAPIC_NUM_PINS) { 120 uint32_t mask = 1 << vector; 121 uint64_t entry = s->ioredtbl[vector]; 122 123 if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) == 124 IOAPIC_TRIGGER_LEVEL) { 125 /* level triggered */ 126 if (level) { 127 s->irr |= mask; 128 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) { 129 ioapic_service(s); 130 } 131 } else { 132 s->irr &= ~mask; 133 } 134 } else { 135 /* According to the 82093AA manual, we must ignore edge requests 136 * if the input pin is masked. */ 137 if (level && !(entry & IOAPIC_LVT_MASKED)) { 138 s->irr |= mask; 139 ioapic_service(s); 140 } 141 } 142 } 143 } 144 145 static void ioapic_update_kvm_routes(IOAPICCommonState *s) 146 { 147 #ifdef CONFIG_KVM 148 int i; 149 150 if (kvm_irqchip_is_split()) { 151 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 152 uint64_t entry = s->ioredtbl[i]; 153 uint8_t trig_mode; 154 uint8_t delivery_mode; 155 uint8_t dest; 156 uint8_t dest_mode; 157 uint64_t pin_polarity; 158 MSIMessage msg; 159 160 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1); 161 dest = entry >> IOAPIC_LVT_DEST_SHIFT; 162 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; 163 pin_polarity = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1; 164 delivery_mode = 165 (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK; 166 167 msg.address = APIC_DEFAULT_ADDRESS; 168 msg.address |= dest_mode << 2; 169 msg.address |= dest << 12; 170 171 msg.data = entry & IOAPIC_VECTOR_MASK; 172 msg.data |= delivery_mode << APIC_DELIVERY_MODE_SHIFT; 173 msg.data |= pin_polarity << APIC_POLARITY_SHIFT; 174 msg.data |= trig_mode << APIC_TRIG_MODE_SHIFT; 175 176 kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL); 177 } 178 kvm_irqchip_commit_routes(kvm_state); 179 } 180 #endif 181 } 182 183 void ioapic_eoi_broadcast(int vector) 184 { 185 IOAPICCommonState *s; 186 uint64_t entry; 187 int i, n; 188 189 for (i = 0; i < MAX_IOAPICS; i++) { 190 s = ioapics[i]; 191 if (!s) { 192 continue; 193 } 194 for (n = 0; n < IOAPIC_NUM_PINS; n++) { 195 entry = s->ioredtbl[n]; 196 if ((entry & IOAPIC_LVT_REMOTE_IRR) 197 && (entry & IOAPIC_VECTOR_MASK) == vector) { 198 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR; 199 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { 200 ioapic_service(s); 201 } 202 } 203 } 204 } 205 } 206 207 void ioapic_dump_state(Monitor *mon, const QDict *qdict) 208 { 209 int i; 210 211 for (i = 0; i < MAX_IOAPICS; i++) { 212 if (ioapics[i] != 0) { 213 ioapic_print_redtbl(mon, ioapics[i]); 214 } 215 } 216 } 217 218 static uint64_t 219 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size) 220 { 221 IOAPICCommonState *s = opaque; 222 int index; 223 uint32_t val = 0; 224 225 switch (addr & 0xff) { 226 case IOAPIC_IOREGSEL: 227 val = s->ioregsel; 228 break; 229 case IOAPIC_IOWIN: 230 if (size != 4) { 231 break; 232 } 233 switch (s->ioregsel) { 234 case IOAPIC_REG_ID: 235 case IOAPIC_REG_ARB: 236 val = s->id << IOAPIC_ID_SHIFT; 237 break; 238 case IOAPIC_REG_VER: 239 val = IOAPIC_VERSION | 240 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); 241 break; 242 default: 243 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; 244 if (index >= 0 && index < IOAPIC_NUM_PINS) { 245 if (s->ioregsel & 1) { 246 val = s->ioredtbl[index] >> 32; 247 } else { 248 val = s->ioredtbl[index] & 0xffffffff; 249 } 250 } 251 } 252 DPRINTF("read: %08x = %08x\n", s->ioregsel, val); 253 break; 254 } 255 return val; 256 } 257 258 /* 259 * This is to satisfy the hack in Linux kernel. One hack of it is to 260 * simulate clearing the Remote IRR bit of IOAPIC entry using the 261 * following: 262 * 263 * "For IO-APIC's with EOI register, we use that to do an explicit EOI. 264 * Otherwise, we simulate the EOI message manually by changing the trigger 265 * mode to edge and then back to level, with RTE being masked during 266 * this." 267 * 268 * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701) 269 * 270 * This is based on the assumption that, Remote IRR bit will be 271 * cleared by IOAPIC hardware when configured as edge-triggered 272 * interrupts. 273 * 274 * Without this, level-triggered interrupts in IR mode might fail to 275 * work correctly. 276 */ 277 static inline void 278 ioapic_fix_edge_remote_irr(uint64_t *entry) 279 { 280 if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) { 281 /* Edge-triggered interrupts, make sure remote IRR is zero */ 282 *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR); 283 } 284 } 285 286 static void 287 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, 288 unsigned int size) 289 { 290 IOAPICCommonState *s = opaque; 291 int index; 292 293 switch (addr & 0xff) { 294 case IOAPIC_IOREGSEL: 295 s->ioregsel = val; 296 break; 297 case IOAPIC_IOWIN: 298 if (size != 4) { 299 break; 300 } 301 DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val); 302 switch (s->ioregsel) { 303 case IOAPIC_REG_ID: 304 s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK; 305 break; 306 case IOAPIC_REG_VER: 307 case IOAPIC_REG_ARB: 308 break; 309 default: 310 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; 311 if (index >= 0 && index < IOAPIC_NUM_PINS) { 312 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS; 313 if (s->ioregsel & 1) { 314 s->ioredtbl[index] &= 0xffffffff; 315 s->ioredtbl[index] |= (uint64_t)val << 32; 316 } else { 317 s->ioredtbl[index] &= ~0xffffffffULL; 318 s->ioredtbl[index] |= val; 319 } 320 /* restore RO bits */ 321 s->ioredtbl[index] &= IOAPIC_RW_BITS; 322 s->ioredtbl[index] |= ro_bits; 323 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); 324 ioapic_service(s); 325 } 326 } 327 break; 328 } 329 330 ioapic_update_kvm_routes(s); 331 } 332 333 static const MemoryRegionOps ioapic_io_ops = { 334 .read = ioapic_mem_read, 335 .write = ioapic_mem_write, 336 .endianness = DEVICE_NATIVE_ENDIAN, 337 }; 338 339 static void ioapic_realize(DeviceState *dev, Error **errp) 340 { 341 IOAPICCommonState *s = IOAPIC_COMMON(dev); 342 343 memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s, 344 "ioapic", 0x1000); 345 346 qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS); 347 348 ioapics[ioapic_no] = s; 349 } 350 351 static void ioapic_class_init(ObjectClass *klass, void *data) 352 { 353 IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass); 354 DeviceClass *dc = DEVICE_CLASS(klass); 355 356 k->realize = ioapic_realize; 357 dc->reset = ioapic_reset_common; 358 } 359 360 static const TypeInfo ioapic_info = { 361 .name = "ioapic", 362 .parent = TYPE_IOAPIC_COMMON, 363 .instance_size = sizeof(IOAPICCommonState), 364 .class_init = ioapic_class_init, 365 }; 366 367 static void ioapic_register_types(void) 368 { 369 type_register_static(&ioapic_info); 370 } 371 372 type_init(ioapic_register_types) 373