1 /* 2 * i.MX31 Vectored Interrupt Controller 3 * 4 * Note this is NOT the PL192 provided by ARM, but 5 * a custom implementation by Freescale. 6 * 7 * Copyright (c) 2008 OKL 8 * Copyright (c) 2011 NICTA Pty Ltd 9 * Originally written by Hans Jiang 10 * 11 * This code is licensed under the GPL version 2 or later. See 12 * the COPYING file in the top-level directory. 13 * 14 * TODO: implement vectors. 15 */ 16 17 #include "hw/hw.h" 18 #include "hw/sysbus.h" 19 #include "qemu/host-utils.h" 20 21 #define DEBUG_INT 1 22 #undef DEBUG_INT /* comment out for debugging */ 23 24 #ifdef DEBUG_INT 25 #define DPRINTF(fmt, args...) \ 26 do { printf("imx_avic: " fmt , ##args); } while (0) 27 #else 28 #define DPRINTF(fmt, args...) do {} while (0) 29 #endif 30 31 /* 32 * Define to 1 for messages about attempts to 33 * access unimplemented registers or similar. 34 */ 35 #define DEBUG_IMPLEMENTATION 1 36 #if DEBUG_IMPLEMENTATION 37 # define IPRINTF(fmt, args...) \ 38 do { fprintf(stderr, "imx_avic: " fmt, ##args); } while (0) 39 #else 40 # define IPRINTF(fmt, args...) do {} while (0) 41 #endif 42 43 #define IMX_AVIC_NUM_IRQS 64 44 45 /* Interrupt Control Bits */ 46 #define ABFLAG (1<<25) 47 #define ABFEN (1<<24) 48 #define NIDIS (1<<22) /* Normal Interrupt disable */ 49 #define FIDIS (1<<21) /* Fast interrupt disable */ 50 #define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */ 51 #define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */ 52 #define NM (1<<18) /* Normal interrupt mode */ 53 54 55 #define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4) 56 #define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD) 57 58 #define TYPE_IMX_AVIC "imx_avic" 59 #define IMX_AVIC(obj) \ 60 OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC) 61 62 typedef struct IMXAVICState { 63 SysBusDevice parent_obj; 64 65 MemoryRegion iomem; 66 uint64_t pending; 67 uint64_t enabled; 68 uint64_t is_fiq; 69 uint32_t intcntl; 70 uint32_t intmask; 71 qemu_irq irq; 72 qemu_irq fiq; 73 uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */ 74 } IMXAVICState; 75 76 static const VMStateDescription vmstate_imx_avic = { 77 .name = "imx-avic", 78 .version_id = 1, 79 .minimum_version_id = 1, 80 .fields = (VMStateField[]) { 81 VMSTATE_UINT64(pending, IMXAVICState), 82 VMSTATE_UINT64(enabled, IMXAVICState), 83 VMSTATE_UINT64(is_fiq, IMXAVICState), 84 VMSTATE_UINT32(intcntl, IMXAVICState), 85 VMSTATE_UINT32(intmask, IMXAVICState), 86 VMSTATE_UINT32_ARRAY(prio, IMXAVICState, PRIO_WORDS), 87 VMSTATE_END_OF_LIST() 88 }, 89 }; 90 91 92 93 static inline int imx_avic_prio(IMXAVICState *s, int irq) 94 { 95 uint32_t word = irq / PRIO_PER_WORD; 96 uint32_t part = 4 * (irq % PRIO_PER_WORD); 97 return 0xf & (s->prio[word] >> part); 98 } 99 100 static inline void imx_avic_set_prio(IMXAVICState *s, int irq, int prio) 101 { 102 uint32_t word = irq / PRIO_PER_WORD; 103 uint32_t part = 4 * (irq % PRIO_PER_WORD); 104 uint32_t mask = ~(0xf << part); 105 s->prio[word] &= mask; 106 s->prio[word] |= prio << part; 107 } 108 109 /* Update interrupts. */ 110 static void imx_avic_update(IMXAVICState *s) 111 { 112 int i; 113 uint64_t new = s->pending & s->enabled; 114 uint64_t flags; 115 116 flags = new & s->is_fiq; 117 qemu_set_irq(s->fiq, !!flags); 118 119 flags = new & ~s->is_fiq; 120 if (!flags || (s->intmask == 0x1f)) { 121 qemu_set_irq(s->irq, !!flags); 122 return; 123 } 124 125 /* 126 * Take interrupt if there's a pending interrupt with 127 * priority higher than the value of intmask 128 */ 129 for (i = 0; i < IMX_AVIC_NUM_IRQS; i++) { 130 if (flags & (1UL << i)) { 131 if (imx_avic_prio(s, i) > s->intmask) { 132 qemu_set_irq(s->irq, 1); 133 return; 134 } 135 } 136 } 137 qemu_set_irq(s->irq, 0); 138 } 139 140 static void imx_avic_set_irq(void *opaque, int irq, int level) 141 { 142 IMXAVICState *s = (IMXAVICState *)opaque; 143 144 if (level) { 145 DPRINTF("Raising IRQ %d, prio %d\n", 146 irq, imx_avic_prio(s, irq)); 147 s->pending |= (1ULL << irq); 148 } else { 149 DPRINTF("Clearing IRQ %d, prio %d\n", 150 irq, imx_avic_prio(s, irq)); 151 s->pending &= ~(1ULL << irq); 152 } 153 154 imx_avic_update(s); 155 } 156 157 158 static uint64_t imx_avic_read(void *opaque, 159 hwaddr offset, unsigned size) 160 { 161 IMXAVICState *s = (IMXAVICState *)opaque; 162 163 164 DPRINTF("read(offset = 0x%x)\n", offset >> 2); 165 switch (offset >> 2) { 166 case 0: /* INTCNTL */ 167 return s->intcntl; 168 169 case 1: /* Normal Interrupt Mask Register, NIMASK */ 170 return s->intmask; 171 172 case 2: /* Interrupt Enable Number Register, INTENNUM */ 173 case 3: /* Interrupt Disable Number Register, INTDISNUM */ 174 return 0; 175 176 case 4: /* Interrupt Enabled Number Register High */ 177 return s->enabled >> 32; 178 179 case 5: /* Interrupt Enabled Number Register Low */ 180 return s->enabled & 0xffffffffULL; 181 182 case 6: /* Interrupt Type Register High */ 183 return s->is_fiq >> 32; 184 185 case 7: /* Interrupt Type Register Low */ 186 return s->is_fiq & 0xffffffffULL; 187 188 case 8: /* Normal Interrupt Priority Register 7 */ 189 case 9: /* Normal Interrupt Priority Register 6 */ 190 case 10:/* Normal Interrupt Priority Register 5 */ 191 case 11:/* Normal Interrupt Priority Register 4 */ 192 case 12:/* Normal Interrupt Priority Register 3 */ 193 case 13:/* Normal Interrupt Priority Register 2 */ 194 case 14:/* Normal Interrupt Priority Register 1 */ 195 case 15:/* Normal Interrupt Priority Register 0 */ 196 return s->prio[15-(offset>>2)]; 197 198 case 16: /* Normal interrupt vector and status register */ 199 { 200 /* 201 * This returns the highest priority 202 * outstanding interrupt. Where there is more than 203 * one pending IRQ with the same priority, 204 * take the highest numbered one. 205 */ 206 uint64_t flags = s->pending & s->enabled & ~s->is_fiq; 207 int i; 208 int prio = -1; 209 int irq = -1; 210 for (i = 63; i >= 0; --i) { 211 if (flags & (1ULL<<i)) { 212 int irq_prio = imx_avic_prio(s, i); 213 if (irq_prio > prio) { 214 irq = i; 215 prio = irq_prio; 216 } 217 } 218 } 219 if (irq >= 0) { 220 imx_avic_set_irq(s, irq, 0); 221 return irq << 16 | prio; 222 } 223 return 0xffffffffULL; 224 } 225 case 17:/* Fast Interrupt vector and status register */ 226 { 227 uint64_t flags = s->pending & s->enabled & s->is_fiq; 228 int i = ctz64(flags); 229 if (i < 64) { 230 imx_avic_set_irq(opaque, i, 0); 231 return i; 232 } 233 return 0xffffffffULL; 234 } 235 case 18:/* Interrupt source register high */ 236 return s->pending >> 32; 237 238 case 19:/* Interrupt source register low */ 239 return s->pending & 0xffffffffULL; 240 241 case 20:/* Interrupt Force Register high */ 242 case 21:/* Interrupt Force Register low */ 243 return 0; 244 245 case 22:/* Normal Interrupt Pending Register High */ 246 return (s->pending & s->enabled & ~s->is_fiq) >> 32; 247 248 case 23:/* Normal Interrupt Pending Register Low */ 249 return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL; 250 251 case 24: /* Fast Interrupt Pending Register High */ 252 return (s->pending & s->enabled & s->is_fiq) >> 32; 253 254 case 25: /* Fast Interrupt Pending Register Low */ 255 return (s->pending & s->enabled & s->is_fiq) & 0xffffffffULL; 256 257 case 0x40: /* AVIC vector 0, use for WFI WAR */ 258 return 0x4; 259 260 default: 261 IPRINTF("imx_avic_read: Bad offset 0x%x\n", (int)offset); 262 return 0; 263 } 264 } 265 266 static void imx_avic_write(void *opaque, hwaddr offset, 267 uint64_t val, unsigned size) 268 { 269 IMXAVICState *s = (IMXAVICState *)opaque; 270 271 /* Vector Registers not yet supported */ 272 if (offset >= 0x100 && offset <= 0x2fc) { 273 IPRINTF("imx_avic_write to vector register %d ignored\n", 274 (unsigned int)((offset - 0x100) >> 2)); 275 return; 276 } 277 278 DPRINTF("imx_avic_write(0x%x) = %x\n", 279 (unsigned int)offset>>2, (unsigned int)val); 280 switch (offset >> 2) { 281 case 0: /* Interrupt Control Register, INTCNTL */ 282 s->intcntl = val & (ABFEN | NIDIS | FIDIS | NIAD | FIAD | NM); 283 if (s->intcntl & ABFEN) { 284 s->intcntl &= ~(val & ABFLAG); 285 } 286 break; 287 288 case 1: /* Normal Interrupt Mask Register, NIMASK */ 289 s->intmask = val & 0x1f; 290 break; 291 292 case 2: /* Interrupt Enable Number Register, INTENNUM */ 293 DPRINTF("enable(%d)\n", (int)val); 294 val &= 0x3f; 295 s->enabled |= (1ULL << val); 296 break; 297 298 case 3: /* Interrupt Disable Number Register, INTDISNUM */ 299 DPRINTF("disable(%d)\n", (int)val); 300 val &= 0x3f; 301 s->enabled &= ~(1ULL << val); 302 break; 303 304 case 4: /* Interrupt Enable Number Register High */ 305 s->enabled = (s->enabled & 0xffffffffULL) | (val << 32); 306 break; 307 308 case 5: /* Interrupt Enable Number Register Low */ 309 s->enabled = (s->enabled & 0xffffffff00000000ULL) | val; 310 break; 311 312 case 6: /* Interrupt Type Register High */ 313 s->is_fiq = (s->is_fiq & 0xffffffffULL) | (val << 32); 314 break; 315 316 case 7: /* Interrupt Type Register Low */ 317 s->is_fiq = (s->is_fiq & 0xffffffff00000000ULL) | val; 318 break; 319 320 case 8: /* Normal Interrupt Priority Register 7 */ 321 case 9: /* Normal Interrupt Priority Register 6 */ 322 case 10:/* Normal Interrupt Priority Register 5 */ 323 case 11:/* Normal Interrupt Priority Register 4 */ 324 case 12:/* Normal Interrupt Priority Register 3 */ 325 case 13:/* Normal Interrupt Priority Register 2 */ 326 case 14:/* Normal Interrupt Priority Register 1 */ 327 case 15:/* Normal Interrupt Priority Register 0 */ 328 s->prio[15-(offset>>2)] = val; 329 break; 330 331 /* Read-only registers, writes ignored */ 332 case 16:/* Normal Interrupt Vector and Status register */ 333 case 17:/* Fast Interrupt vector and status register */ 334 case 18:/* Interrupt source register high */ 335 case 19:/* Interrupt source register low */ 336 return; 337 338 case 20:/* Interrupt Force Register high */ 339 s->pending = (s->pending & 0xffffffffULL) | (val << 32); 340 break; 341 342 case 21:/* Interrupt Force Register low */ 343 s->pending = (s->pending & 0xffffffff00000000ULL) | val; 344 break; 345 346 case 22:/* Normal Interrupt Pending Register High */ 347 case 23:/* Normal Interrupt Pending Register Low */ 348 case 24: /* Fast Interrupt Pending Register High */ 349 case 25: /* Fast Interrupt Pending Register Low */ 350 return; 351 352 default: 353 IPRINTF("imx_avic_write: Bad offset %x\n", (int)offset); 354 } 355 imx_avic_update(s); 356 } 357 358 static const MemoryRegionOps imx_avic_ops = { 359 .read = imx_avic_read, 360 .write = imx_avic_write, 361 .endianness = DEVICE_NATIVE_ENDIAN, 362 }; 363 364 static void imx_avic_reset(DeviceState *dev) 365 { 366 IMXAVICState *s = IMX_AVIC(dev); 367 368 s->pending = 0; 369 s->enabled = 0; 370 s->is_fiq = 0; 371 s->intmask = 0x1f; 372 s->intcntl = 0; 373 memset(s->prio, 0, sizeof s->prio); 374 } 375 376 static int imx_avic_init(SysBusDevice *sbd) 377 { 378 DeviceState *dev = DEVICE(sbd); 379 IMXAVICState *s = IMX_AVIC(dev); 380 381 memory_region_init_io(&s->iomem, OBJECT(s), &imx_avic_ops, s, 382 "imx_avic", 0x1000); 383 sysbus_init_mmio(sbd, &s->iomem); 384 385 qdev_init_gpio_in(dev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS); 386 sysbus_init_irq(sbd, &s->irq); 387 sysbus_init_irq(sbd, &s->fiq); 388 389 return 0; 390 } 391 392 393 static void imx_avic_class_init(ObjectClass *klass, void *data) 394 { 395 DeviceClass *dc = DEVICE_CLASS(klass); 396 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 397 k->init = imx_avic_init; 398 dc->vmsd = &vmstate_imx_avic; 399 dc->reset = imx_avic_reset; 400 dc->desc = "i.MX Advanced Vector Interrupt Controller"; 401 } 402 403 static const TypeInfo imx_avic_info = { 404 .name = TYPE_IMX_AVIC, 405 .parent = TYPE_SYS_BUS_DEVICE, 406 .instance_size = sizeof(IMXAVICState), 407 .class_init = imx_avic_class_init, 408 }; 409 410 static void imx_avic_register_types(void) 411 { 412 type_register_static(&imx_avic_info); 413 } 414 415 type_init(imx_avic_register_types) 416