1 /*
2 * QEMU 8259 - common bits of emulated and KVM kernel model
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/intc/i8259.h"
28 #include "hw/isa/i8259_internal.h"
29 #include "hw/qdev-properties.h"
30 #include "migration/vmstate.h"
31 #include "qapi/error.h"
32
33 static int irq_level[16];
34 static uint64_t irq_count[16];
35
pic_reset_common(PICCommonState * s)36 void pic_reset_common(PICCommonState *s)
37 {
38 s->last_irr = 0;
39 s->irr &= s->elcr;
40 s->imr = 0;
41 s->isr = 0;
42 s->priority_add = 0;
43 s->irq_base = 0;
44 s->read_reg_select = 0;
45 s->poll = 0;
46 s->special_mask = 0;
47 s->init_state = 0;
48 s->auto_eoi = 0;
49 s->rotate_on_auto_eoi = 0;
50 s->special_fully_nested_mode = 0;
51 s->init4 = 0;
52 s->single_mode = 0;
53 /* Note: ELCR and LTIM are not reset */
54 }
55
pic_dispatch_pre_save(void * opaque)56 static int pic_dispatch_pre_save(void *opaque)
57 {
58 PICCommonState *s = opaque;
59 PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
60
61 if (info->pre_save) {
62 info->pre_save(s);
63 }
64
65 return 0;
66 }
67
pic_dispatch_post_load(void * opaque,int version_id)68 static int pic_dispatch_post_load(void *opaque, int version_id)
69 {
70 PICCommonState *s = opaque;
71 PICCommonClass *info = PIC_COMMON_GET_CLASS(s);
72
73 if (info->post_load) {
74 info->post_load(s);
75 }
76 return 0;
77 }
78
pic_common_realize(DeviceState * dev,Error ** errp)79 static void pic_common_realize(DeviceState *dev, Error **errp)
80 {
81 PICCommonState *s = PIC_COMMON(dev);
82 ISADevice *isa = ISA_DEVICE(dev);
83
84 isa_register_ioport(isa, &s->base_io, s->iobase);
85 if (s->elcr_addr != -1) {
86 isa_register_ioport(isa, &s->elcr_io, s->elcr_addr);
87 }
88
89 qdev_set_legacy_instance_id(dev, s->iobase, 1);
90 }
91
i8259_init_chip(const char * name,ISABus * bus,bool master)92 ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master)
93 {
94 DeviceState *dev;
95 ISADevice *isadev;
96
97 isadev = isa_new(name);
98 dev = DEVICE(isadev);
99 qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0);
100 qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1);
101 qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde);
102 qdev_prop_set_bit(dev, "master", master);
103 isa_realize_and_unref(isadev, bus, &error_fatal);
104
105 return isadev;
106 }
107
pic_stat_update_irq(int irq,int level)108 void pic_stat_update_irq(int irq, int level)
109 {
110 if (level != irq_level[irq]) {
111 irq_level[irq] = level;
112 if (level == 1) {
113 irq_count[irq]++;
114 }
115 }
116 }
117
pic_get_statistics(InterruptStatsProvider * obj,uint64_t ** irq_counts,unsigned int * nb_irqs)118 static bool pic_get_statistics(InterruptStatsProvider *obj,
119 uint64_t **irq_counts, unsigned int *nb_irqs)
120 {
121 PICCommonState *s = PIC_COMMON(obj);
122
123 if (s->master) {
124 *irq_counts = irq_count;
125 *nb_irqs = ARRAY_SIZE(irq_count);
126 } else {
127 *irq_counts = NULL;
128 *nb_irqs = 0;
129 }
130
131 return true;
132 }
133
pic_print_info(InterruptStatsProvider * obj,GString * buf)134 static void pic_print_info(InterruptStatsProvider *obj, GString *buf)
135 {
136 PICCommonState *s = PIC_COMMON(obj);
137
138 pic_dispatch_pre_save(s);
139 g_string_append_printf(buf, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
140 "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
141 s->master ? 0 : 1, s->irr, s->imr, s->isr,
142 s->priority_add,
143 s->irq_base, s->read_reg_select, s->elcr,
144 s->special_fully_nested_mode);
145 }
146
ltim_state_needed(void * opaque)147 static bool ltim_state_needed(void *opaque)
148 {
149 PICCommonState *s = PIC_COMMON(opaque);
150
151 return !!s->ltim;
152 }
153
154 static const VMStateDescription vmstate_pic_ltim = {
155 .name = "i8259/ltim",
156 .version_id = 1,
157 .minimum_version_id = 1,
158 .needed = ltim_state_needed,
159 .fields = (const VMStateField[]) {
160 VMSTATE_UINT8(ltim, PICCommonState),
161 VMSTATE_END_OF_LIST()
162 }
163 };
164
165 static const VMStateDescription vmstate_pic_common = {
166 .name = "i8259",
167 .version_id = 1,
168 .minimum_version_id = 1,
169 .pre_save = pic_dispatch_pre_save,
170 .post_load = pic_dispatch_post_load,
171 .fields = (const VMStateField[]) {
172 VMSTATE_UINT8(last_irr, PICCommonState),
173 VMSTATE_UINT8(irr, PICCommonState),
174 VMSTATE_UINT8(imr, PICCommonState),
175 VMSTATE_UINT8(isr, PICCommonState),
176 VMSTATE_UINT8(priority_add, PICCommonState),
177 VMSTATE_UINT8(irq_base, PICCommonState),
178 VMSTATE_UINT8(read_reg_select, PICCommonState),
179 VMSTATE_UINT8(poll, PICCommonState),
180 VMSTATE_UINT8(special_mask, PICCommonState),
181 VMSTATE_UINT8(init_state, PICCommonState),
182 VMSTATE_UINT8(auto_eoi, PICCommonState),
183 VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState),
184 VMSTATE_UINT8(special_fully_nested_mode, PICCommonState),
185 VMSTATE_UINT8(init4, PICCommonState),
186 VMSTATE_UINT8(single_mode, PICCommonState),
187 VMSTATE_UINT8(elcr, PICCommonState),
188 VMSTATE_END_OF_LIST()
189 },
190 .subsections = (const VMStateDescription * const []) {
191 &vmstate_pic_ltim,
192 NULL
193 }
194 };
195
196 static Property pic_properties_common[] = {
197 DEFINE_PROP_UINT32("iobase", PICCommonState, iobase, -1),
198 DEFINE_PROP_UINT32("elcr_addr", PICCommonState, elcr_addr, -1),
199 DEFINE_PROP_UINT8("elcr_mask", PICCommonState, elcr_mask, -1),
200 DEFINE_PROP_BIT("master", PICCommonState, master, 0, false),
201 DEFINE_PROP_END_OF_LIST(),
202 };
203
pic_common_class_init(ObjectClass * klass,void * data)204 static void pic_common_class_init(ObjectClass *klass, void *data)
205 {
206 DeviceClass *dc = DEVICE_CLASS(klass);
207 InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
208
209 dc->vmsd = &vmstate_pic_common;
210 device_class_set_props(dc, pic_properties_common);
211 dc->realize = pic_common_realize;
212 /*
213 * Reason: unlike ordinary ISA devices, the PICs need additional
214 * wiring: its IRQ input lines are set up by board code, and the
215 * wiring of the slave to the master is hard-coded in device model
216 * code.
217 */
218 dc->user_creatable = false;
219 ic->get_statistics = pic_get_statistics;
220 ic->print_info = pic_print_info;
221 }
222
223 static const TypeInfo pic_common_type = {
224 .name = TYPE_PIC_COMMON,
225 .parent = TYPE_ISA_DEVICE,
226 .instance_size = sizeof(PICCommonState),
227 .class_size = sizeof(PICCommonClass),
228 .class_init = pic_common_class_init,
229 .abstract = true,
230 .interfaces = (InterfaceInfo[]) {
231 { TYPE_INTERRUPT_STATS_PROVIDER },
232 { }
233 },
234 };
235
pic_common_register_types(void)236 static void pic_common_register_types(void)
237 {
238 type_register_static(&pic_common_type);
239 }
240
241 type_init(pic_common_register_types)
242