1 /* 2 * QEMU 8259 - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2011 Jan Kiszka, Siemens AG 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "hw/i386/pc.h" 26 #include "hw/isa/i8259_internal.h" 27 28 void pic_reset_common(PICCommonState *s) 29 { 30 s->last_irr = 0; 31 s->irr &= s->elcr; 32 s->imr = 0; 33 s->isr = 0; 34 s->priority_add = 0; 35 s->irq_base = 0; 36 s->read_reg_select = 0; 37 s->poll = 0; 38 s->special_mask = 0; 39 s->init_state = 0; 40 s->auto_eoi = 0; 41 s->rotate_on_auto_eoi = 0; 42 s->special_fully_nested_mode = 0; 43 s->init4 = 0; 44 s->single_mode = 0; 45 /* Note: ELCR is not reset */ 46 } 47 48 static void pic_dispatch_pre_save(void *opaque) 49 { 50 PICCommonState *s = opaque; 51 PICCommonClass *info = PIC_COMMON_GET_CLASS(s); 52 53 if (info->pre_save) { 54 info->pre_save(s); 55 } 56 } 57 58 static int pic_dispatch_post_load(void *opaque, int version_id) 59 { 60 PICCommonState *s = opaque; 61 PICCommonClass *info = PIC_COMMON_GET_CLASS(s); 62 63 if (info->post_load) { 64 info->post_load(s); 65 } 66 return 0; 67 } 68 69 static void pic_common_realize(DeviceState *dev, Error **errp) 70 { 71 PICCommonState *s = PIC_COMMON(dev); 72 73 isa_register_ioport(NULL, &s->base_io, s->iobase); 74 if (s->elcr_addr != -1) { 75 isa_register_ioport(NULL, &s->elcr_io, s->elcr_addr); 76 } 77 78 qdev_set_legacy_instance_id(dev, s->iobase, 1); 79 } 80 81 ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master) 82 { 83 DeviceState *dev; 84 ISADevice *isadev; 85 86 isadev = isa_create(bus, name); 87 dev = DEVICE(isadev); 88 qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0); 89 qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1); 90 qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde); 91 qdev_prop_set_bit(dev, "master", master); 92 qdev_init_nofail(dev); 93 94 return isadev; 95 } 96 97 static const VMStateDescription vmstate_pic_common = { 98 .name = "i8259", 99 .version_id = 1, 100 .minimum_version_id = 1, 101 .minimum_version_id_old = 1, 102 .pre_save = pic_dispatch_pre_save, 103 .post_load = pic_dispatch_post_load, 104 .fields = (VMStateField[]) { 105 VMSTATE_UINT8(last_irr, PICCommonState), 106 VMSTATE_UINT8(irr, PICCommonState), 107 VMSTATE_UINT8(imr, PICCommonState), 108 VMSTATE_UINT8(isr, PICCommonState), 109 VMSTATE_UINT8(priority_add, PICCommonState), 110 VMSTATE_UINT8(irq_base, PICCommonState), 111 VMSTATE_UINT8(read_reg_select, PICCommonState), 112 VMSTATE_UINT8(poll, PICCommonState), 113 VMSTATE_UINT8(special_mask, PICCommonState), 114 VMSTATE_UINT8(init_state, PICCommonState), 115 VMSTATE_UINT8(auto_eoi, PICCommonState), 116 VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState), 117 VMSTATE_UINT8(special_fully_nested_mode, PICCommonState), 118 VMSTATE_UINT8(init4, PICCommonState), 119 VMSTATE_UINT8(single_mode, PICCommonState), 120 VMSTATE_UINT8(elcr, PICCommonState), 121 VMSTATE_END_OF_LIST() 122 } 123 }; 124 125 static Property pic_properties_common[] = { 126 DEFINE_PROP_UINT32("iobase", PICCommonState, iobase, -1), 127 DEFINE_PROP_UINT32("elcr_addr", PICCommonState, elcr_addr, -1), 128 DEFINE_PROP_UINT8("elcr_mask", PICCommonState, elcr_mask, -1), 129 DEFINE_PROP_BIT("master", PICCommonState, master, 0, false), 130 DEFINE_PROP_END_OF_LIST(), 131 }; 132 133 static void pic_common_class_init(ObjectClass *klass, void *data) 134 { 135 DeviceClass *dc = DEVICE_CLASS(klass); 136 137 dc->vmsd = &vmstate_pic_common; 138 dc->props = pic_properties_common; 139 dc->realize = pic_common_realize; 140 /* 141 * Reason: unlike ordinary ISA devices, the PICs need additional 142 * wiring: its IRQ input lines are set up by board code, and the 143 * wiring of the slave to the master is hard-coded in device model 144 * code. 145 */ 146 dc->cannot_instantiate_with_device_add_yet = true; 147 } 148 149 static const TypeInfo pic_common_type = { 150 .name = TYPE_PIC_COMMON, 151 .parent = TYPE_ISA_DEVICE, 152 .instance_size = sizeof(PICCommonState), 153 .class_size = sizeof(PICCommonClass), 154 .class_init = pic_common_class_init, 155 .abstract = true, 156 }; 157 158 static void pic_common_register_types(void) 159 { 160 type_register_static(&pic_common_type); 161 } 162 163 type_init(pic_common_register_types) 164