1 /* 2 * QEMU 8259 - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2011 Jan Kiszka, Siemens AG 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/i386/pc.h" 28 #include "hw/isa/i8259_internal.h" 29 #include "migration/vmstate.h" 30 #include "monitor/monitor.h" 31 32 static int irq_level[16]; 33 static uint64_t irq_count[16]; 34 35 void pic_reset_common(PICCommonState *s) 36 { 37 s->last_irr = 0; 38 s->irr &= s->elcr; 39 s->imr = 0; 40 s->isr = 0; 41 s->priority_add = 0; 42 s->irq_base = 0; 43 s->read_reg_select = 0; 44 s->poll = 0; 45 s->special_mask = 0; 46 s->init_state = 0; 47 s->auto_eoi = 0; 48 s->rotate_on_auto_eoi = 0; 49 s->special_fully_nested_mode = 0; 50 s->init4 = 0; 51 s->single_mode = 0; 52 /* Note: ELCR is not reset */ 53 } 54 55 static int pic_dispatch_pre_save(void *opaque) 56 { 57 PICCommonState *s = opaque; 58 PICCommonClass *info = PIC_COMMON_GET_CLASS(s); 59 60 if (info->pre_save) { 61 info->pre_save(s); 62 } 63 64 return 0; 65 } 66 67 static int pic_dispatch_post_load(void *opaque, int version_id) 68 { 69 PICCommonState *s = opaque; 70 PICCommonClass *info = PIC_COMMON_GET_CLASS(s); 71 72 if (info->post_load) { 73 info->post_load(s); 74 } 75 return 0; 76 } 77 78 static void pic_common_realize(DeviceState *dev, Error **errp) 79 { 80 PICCommonState *s = PIC_COMMON(dev); 81 ISADevice *isa = ISA_DEVICE(dev); 82 83 isa_register_ioport(isa, &s->base_io, s->iobase); 84 if (s->elcr_addr != -1) { 85 isa_register_ioport(isa, &s->elcr_io, s->elcr_addr); 86 } 87 88 qdev_set_legacy_instance_id(dev, s->iobase, 1); 89 } 90 91 ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master) 92 { 93 DeviceState *dev; 94 ISADevice *isadev; 95 96 isadev = isa_create(bus, name); 97 dev = DEVICE(isadev); 98 qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0); 99 qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1); 100 qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde); 101 qdev_prop_set_bit(dev, "master", master); 102 qdev_init_nofail(dev); 103 104 return isadev; 105 } 106 107 void pic_stat_update_irq(int irq, int level) 108 { 109 if (level != irq_level[irq]) { 110 irq_level[irq] = level; 111 if (level == 1) { 112 irq_count[irq]++; 113 } 114 } 115 } 116 117 bool pic_get_statistics(InterruptStatsProvider *obj, 118 uint64_t **irq_counts, unsigned int *nb_irqs) 119 { 120 PICCommonState *s = PIC_COMMON(obj); 121 122 if (s->master) { 123 *irq_counts = irq_count; 124 *nb_irqs = ARRAY_SIZE(irq_count); 125 } else { 126 *irq_counts = NULL; 127 *nb_irqs = 0; 128 } 129 130 return true; 131 } 132 133 void pic_print_info(InterruptStatsProvider *obj, Monitor *mon) 134 { 135 PICCommonState *s = PIC_COMMON(obj); 136 137 pic_dispatch_pre_save(s); 138 monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " 139 "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", 140 s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add, 141 s->irq_base, s->read_reg_select, s->elcr, 142 s->special_fully_nested_mode); 143 } 144 145 static const VMStateDescription vmstate_pic_common = { 146 .name = "i8259", 147 .version_id = 1, 148 .minimum_version_id = 1, 149 .pre_save = pic_dispatch_pre_save, 150 .post_load = pic_dispatch_post_load, 151 .fields = (VMStateField[]) { 152 VMSTATE_UINT8(last_irr, PICCommonState), 153 VMSTATE_UINT8(irr, PICCommonState), 154 VMSTATE_UINT8(imr, PICCommonState), 155 VMSTATE_UINT8(isr, PICCommonState), 156 VMSTATE_UINT8(priority_add, PICCommonState), 157 VMSTATE_UINT8(irq_base, PICCommonState), 158 VMSTATE_UINT8(read_reg_select, PICCommonState), 159 VMSTATE_UINT8(poll, PICCommonState), 160 VMSTATE_UINT8(special_mask, PICCommonState), 161 VMSTATE_UINT8(init_state, PICCommonState), 162 VMSTATE_UINT8(auto_eoi, PICCommonState), 163 VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState), 164 VMSTATE_UINT8(special_fully_nested_mode, PICCommonState), 165 VMSTATE_UINT8(init4, PICCommonState), 166 VMSTATE_UINT8(single_mode, PICCommonState), 167 VMSTATE_UINT8(elcr, PICCommonState), 168 VMSTATE_END_OF_LIST() 169 } 170 }; 171 172 static Property pic_properties_common[] = { 173 DEFINE_PROP_UINT32("iobase", PICCommonState, iobase, -1), 174 DEFINE_PROP_UINT32("elcr_addr", PICCommonState, elcr_addr, -1), 175 DEFINE_PROP_UINT8("elcr_mask", PICCommonState, elcr_mask, -1), 176 DEFINE_PROP_BIT("master", PICCommonState, master, 0, false), 177 DEFINE_PROP_END_OF_LIST(), 178 }; 179 180 static void pic_common_class_init(ObjectClass *klass, void *data) 181 { 182 DeviceClass *dc = DEVICE_CLASS(klass); 183 InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass); 184 185 dc->vmsd = &vmstate_pic_common; 186 dc->props = pic_properties_common; 187 dc->realize = pic_common_realize; 188 /* 189 * Reason: unlike ordinary ISA devices, the PICs need additional 190 * wiring: its IRQ input lines are set up by board code, and the 191 * wiring of the slave to the master is hard-coded in device model 192 * code. 193 */ 194 dc->user_creatable = false; 195 ic->get_statistics = pic_get_statistics; 196 ic->print_info = pic_print_info; 197 } 198 199 static const TypeInfo pic_common_type = { 200 .name = TYPE_PIC_COMMON, 201 .parent = TYPE_ISA_DEVICE, 202 .instance_size = sizeof(PICCommonState), 203 .class_size = sizeof(PICCommonClass), 204 .class_init = pic_common_class_init, 205 .abstract = true, 206 .interfaces = (InterfaceInfo[]) { 207 { TYPE_INTERRUPT_STATS_PROVIDER }, 208 { } 209 }, 210 }; 211 212 static void pic_common_register_types(void) 213 { 214 type_register_static(&pic_common_type); 215 } 216 217 type_init(pic_common_register_types) 218