1 /* 2 * QEMU GRLIB IRQMP Emulator 3 * 4 * (Multiprocessor and extended interrupt not supported) 5 * 6 * Copyright (c) 2010-2019 AdaCore 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/irq.h" 29 #include "hw/sysbus.h" 30 #include "cpu.h" 31 32 #include "hw/qdev-properties.h" 33 #include "hw/sparc/grlib.h" 34 35 #include "trace.h" 36 #include "qapi/error.h" 37 #include "qemu/module.h" 38 #include "qom/object.h" 39 40 #define IRQMP_MAX_CPU 16 41 #define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */ 42 43 /* Memory mapped register offsets */ 44 #define LEVEL_OFFSET 0x00 45 #define PENDING_OFFSET 0x04 46 #define FORCE0_OFFSET 0x08 47 #define CLEAR_OFFSET 0x0C 48 #define MP_STATUS_OFFSET 0x10 49 #define BROADCAST_OFFSET 0x14 50 #define MASK_OFFSET 0x40 51 #define FORCE_OFFSET 0x80 52 #define EXTENDED_OFFSET 0xC0 53 54 OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP) 55 56 typedef struct IRQMPState IRQMPState; 57 58 struct IRQMP { 59 SysBusDevice parent_obj; 60 61 MemoryRegion iomem; 62 63 IRQMPState *state; 64 qemu_irq irq; 65 }; 66 67 struct IRQMPState { 68 uint32_t level; 69 uint32_t pending; 70 uint32_t clear; 71 uint32_t broadcast; 72 73 uint32_t mask[IRQMP_MAX_CPU]; 74 uint32_t force[IRQMP_MAX_CPU]; 75 uint32_t extended[IRQMP_MAX_CPU]; 76 77 IRQMP *parent; 78 }; 79 80 static void grlib_irqmp_check_irqs(IRQMPState *state) 81 { 82 uint32_t pend = 0; 83 uint32_t level0 = 0; 84 uint32_t level1 = 0; 85 86 assert(state != NULL); 87 assert(state->parent != NULL); 88 89 /* IRQ for CPU 0 (no SMP support) */ 90 pend = (state->pending | state->force[0]) 91 & state->mask[0]; 92 93 level0 = pend & ~state->level; 94 level1 = pend & state->level; 95 96 trace_grlib_irqmp_check_irqs(state->pending, state->force[0], 97 state->mask[0], level1, level0); 98 99 /* Trigger level1 interrupt first and level0 if there is no level1 */ 100 qemu_set_irq(state->parent->irq, level1 ?: level0); 101 } 102 103 static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask) 104 { 105 /* Clear registers */ 106 state->pending &= ~mask; 107 state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */ 108 109 grlib_irqmp_check_irqs(state); 110 } 111 112 void grlib_irqmp_ack(DeviceState *dev, int intno) 113 { 114 IRQMP *irqmp = GRLIB_IRQMP(dev); 115 IRQMPState *state; 116 uint32_t mask; 117 118 state = irqmp->state; 119 assert(state != NULL); 120 121 intno &= 15; 122 mask = 1 << intno; 123 124 trace_grlib_irqmp_ack(intno); 125 126 grlib_irqmp_ack_mask(state, mask); 127 } 128 129 void grlib_irqmp_set_irq(void *opaque, int irq, int level) 130 { 131 IRQMP *irqmp = GRLIB_IRQMP(opaque); 132 IRQMPState *s; 133 int i = 0; 134 135 s = irqmp->state; 136 assert(s != NULL); 137 assert(s->parent != NULL); 138 139 140 if (level) { 141 trace_grlib_irqmp_set_irq(irq); 142 143 if (s->broadcast & 1 << irq) { 144 /* Broadcasted IRQ */ 145 for (i = 0; i < IRQMP_MAX_CPU; i++) { 146 s->force[i] |= 1 << irq; 147 } 148 } else { 149 s->pending |= 1 << irq; 150 } 151 grlib_irqmp_check_irqs(s); 152 153 } 154 } 155 156 static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr, 157 unsigned size) 158 { 159 IRQMP *irqmp = opaque; 160 IRQMPState *state; 161 162 assert(irqmp != NULL); 163 state = irqmp->state; 164 assert(state != NULL); 165 166 addr &= 0xff; 167 168 /* global registers */ 169 switch (addr) { 170 case LEVEL_OFFSET: 171 return state->level; 172 173 case PENDING_OFFSET: 174 return state->pending; 175 176 case FORCE0_OFFSET: 177 /* This register is an "alias" for the force register of CPU 0 */ 178 return state->force[0]; 179 180 case CLEAR_OFFSET: 181 case MP_STATUS_OFFSET: 182 /* Always read as 0 */ 183 return 0; 184 185 case BROADCAST_OFFSET: 186 return state->broadcast; 187 188 default: 189 break; 190 } 191 192 /* mask registers */ 193 if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) { 194 int cpu = (addr - MASK_OFFSET) / 4; 195 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 196 197 return state->mask[cpu]; 198 } 199 200 /* force registers */ 201 if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) { 202 int cpu = (addr - FORCE_OFFSET) / 4; 203 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 204 205 return state->force[cpu]; 206 } 207 208 /* extended (not supported) */ 209 if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) { 210 int cpu = (addr - EXTENDED_OFFSET) / 4; 211 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 212 213 return state->extended[cpu]; 214 } 215 216 trace_grlib_irqmp_readl_unknown(addr); 217 return 0; 218 } 219 220 static void grlib_irqmp_write(void *opaque, hwaddr addr, 221 uint64_t value, unsigned size) 222 { 223 IRQMP *irqmp = opaque; 224 IRQMPState *state; 225 226 assert(irqmp != NULL); 227 state = irqmp->state; 228 assert(state != NULL); 229 230 addr &= 0xff; 231 232 /* global registers */ 233 switch (addr) { 234 case LEVEL_OFFSET: 235 value &= 0xFFFF << 1; /* clean up the value */ 236 state->level = value; 237 return; 238 239 case PENDING_OFFSET: 240 /* Read Only */ 241 return; 242 243 case FORCE0_OFFSET: 244 /* This register is an "alias" for the force register of CPU 0 */ 245 246 value &= 0xFFFE; /* clean up the value */ 247 state->force[0] = value; 248 grlib_irqmp_check_irqs(irqmp->state); 249 return; 250 251 case CLEAR_OFFSET: 252 value &= ~1; /* clean up the value */ 253 grlib_irqmp_ack_mask(state, value); 254 return; 255 256 case MP_STATUS_OFFSET: 257 /* Read Only (no SMP support) */ 258 return; 259 260 case BROADCAST_OFFSET: 261 value &= 0xFFFE; /* clean up the value */ 262 state->broadcast = value; 263 return; 264 265 default: 266 break; 267 } 268 269 /* mask registers */ 270 if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) { 271 int cpu = (addr - MASK_OFFSET) / 4; 272 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 273 274 value &= ~1; /* clean up the value */ 275 state->mask[cpu] = value; 276 grlib_irqmp_check_irqs(irqmp->state); 277 return; 278 } 279 280 /* force registers */ 281 if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) { 282 int cpu = (addr - FORCE_OFFSET) / 4; 283 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 284 285 uint32_t force = value & 0xFFFE; 286 uint32_t clear = (value >> 16) & 0xFFFE; 287 uint32_t old = state->force[cpu]; 288 289 state->force[cpu] = (old | force) & ~clear; 290 grlib_irqmp_check_irqs(irqmp->state); 291 return; 292 } 293 294 /* extended (not supported) */ 295 if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) { 296 int cpu = (addr - EXTENDED_OFFSET) / 4; 297 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 298 299 value &= 0xF; /* clean up the value */ 300 state->extended[cpu] = value; 301 return; 302 } 303 304 trace_grlib_irqmp_writel_unknown(addr, value); 305 } 306 307 static const MemoryRegionOps grlib_irqmp_ops = { 308 .read = grlib_irqmp_read, 309 .write = grlib_irqmp_write, 310 .endianness = DEVICE_NATIVE_ENDIAN, 311 .valid = { 312 .min_access_size = 4, 313 .max_access_size = 4, 314 }, 315 }; 316 317 static void grlib_irqmp_reset(DeviceState *d) 318 { 319 IRQMP *irqmp = GRLIB_IRQMP(d); 320 assert(irqmp->state != NULL); 321 322 memset(irqmp->state, 0, sizeof *irqmp->state); 323 irqmp->state->parent = irqmp; 324 } 325 326 static void grlib_irqmp_init(Object *obj) 327 { 328 IRQMP *irqmp = GRLIB_IRQMP(obj); 329 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 330 331 qdev_init_gpio_out_named(DEVICE(obj), &irqmp->irq, "grlib-irq", 1); 332 memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp, 333 "irqmp", IRQMP_REG_SIZE); 334 335 irqmp->state = g_malloc0(sizeof *irqmp->state); 336 337 sysbus_init_mmio(dev, &irqmp->iomem); 338 } 339 340 static void grlib_irqmp_class_init(ObjectClass *klass, void *data) 341 { 342 DeviceClass *dc = DEVICE_CLASS(klass); 343 344 dc->reset = grlib_irqmp_reset; 345 } 346 347 static const TypeInfo grlib_irqmp_info = { 348 .name = TYPE_GRLIB_IRQMP, 349 .parent = TYPE_SYS_BUS_DEVICE, 350 .instance_size = sizeof(IRQMP), 351 .instance_init = grlib_irqmp_init, 352 .class_init = grlib_irqmp_class_init, 353 }; 354 355 static void grlib_irqmp_register_types(void) 356 { 357 type_register_static(&grlib_irqmp_info); 358 } 359 360 type_init(grlib_irqmp_register_types) 361