1 /* 2 * QEMU GRLIB IRQMP Emulator 3 * 4 * (Extended interrupt not supported) 5 * 6 * SPDX-License-Identifier: MIT 7 * 8 * Copyright (c) 2010-2024 AdaCore 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "hw/irq.h" 31 #include "hw/sysbus.h" 32 33 #include "hw/qdev-properties.h" 34 #include "hw/intc/grlib_irqmp.h" 35 36 #include "trace.h" 37 #include "qapi/error.h" 38 #include "qemu/module.h" 39 #include "qom/object.h" 40 41 #define IRQMP_MAX_CPU 16 42 #define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */ 43 44 /* Memory mapped register offsets */ 45 #define LEVEL_OFFSET 0x00 46 #define PENDING_OFFSET 0x04 47 #define FORCE0_OFFSET 0x08 48 #define CLEAR_OFFSET 0x0C 49 #define MP_STATUS_OFFSET 0x10 50 #define BROADCAST_OFFSET 0x14 51 #define MASK_OFFSET 0x40 52 #define FORCE_OFFSET 0x80 53 #define EXTENDED_OFFSET 0xC0 54 55 /* Multiprocessor Status Register */ 56 #define MP_STATUS_CPU_STATUS_MASK ((1 << IRQMP_MAX_CPU)-2) 57 #define MP_STATUS_NCPU_SHIFT 28 58 59 #define MAX_PILS 16 60 61 OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP) 62 63 typedef struct IRQMPState IRQMPState; 64 65 struct IRQMP { 66 SysBusDevice parent_obj; 67 68 MemoryRegion iomem; 69 70 unsigned int ncpus; 71 IRQMPState *state; 72 qemu_irq start_signal[IRQMP_MAX_CPU]; 73 qemu_irq irq; 74 }; 75 76 struct IRQMPState { 77 uint32_t level; 78 uint32_t pending; 79 uint32_t clear; 80 uint32_t mpstatus; 81 uint32_t broadcast; 82 83 uint32_t mask[IRQMP_MAX_CPU]; 84 uint32_t force[IRQMP_MAX_CPU]; 85 uint32_t extended[IRQMP_MAX_CPU]; 86 87 IRQMP *parent; 88 }; 89 90 static void grlib_irqmp_check_irqs(IRQMPState *state) 91 { 92 uint32_t pend = 0; 93 uint32_t level0 = 0; 94 uint32_t level1 = 0; 95 96 assert(state != NULL); 97 assert(state->parent != NULL); 98 99 /* IRQ for CPU 0 (no SMP support) */ 100 pend = (state->pending | state->force[0]) 101 & state->mask[0]; 102 103 level0 = pend & ~state->level; 104 level1 = pend & state->level; 105 106 trace_grlib_irqmp_check_irqs(state->pending, state->force[0], 107 state->mask[0], level1, level0); 108 109 /* Trigger level1 interrupt first and level0 if there is no level1 */ 110 qemu_set_irq(state->parent->irq, level1 ?: level0); 111 } 112 113 static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask) 114 { 115 /* Clear registers */ 116 state->pending &= ~mask; 117 state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */ 118 119 grlib_irqmp_check_irqs(state); 120 } 121 122 void grlib_irqmp_ack(DeviceState *dev, int intno) 123 { 124 IRQMP *irqmp = GRLIB_IRQMP(dev); 125 IRQMPState *state; 126 uint32_t mask; 127 128 state = irqmp->state; 129 assert(state != NULL); 130 131 intno &= 15; 132 mask = 1 << intno; 133 134 trace_grlib_irqmp_ack(intno); 135 136 grlib_irqmp_ack_mask(state, mask); 137 } 138 139 static void grlib_irqmp_set_irq(void *opaque, int irq, int level) 140 { 141 IRQMP *irqmp = GRLIB_IRQMP(opaque); 142 IRQMPState *s; 143 int i = 0; 144 145 s = irqmp->state; 146 assert(s != NULL); 147 assert(s->parent != NULL); 148 149 150 if (level) { 151 trace_grlib_irqmp_set_irq(irq); 152 153 if (s->broadcast & 1 << irq) { 154 /* Broadcasted IRQ */ 155 for (i = 0; i < IRQMP_MAX_CPU; i++) { 156 s->force[i] |= 1 << irq; 157 } 158 } else { 159 s->pending |= 1 << irq; 160 } 161 grlib_irqmp_check_irqs(s); 162 163 } 164 } 165 166 static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr, 167 unsigned size) 168 { 169 IRQMP *irqmp = opaque; 170 IRQMPState *state; 171 172 assert(irqmp != NULL); 173 state = irqmp->state; 174 assert(state != NULL); 175 176 addr &= 0xff; 177 178 /* global registers */ 179 switch (addr) { 180 case LEVEL_OFFSET: 181 return state->level; 182 183 case PENDING_OFFSET: 184 return state->pending; 185 186 case FORCE0_OFFSET: 187 /* This register is an "alias" for the force register of CPU 0 */ 188 return state->force[0]; 189 190 case CLEAR_OFFSET: 191 /* Always read as 0 */ 192 return 0; 193 194 case MP_STATUS_OFFSET: 195 return state->mpstatus; 196 197 case BROADCAST_OFFSET: 198 return state->broadcast; 199 200 default: 201 break; 202 } 203 204 /* mask registers */ 205 if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) { 206 int cpu = (addr - MASK_OFFSET) / 4; 207 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 208 209 return state->mask[cpu]; 210 } 211 212 /* force registers */ 213 if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) { 214 int cpu = (addr - FORCE_OFFSET) / 4; 215 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 216 217 return state->force[cpu]; 218 } 219 220 /* extended (not supported) */ 221 if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) { 222 int cpu = (addr - EXTENDED_OFFSET) / 4; 223 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 224 225 return state->extended[cpu]; 226 } 227 228 trace_grlib_irqmp_readl_unknown(addr); 229 return 0; 230 } 231 232 static void grlib_irqmp_write(void *opaque, hwaddr addr, 233 uint64_t value, unsigned size) 234 { 235 IRQMP *irqmp = opaque; 236 IRQMPState *state; 237 int i; 238 239 assert(irqmp != NULL); 240 state = irqmp->state; 241 assert(state != NULL); 242 243 addr &= 0xff; 244 245 /* global registers */ 246 switch (addr) { 247 case LEVEL_OFFSET: 248 value &= 0xFFFF << 1; /* clean up the value */ 249 state->level = value; 250 return; 251 252 case PENDING_OFFSET: 253 /* Read Only */ 254 return; 255 256 case FORCE0_OFFSET: 257 /* This register is an "alias" for the force register of CPU 0 */ 258 259 value &= 0xFFFE; /* clean up the value */ 260 state->force[0] = value; 261 grlib_irqmp_check_irqs(irqmp->state); 262 return; 263 264 case CLEAR_OFFSET: 265 value &= ~1; /* clean up the value */ 266 grlib_irqmp_ack_mask(state, value); 267 return; 268 269 case MP_STATUS_OFFSET: 270 /* 271 * Writing and reading operations are reversed for the CPU status. 272 * Writing "1" will start the CPU, but reading "1" means that the CPU 273 * is power-down. 274 */ 275 value &= MP_STATUS_CPU_STATUS_MASK; 276 for (i = 0; i < irqmp->ncpus; i++) { 277 if ((value >> i) & 1) { 278 qemu_set_irq(irqmp->start_signal[i], 1); 279 state->mpstatus &= ~(1 << i); 280 } 281 } 282 return; 283 284 case BROADCAST_OFFSET: 285 value &= 0xFFFE; /* clean up the value */ 286 state->broadcast = value; 287 return; 288 289 default: 290 break; 291 } 292 293 /* mask registers */ 294 if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) { 295 int cpu = (addr - MASK_OFFSET) / 4; 296 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 297 298 value &= ~1; /* clean up the value */ 299 state->mask[cpu] = value; 300 grlib_irqmp_check_irqs(irqmp->state); 301 return; 302 } 303 304 /* force registers */ 305 if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) { 306 int cpu = (addr - FORCE_OFFSET) / 4; 307 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 308 309 uint32_t force = value & 0xFFFE; 310 uint32_t clear = (value >> 16) & 0xFFFE; 311 uint32_t old = state->force[cpu]; 312 313 state->force[cpu] = (old | force) & ~clear; 314 grlib_irqmp_check_irqs(irqmp->state); 315 return; 316 } 317 318 /* extended (not supported) */ 319 if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) { 320 int cpu = (addr - EXTENDED_OFFSET) / 4; 321 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 322 323 value &= 0xF; /* clean up the value */ 324 state->extended[cpu] = value; 325 return; 326 } 327 328 trace_grlib_irqmp_writel_unknown(addr, value); 329 } 330 331 static const MemoryRegionOps grlib_irqmp_ops = { 332 .read = grlib_irqmp_read, 333 .write = grlib_irqmp_write, 334 .endianness = DEVICE_NATIVE_ENDIAN, 335 .valid = { 336 .min_access_size = 4, 337 .max_access_size = 4, 338 }, 339 }; 340 341 static void grlib_irqmp_reset(DeviceState *d) 342 { 343 IRQMP *irqmp = GRLIB_IRQMP(d); 344 assert(irqmp->state != NULL); 345 346 memset(irqmp->state, 0, sizeof *irqmp->state); 347 irqmp->state->parent = irqmp; 348 irqmp->state->mpstatus = ((irqmp->ncpus - 1) << MP_STATUS_NCPU_SHIFT) | 349 ((1 << irqmp->ncpus) - 2); 350 } 351 352 static void grlib_irqmp_realize(DeviceState *dev, Error **errp) 353 { 354 IRQMP *irqmp = GRLIB_IRQMP(dev); 355 356 if ((!irqmp->ncpus) || (irqmp->ncpus > IRQMP_MAX_CPU)) { 357 error_setg(errp, "Invalid ncpus properties: " 358 "%u, must be 0 < ncpus =< %u.", irqmp->ncpus, 359 IRQMP_MAX_CPU); 360 } 361 362 qdev_init_gpio_in(dev, grlib_irqmp_set_irq, MAX_PILS); 363 364 /* 365 * Transitionning from 0 to 1 starts the CPUs. The opposite can't 366 * happen. 367 */ 368 qdev_init_gpio_out_named(dev, irqmp->start_signal, "grlib-start-cpu", 369 IRQMP_MAX_CPU); 370 qdev_init_gpio_out_named(dev, &irqmp->irq, "grlib-irq", 1); 371 memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp, 372 "irqmp", IRQMP_REG_SIZE); 373 374 irqmp->state = g_malloc0(sizeof *irqmp->state); 375 376 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &irqmp->iomem); 377 } 378 379 static Property grlib_irqmp_properties[] = { 380 DEFINE_PROP_UINT32("ncpus", IRQMP, ncpus, 1), 381 DEFINE_PROP_END_OF_LIST(), 382 }; 383 384 static void grlib_irqmp_class_init(ObjectClass *klass, void *data) 385 { 386 DeviceClass *dc = DEVICE_CLASS(klass); 387 388 dc->realize = grlib_irqmp_realize; 389 dc->reset = grlib_irqmp_reset; 390 device_class_set_props(dc, grlib_irqmp_properties); 391 } 392 393 static const TypeInfo grlib_irqmp_info = { 394 .name = TYPE_GRLIB_IRQMP, 395 .parent = TYPE_SYS_BUS_DEVICE, 396 .instance_size = sizeof(IRQMP), 397 .class_init = grlib_irqmp_class_init, 398 }; 399 400 static void grlib_irqmp_register_types(void) 401 { 402 type_register_static(&grlib_irqmp_info); 403 } 404 405 type_init(grlib_irqmp_register_types) 406