1 /* 2 * QEMU GRLIB IRQMP Emulator 3 * 4 * (Multiprocessor and extended interrupt not supported) 5 * 6 * Copyright (c) 2010-2019 AdaCore 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/sysbus.h" 29 #include "cpu.h" 30 31 #include "hw/sparc/grlib.h" 32 33 #include "trace.h" 34 #include "qapi/error.h" 35 36 #define IRQMP_MAX_CPU 16 37 #define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */ 38 39 /* Memory mapped register offsets */ 40 #define LEVEL_OFFSET 0x00 41 #define PENDING_OFFSET 0x04 42 #define FORCE0_OFFSET 0x08 43 #define CLEAR_OFFSET 0x0C 44 #define MP_STATUS_OFFSET 0x10 45 #define BROADCAST_OFFSET 0x14 46 #define MASK_OFFSET 0x40 47 #define FORCE_OFFSET 0x80 48 #define EXTENDED_OFFSET 0xC0 49 50 #define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP) 51 52 typedef struct IRQMPState IRQMPState; 53 54 typedef struct IRQMP { 55 SysBusDevice parent_obj; 56 57 MemoryRegion iomem; 58 59 void *set_pil_in; 60 void *set_pil_in_opaque; 61 62 IRQMPState *state; 63 } IRQMP; 64 65 struct IRQMPState { 66 uint32_t level; 67 uint32_t pending; 68 uint32_t clear; 69 uint32_t broadcast; 70 71 uint32_t mask[IRQMP_MAX_CPU]; 72 uint32_t force[IRQMP_MAX_CPU]; 73 uint32_t extended[IRQMP_MAX_CPU]; 74 75 IRQMP *parent; 76 }; 77 78 static void grlib_irqmp_check_irqs(IRQMPState *state) 79 { 80 uint32_t pend = 0; 81 uint32_t level0 = 0; 82 uint32_t level1 = 0; 83 set_pil_in_fn set_pil_in; 84 85 assert(state != NULL); 86 assert(state->parent != NULL); 87 88 /* IRQ for CPU 0 (no SMP support) */ 89 pend = (state->pending | state->force[0]) 90 & state->mask[0]; 91 92 level0 = pend & ~state->level; 93 level1 = pend & state->level; 94 95 trace_grlib_irqmp_check_irqs(state->pending, state->force[0], 96 state->mask[0], level1, level0); 97 98 set_pil_in = (set_pil_in_fn)state->parent->set_pil_in; 99 100 /* Trigger level1 interrupt first and level0 if there is no level1 */ 101 if (level1 != 0) { 102 set_pil_in(state->parent->set_pil_in_opaque, level1); 103 } else { 104 set_pil_in(state->parent->set_pil_in_opaque, level0); 105 } 106 } 107 108 static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask) 109 { 110 /* Clear registers */ 111 state->pending &= ~mask; 112 state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */ 113 114 grlib_irqmp_check_irqs(state); 115 } 116 117 void grlib_irqmp_ack(DeviceState *dev, int intno) 118 { 119 IRQMP *irqmp = GRLIB_IRQMP(dev); 120 IRQMPState *state; 121 uint32_t mask; 122 123 state = irqmp->state; 124 assert(state != NULL); 125 126 intno &= 15; 127 mask = 1 << intno; 128 129 trace_grlib_irqmp_ack(intno); 130 131 grlib_irqmp_ack_mask(state, mask); 132 } 133 134 void grlib_irqmp_set_irq(void *opaque, int irq, int level) 135 { 136 IRQMP *irqmp = GRLIB_IRQMP(opaque); 137 IRQMPState *s; 138 int i = 0; 139 140 s = irqmp->state; 141 assert(s != NULL); 142 assert(s->parent != NULL); 143 144 145 if (level) { 146 trace_grlib_irqmp_set_irq(irq); 147 148 if (s->broadcast & 1 << irq) { 149 /* Broadcasted IRQ */ 150 for (i = 0; i < IRQMP_MAX_CPU; i++) { 151 s->force[i] |= 1 << irq; 152 } 153 } else { 154 s->pending |= 1 << irq; 155 } 156 grlib_irqmp_check_irqs(s); 157 158 } 159 } 160 161 static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr, 162 unsigned size) 163 { 164 IRQMP *irqmp = opaque; 165 IRQMPState *state; 166 167 assert(irqmp != NULL); 168 state = irqmp->state; 169 assert(state != NULL); 170 171 addr &= 0xff; 172 173 /* global registers */ 174 switch (addr) { 175 case LEVEL_OFFSET: 176 return state->level; 177 178 case PENDING_OFFSET: 179 return state->pending; 180 181 case FORCE0_OFFSET: 182 /* This register is an "alias" for the force register of CPU 0 */ 183 return state->force[0]; 184 185 case CLEAR_OFFSET: 186 case MP_STATUS_OFFSET: 187 /* Always read as 0 */ 188 return 0; 189 190 case BROADCAST_OFFSET: 191 return state->broadcast; 192 193 default: 194 break; 195 } 196 197 /* mask registers */ 198 if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) { 199 int cpu = (addr - MASK_OFFSET) / 4; 200 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 201 202 return state->mask[cpu]; 203 } 204 205 /* force registers */ 206 if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) { 207 int cpu = (addr - FORCE_OFFSET) / 4; 208 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 209 210 return state->force[cpu]; 211 } 212 213 /* extended (not supported) */ 214 if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) { 215 int cpu = (addr - EXTENDED_OFFSET) / 4; 216 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 217 218 return state->extended[cpu]; 219 } 220 221 trace_grlib_irqmp_readl_unknown(addr); 222 return 0; 223 } 224 225 static void grlib_irqmp_write(void *opaque, hwaddr addr, 226 uint64_t value, unsigned size) 227 { 228 IRQMP *irqmp = opaque; 229 IRQMPState *state; 230 231 assert(irqmp != NULL); 232 state = irqmp->state; 233 assert(state != NULL); 234 235 addr &= 0xff; 236 237 /* global registers */ 238 switch (addr) { 239 case LEVEL_OFFSET: 240 value &= 0xFFFF << 1; /* clean up the value */ 241 state->level = value; 242 return; 243 244 case PENDING_OFFSET: 245 /* Read Only */ 246 return; 247 248 case FORCE0_OFFSET: 249 /* This register is an "alias" for the force register of CPU 0 */ 250 251 value &= 0xFFFE; /* clean up the value */ 252 state->force[0] = value; 253 grlib_irqmp_check_irqs(irqmp->state); 254 return; 255 256 case CLEAR_OFFSET: 257 value &= ~1; /* clean up the value */ 258 grlib_irqmp_ack_mask(state, value); 259 return; 260 261 case MP_STATUS_OFFSET: 262 /* Read Only (no SMP support) */ 263 return; 264 265 case BROADCAST_OFFSET: 266 value &= 0xFFFE; /* clean up the value */ 267 state->broadcast = value; 268 return; 269 270 default: 271 break; 272 } 273 274 /* mask registers */ 275 if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) { 276 int cpu = (addr - MASK_OFFSET) / 4; 277 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 278 279 value &= ~1; /* clean up the value */ 280 state->mask[cpu] = value; 281 grlib_irqmp_check_irqs(irqmp->state); 282 return; 283 } 284 285 /* force registers */ 286 if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) { 287 int cpu = (addr - FORCE_OFFSET) / 4; 288 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 289 290 uint32_t force = value & 0xFFFE; 291 uint32_t clear = (value >> 16) & 0xFFFE; 292 uint32_t old = state->force[cpu]; 293 294 state->force[cpu] = (old | force) & ~clear; 295 grlib_irqmp_check_irqs(irqmp->state); 296 return; 297 } 298 299 /* extended (not supported) */ 300 if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) { 301 int cpu = (addr - EXTENDED_OFFSET) / 4; 302 assert(cpu >= 0 && cpu < IRQMP_MAX_CPU); 303 304 value &= 0xF; /* clean up the value */ 305 state->extended[cpu] = value; 306 return; 307 } 308 309 trace_grlib_irqmp_writel_unknown(addr, value); 310 } 311 312 static const MemoryRegionOps grlib_irqmp_ops = { 313 .read = grlib_irqmp_read, 314 .write = grlib_irqmp_write, 315 .endianness = DEVICE_NATIVE_ENDIAN, 316 .valid = { 317 .min_access_size = 4, 318 .max_access_size = 4, 319 }, 320 }; 321 322 static void grlib_irqmp_reset(DeviceState *d) 323 { 324 IRQMP *irqmp = GRLIB_IRQMP(d); 325 assert(irqmp->state != NULL); 326 327 memset(irqmp->state, 0, sizeof *irqmp->state); 328 irqmp->state->parent = irqmp; 329 } 330 331 static void grlib_irqmp_init(Object *obj) 332 { 333 IRQMP *irqmp = GRLIB_IRQMP(obj); 334 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 335 336 memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp, 337 "irqmp", IRQMP_REG_SIZE); 338 339 irqmp->state = g_malloc0(sizeof *irqmp->state); 340 341 sysbus_init_mmio(dev, &irqmp->iomem); 342 } 343 344 static void grlib_irqmp_realize(DeviceState *dev, Error **errp) 345 { 346 IRQMP *irqmp = GRLIB_IRQMP(dev); 347 348 /* Check parameters */ 349 if (irqmp->set_pil_in == NULL) { 350 error_setg(errp, "set_pil_in cannot be NULL."); 351 } 352 } 353 354 static Property grlib_irqmp_properties[] = { 355 DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in), 356 DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque), 357 DEFINE_PROP_END_OF_LIST(), 358 }; 359 360 static void grlib_irqmp_class_init(ObjectClass *klass, void *data) 361 { 362 DeviceClass *dc = DEVICE_CLASS(klass); 363 364 dc->reset = grlib_irqmp_reset; 365 dc->props = grlib_irqmp_properties; 366 /* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */ 367 dc->user_creatable = false; 368 dc->realize = grlib_irqmp_realize; 369 } 370 371 static const TypeInfo grlib_irqmp_info = { 372 .name = TYPE_GRLIB_IRQMP, 373 .parent = TYPE_SYS_BUS_DEVICE, 374 .instance_size = sizeof(IRQMP), 375 .instance_init = grlib_irqmp_init, 376 .class_init = grlib_irqmp_class_init, 377 }; 378 379 static void grlib_irqmp_register_types(void) 380 { 381 type_register_static(&grlib_irqmp_info); 382 } 383 384 type_init(grlib_irqmp_register_types) 385