1 /* 2 * ARM GICv3 support - internal interfaces 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Copyright (c) 2015 Huawei. 6 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 7 * Written by Peter Maydell 8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef QEMU_ARM_GICV3_INTERNAL_H 25 #define QEMU_ARM_GICV3_INTERNAL_H 26 27 #include "hw/registerfields.h" 28 #include "hw/intc/arm_gicv3_common.h" 29 30 /* Distributor registers, as offsets from the distributor base address */ 31 #define GICD_CTLR 0x0000 32 #define GICD_TYPER 0x0004 33 #define GICD_IIDR 0x0008 34 #define GICD_STATUSR 0x0010 35 #define GICD_SETSPI_NSR 0x0040 36 #define GICD_CLRSPI_NSR 0x0048 37 #define GICD_SETSPI_SR 0x0050 38 #define GICD_CLRSPI_SR 0x0058 39 #define GICD_SEIR 0x0068 40 #define GICD_IGROUPR 0x0080 41 #define GICD_ISENABLER 0x0100 42 #define GICD_ICENABLER 0x0180 43 #define GICD_ISPENDR 0x0200 44 #define GICD_ICPENDR 0x0280 45 #define GICD_ISACTIVER 0x0300 46 #define GICD_ICACTIVER 0x0380 47 #define GICD_IPRIORITYR 0x0400 48 #define GICD_ITARGETSR 0x0800 49 #define GICD_ICFGR 0x0C00 50 #define GICD_IGRPMODR 0x0D00 51 #define GICD_NSACR 0x0E00 52 #define GICD_SGIR 0x0F00 53 #define GICD_CPENDSGIR 0x0F10 54 #define GICD_SPENDSGIR 0x0F20 55 #define GICD_IROUTER 0x6000 56 #define GICD_IDREGS 0xFFD0 57 58 /* GICD_CTLR fields */ 59 #define GICD_CTLR_EN_GRP0 (1U << 0) 60 #define GICD_CTLR_EN_GRP1NS (1U << 1) /* GICv3 5.3.20 */ 61 #define GICD_CTLR_EN_GRP1S (1U << 2) 62 #define GICD_CTLR_EN_GRP1_ALL (GICD_CTLR_EN_GRP1NS | GICD_CTLR_EN_GRP1S) 63 /* Bit 4 is ARE if the system doesn't support TrustZone, ARE_S otherwise */ 64 #define GICD_CTLR_ARE (1U << 4) 65 #define GICD_CTLR_ARE_S (1U << 4) 66 #define GICD_CTLR_ARE_NS (1U << 5) 67 #define GICD_CTLR_DS (1U << 6) 68 #define GICD_CTLR_E1NWF (1U << 7) 69 #define GICD_CTLR_RWP (1U << 31) 70 71 #define GICD_TYPER_NMI_SHIFT 9 72 #define GICD_TYPER_LPIS_SHIFT 17 73 74 /* 16 bits EventId */ 75 #define GICD_TYPER_IDBITS 0xf 76 77 /* 78 * Redistributor frame offsets from RD_base 79 */ 80 #define GICR_SGI_OFFSET 0x10000 81 #define GICR_VLPI_OFFSET 0x20000 82 83 /* 84 * Redistributor registers, offsets from RD_base 85 */ 86 #define GICR_CTLR 0x0000 87 #define GICR_IIDR 0x0004 88 #define GICR_TYPER 0x0008 89 #define GICR_STATUSR 0x0010 90 #define GICR_WAKER 0x0014 91 #define GICR_SETLPIR 0x0040 92 #define GICR_CLRLPIR 0x0048 93 #define GICR_PROPBASER 0x0070 94 #define GICR_PENDBASER 0x0078 95 #define GICR_INVLPIR 0x00A0 96 #define GICR_INVALLR 0x00B0 97 #define GICR_SYNCR 0x00C0 98 #define GICR_IDREGS 0xFFD0 99 100 /* SGI and PPI Redistributor registers, offsets from RD_base */ 101 #define GICR_IGROUPR0 (GICR_SGI_OFFSET + 0x0080) 102 #define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100) 103 #define GICR_ICENABLER0 (GICR_SGI_OFFSET + 0x0180) 104 #define GICR_ISPENDR0 (GICR_SGI_OFFSET + 0x0200) 105 #define GICR_ICPENDR0 (GICR_SGI_OFFSET + 0x0280) 106 #define GICR_ISACTIVER0 (GICR_SGI_OFFSET + 0x0300) 107 #define GICR_ICACTIVER0 (GICR_SGI_OFFSET + 0x0380) 108 #define GICR_IPRIORITYR (GICR_SGI_OFFSET + 0x0400) 109 #define GICR_ICFGR0 (GICR_SGI_OFFSET + 0x0C00) 110 #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04) 111 #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) 112 #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) 113 #define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80) 114 115 /* VLPI redistributor registers, offsets from VLPI_base */ 116 #define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70) 117 #define GICR_VPENDBASER (GICR_VLPI_OFFSET + 0x78) 118 119 #define GICR_CTLR_ENABLE_LPIS (1U << 0) 120 #define GICR_CTLR_CES (1U << 1) 121 #define GICR_CTLR_RWP (1U << 3) 122 #define GICR_CTLR_DPG0 (1U << 24) 123 #define GICR_CTLR_DPG1NS (1U << 25) 124 #define GICR_CTLR_DPG1S (1U << 26) 125 #define GICR_CTLR_UWP (1U << 31) 126 127 #define GICR_TYPER_PLPIS (1U << 0) 128 #define GICR_TYPER_VLPIS (1U << 1) 129 #define GICR_TYPER_DIRECTLPI (1U << 3) 130 #define GICR_TYPER_LAST (1U << 4) 131 #define GICR_TYPER_DPGS (1U << 5) 132 #define GICR_TYPER_PROCNUM (0xFFFFU << 8) 133 #define GICR_TYPER_COMMONLPIAFF (0x3 << 24) 134 #define GICR_TYPER_AFFINITYVALUE (0xFFFFFFFFULL << 32) 135 136 #define GICR_WAKER_ProcessorSleep (1U << 1) 137 #define GICR_WAKER_ChildrenAsleep (1U << 2) 138 139 FIELD(GICR_PROPBASER, IDBITS, 0, 5) 140 FIELD(GICR_PROPBASER, INNERCACHE, 7, 3) 141 FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2) 142 FIELD(GICR_PROPBASER, PHYADDR, 12, 40) 143 FIELD(GICR_PROPBASER, OUTERCACHE, 56, 3) 144 145 FIELD(GICR_PENDBASER, INNERCACHE, 7, 3) 146 FIELD(GICR_PENDBASER, SHAREABILITY, 10, 2) 147 FIELD(GICR_PENDBASER, PHYADDR, 16, 36) 148 FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3) 149 FIELD(GICR_PENDBASER, PTZ, 62, 1) 150 151 #define GICR_PROPBASER_IDBITS_THRESHOLD 0xd 152 153 /* These are the GICv4 VPROPBASER and VPENDBASER layouts; v4.1 is different */ 154 FIELD(GICR_VPROPBASER, IDBITS, 0, 5) 155 FIELD(GICR_VPROPBASER, INNERCACHE, 7, 3) 156 FIELD(GICR_VPROPBASER, SHAREABILITY, 10, 2) 157 FIELD(GICR_VPROPBASER, PHYADDR, 12, 40) 158 FIELD(GICR_VPROPBASER, OUTERCACHE, 56, 3) 159 160 FIELD(GICR_VPENDBASER, INNERCACHE, 7, 3) 161 FIELD(GICR_VPENDBASER, SHAREABILITY, 10, 2) 162 FIELD(GICR_VPENDBASER, PHYADDR, 16, 36) 163 FIELD(GICR_VPENDBASER, OUTERCACHE, 56, 3) 164 FIELD(GICR_VPENDBASER, DIRTY, 60, 1) 165 FIELD(GICR_VPENDBASER, PENDINGLAST, 61, 1) 166 FIELD(GICR_VPENDBASER, IDAI, 62, 1) 167 FIELD(GICR_VPENDBASER, VALID, 63, 1) 168 169 #define ICC_CTLR_EL1_CBPR (1U << 0) 170 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 171 #define ICC_CTLR_EL1_PMHE (1U << 6) 172 #define ICC_CTLR_EL1_PRIBITS_SHIFT 8 173 #define ICC_CTLR_EL1_PRIBITS_MASK (7U << ICC_CTLR_EL1_PRIBITS_SHIFT) 174 #define ICC_CTLR_EL1_IDBITS_SHIFT 11 175 #define ICC_CTLR_EL1_SEIS (1U << 14) 176 #define ICC_CTLR_EL1_A3V (1U << 15) 177 178 #define ICC_PMR_PRIORITY_MASK 0xff 179 #define ICC_BPR_BINARYPOINT_MASK 0x07 180 #define ICC_IGRPEN_ENABLE 0x01 181 182 #define ICC_CTLR_EL3_CBPR_EL1S (1U << 0) 183 #define ICC_CTLR_EL3_CBPR_EL1NS (1U << 1) 184 #define ICC_CTLR_EL3_EOIMODE_EL3 (1U << 2) 185 #define ICC_CTLR_EL3_EOIMODE_EL1S (1U << 3) 186 #define ICC_CTLR_EL3_EOIMODE_EL1NS (1U << 4) 187 #define ICC_CTLR_EL3_RM (1U << 5) 188 #define ICC_CTLR_EL3_PMHE (1U << 6) 189 #define ICC_CTLR_EL3_PRIBITS_SHIFT 8 190 #define ICC_CTLR_EL3_IDBITS_SHIFT 11 191 #define ICC_CTLR_EL3_SEIS (1U << 14) 192 #define ICC_CTLR_EL3_A3V (1U << 15) 193 #define ICC_CTLR_EL3_NDS (1U << 17) 194 195 #define ICH_VMCR_EL2_VENG0_SHIFT 0 196 #define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT) 197 #define ICH_VMCR_EL2_VENG1_SHIFT 1 198 #define ICH_VMCR_EL2_VENG1 (1U << ICH_VMCR_EL2_VENG1_SHIFT) 199 #define ICH_VMCR_EL2_VACKCTL (1U << 2) 200 #define ICH_VMCR_EL2_VFIQEN (1U << 3) 201 #define ICH_VMCR_EL2_VCBPR_SHIFT 4 202 #define ICH_VMCR_EL2_VCBPR (1U << ICH_VMCR_EL2_VCBPR_SHIFT) 203 #define ICH_VMCR_EL2_VEOIM_SHIFT 9 204 #define ICH_VMCR_EL2_VEOIM (1U << ICH_VMCR_EL2_VEOIM_SHIFT) 205 #define ICH_VMCR_EL2_VBPR1_SHIFT 18 206 #define ICH_VMCR_EL2_VBPR1_LENGTH 3 207 #define ICH_VMCR_EL2_VBPR1_MASK (0x7U << ICH_VMCR_EL2_VBPR1_SHIFT) 208 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 209 #define ICH_VMCR_EL2_VBPR0_LENGTH 3 210 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT) 211 #define ICH_VMCR_EL2_VPMR_SHIFT 24 212 #define ICH_VMCR_EL2_VPMR_LENGTH 8 213 #define ICH_VMCR_EL2_VPMR_MASK (0xffU << ICH_VMCR_EL2_VPMR_SHIFT) 214 215 #define ICH_HCR_EL2_EN (1U << 0) 216 #define ICH_HCR_EL2_UIE (1U << 1) 217 #define ICH_HCR_EL2_LRENPIE (1U << 2) 218 #define ICH_HCR_EL2_NPIE (1U << 3) 219 #define ICH_HCR_EL2_VGRP0EIE (1U << 4) 220 #define ICH_HCR_EL2_VGRP0DIE (1U << 5) 221 #define ICH_HCR_EL2_VGRP1EIE (1U << 6) 222 #define ICH_HCR_EL2_VGRP1DIE (1U << 7) 223 #define ICH_HCR_EL2_TC (1U << 10) 224 #define ICH_HCR_EL2_TALL0 (1U << 11) 225 #define ICH_HCR_EL2_TALL1 (1U << 12) 226 #define ICH_HCR_EL2_TSEI (1U << 13) 227 #define ICH_HCR_EL2_TDIR (1U << 14) 228 #define ICH_HCR_EL2_EOICOUNT_SHIFT 27 229 #define ICH_HCR_EL2_EOICOUNT_LENGTH 5 230 #define ICH_HCR_EL2_EOICOUNT_MASK (0x1fU << ICH_HCR_EL2_EOICOUNT_SHIFT) 231 232 #define ICH_LR_EL2_VINTID_SHIFT 0 233 #define ICH_LR_EL2_VINTID_LENGTH 32 234 #define ICH_LR_EL2_VINTID_MASK (0xffffffffULL << ICH_LR_EL2_VINTID_SHIFT) 235 #define ICH_LR_EL2_PINTID_SHIFT 32 236 #define ICH_LR_EL2_PINTID_LENGTH 10 237 #define ICH_LR_EL2_PINTID_MASK (0x3ffULL << ICH_LR_EL2_PINTID_SHIFT) 238 /* Note that EOI shares with the top bit of the pINTID field */ 239 #define ICH_LR_EL2_EOI (1ULL << 41) 240 #define ICH_LR_EL2_PRIORITY_SHIFT 48 241 #define ICH_LR_EL2_PRIORITY_LENGTH 8 242 #define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT) 243 #define ICH_LR_EL2_GROUP (1ULL << 60) 244 #define ICH_LR_EL2_HW (1ULL << 61) 245 #define ICH_LR_EL2_STATE_SHIFT 62 246 #define ICH_LR_EL2_STATE_LENGTH 2 247 #define ICH_LR_EL2_STATE_MASK (3ULL << ICH_LR_EL2_STATE_SHIFT) 248 /* values for the state field: */ 249 #define ICH_LR_EL2_STATE_INVALID 0 250 #define ICH_LR_EL2_STATE_PENDING 1 251 #define ICH_LR_EL2_STATE_ACTIVE 2 252 #define ICH_LR_EL2_STATE_ACTIVE_PENDING 3 253 #define ICH_LR_EL2_STATE_PENDING_BIT (1ULL << ICH_LR_EL2_STATE_SHIFT) 254 #define ICH_LR_EL2_STATE_ACTIVE_BIT (2ULL << ICH_LR_EL2_STATE_SHIFT) 255 256 #define ICH_MISR_EL2_EOI (1U << 0) 257 #define ICH_MISR_EL2_U (1U << 1) 258 #define ICH_MISR_EL2_LRENP (1U << 2) 259 #define ICH_MISR_EL2_NP (1U << 3) 260 #define ICH_MISR_EL2_VGRP0E (1U << 4) 261 #define ICH_MISR_EL2_VGRP0D (1U << 5) 262 #define ICH_MISR_EL2_VGRP1E (1U << 6) 263 #define ICH_MISR_EL2_VGRP1D (1U << 7) 264 265 #define ICH_VTR_EL2_LISTREGS_SHIFT 0 266 #define ICH_VTR_EL2_TDS (1U << 19) 267 #define ICH_VTR_EL2_NV4 (1U << 20) 268 #define ICH_VTR_EL2_A3V (1U << 21) 269 #define ICH_VTR_EL2_SEIS (1U << 22) 270 #define ICH_VTR_EL2_IDBITS_SHIFT 23 271 #define ICH_VTR_EL2_PREBITS_SHIFT 26 272 #define ICH_VTR_EL2_PRIBITS_SHIFT 29 273 274 /* ITS Registers */ 275 276 FIELD(GITS_BASER, SIZE, 0, 8) 277 FIELD(GITS_BASER, PAGESIZE, 8, 2) 278 FIELD(GITS_BASER, SHAREABILITY, 10, 2) 279 FIELD(GITS_BASER, PHYADDR, 12, 36) 280 FIELD(GITS_BASER, PHYADDRL_64K, 16, 32) 281 FIELD(GITS_BASER, PHYADDRH_64K, 12, 4) 282 FIELD(GITS_BASER, ENTRYSIZE, 48, 5) 283 FIELD(GITS_BASER, OUTERCACHE, 53, 3) 284 FIELD(GITS_BASER, TYPE, 56, 3) 285 FIELD(GITS_BASER, INNERCACHE, 59, 3) 286 FIELD(GITS_BASER, INDIRECT, 62, 1) 287 FIELD(GITS_BASER, VALID, 63, 1) 288 289 FIELD(GITS_CBASER, SIZE, 0, 8) 290 FIELD(GITS_CBASER, SHAREABILITY, 10, 2) 291 FIELD(GITS_CBASER, PHYADDR, 12, 40) 292 FIELD(GITS_CBASER, OUTERCACHE, 53, 3) 293 FIELD(GITS_CBASER, INNERCACHE, 59, 3) 294 FIELD(GITS_CBASER, VALID, 63, 1) 295 296 FIELD(GITS_CREADR, STALLED, 0, 1) 297 FIELD(GITS_CREADR, OFFSET, 5, 15) 298 299 FIELD(GITS_CWRITER, RETRY, 0, 1) 300 FIELD(GITS_CWRITER, OFFSET, 5, 15) 301 302 FIELD(GITS_CTLR, ENABLED, 0, 1) 303 FIELD(GITS_CTLR, QUIESCENT, 31, 1) 304 305 FIELD(GITS_TYPER, PHYSICAL, 0, 1) 306 FIELD(GITS_TYPER, VIRTUAL, 1, 1) 307 FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4) 308 FIELD(GITS_TYPER, IDBITS, 8, 5) 309 FIELD(GITS_TYPER, DEVBITS, 13, 5) 310 FIELD(GITS_TYPER, SEIS, 18, 1) 311 FIELD(GITS_TYPER, PTA, 19, 1) 312 FIELD(GITS_TYPER, CIDBITS, 32, 4) 313 FIELD(GITS_TYPER, CIL, 36, 1) 314 FIELD(GITS_TYPER, VMOVP, 37, 1) 315 316 #define GITS_IDREGS 0xFFD0 317 318 #define GITS_BASER_RO_MASK (R_GITS_BASER_ENTRYSIZE_MASK | \ 319 R_GITS_BASER_TYPE_MASK) 320 321 #define GITS_BASER_PAGESIZE_4K 0 322 #define GITS_BASER_PAGESIZE_16K 1 323 #define GITS_BASER_PAGESIZE_64K 2 324 325 #define GITS_BASER_TYPE_DEVICE 1ULL 326 #define GITS_BASER_TYPE_VPE 2ULL 327 #define GITS_BASER_TYPE_COLLECTION 4ULL 328 329 #define GITS_PAGE_SIZE_4K 0x1000 330 #define GITS_PAGE_SIZE_16K 0x4000 331 #define GITS_PAGE_SIZE_64K 0x10000 332 333 #define L1TABLE_ENTRY_SIZE 8 334 335 #define LPI_CTE_ENABLED TABLE_ENTRY_VALID_MASK 336 #define LPI_PRIORITY_MASK 0xfc 337 338 #define GITS_CMDQ_ENTRY_WORDS 4 339 #define GITS_CMDQ_ENTRY_SIZE (GITS_CMDQ_ENTRY_WORDS * sizeof(uint64_t)) 340 341 #define CMD_MASK 0xff 342 343 /* ITS Commands */ 344 #define GITS_CMD_MOVI 0x01 345 #define GITS_CMD_INT 0x03 346 #define GITS_CMD_CLEAR 0x04 347 #define GITS_CMD_SYNC 0x05 348 #define GITS_CMD_MAPD 0x08 349 #define GITS_CMD_MAPC 0x09 350 #define GITS_CMD_MAPTI 0x0A 351 #define GITS_CMD_MAPI 0x0B 352 #define GITS_CMD_INV 0x0C 353 #define GITS_CMD_INVALL 0x0D 354 #define GITS_CMD_MOVALL 0x0E 355 #define GITS_CMD_DISCARD 0x0F 356 #define GITS_CMD_VMOVI 0x21 357 #define GITS_CMD_VMOVP 0x22 358 #define GITS_CMD_VSYNC 0x25 359 #define GITS_CMD_VMAPP 0x29 360 #define GITS_CMD_VMAPTI 0x2A 361 #define GITS_CMD_VMAPI 0x2B 362 #define GITS_CMD_VINVALL 0x2D 363 364 /* MAPC command fields */ 365 #define ICID_LENGTH 16 366 #define ICID_MASK ((1U << ICID_LENGTH) - 1) 367 FIELD(MAPC, RDBASE, 16, 32) 368 369 #define RDBASE_PROCNUM_LENGTH 16 370 #define RDBASE_PROCNUM_MASK ((1ULL << RDBASE_PROCNUM_LENGTH) - 1) 371 372 /* MAPD command fields */ 373 #define ITTADDR_LENGTH 44 374 #define ITTADDR_SHIFT 8 375 #define ITTADDR_MASK MAKE_64BIT_MASK(ITTADDR_SHIFT, ITTADDR_LENGTH) 376 #define SIZE_MASK 0x1f 377 378 /* MAPI command fields */ 379 #define EVENTID_MASK ((1ULL << 32) - 1) 380 381 /* MAPTI command fields */ 382 #define pINTID_SHIFT 32 383 #define pINTID_MASK MAKE_64BIT_MASK(32, 32) 384 385 #define DEVID_SHIFT 32 386 #define DEVID_MASK MAKE_64BIT_MASK(32, 32) 387 388 #define VALID_SHIFT 63 389 #define CMD_FIELD_VALID_MASK (1ULL << VALID_SHIFT) 390 #define L2_TABLE_VALID_MASK CMD_FIELD_VALID_MASK 391 #define TABLE_ENTRY_VALID_MASK (1ULL << 0) 392 393 /* MOVALL command fields */ 394 FIELD(MOVALL_2, RDBASE1, 16, 36) 395 FIELD(MOVALL_3, RDBASE2, 16, 36) 396 397 /* MOVI command fields */ 398 FIELD(MOVI_0, DEVICEID, 32, 32) 399 FIELD(MOVI_1, EVENTID, 0, 32) 400 FIELD(MOVI_2, ICID, 0, 16) 401 402 /* INV command fields */ 403 FIELD(INV_0, DEVICEID, 32, 32) 404 FIELD(INV_1, EVENTID, 0, 32) 405 406 /* VMAPI, VMAPTI command fields */ 407 FIELD(VMAPTI_0, DEVICEID, 32, 32) 408 FIELD(VMAPTI_1, EVENTID, 0, 32) 409 FIELD(VMAPTI_1, VPEID, 32, 16) 410 FIELD(VMAPTI_2, VINTID, 0, 32) /* VMAPTI only */ 411 FIELD(VMAPTI_2, DOORBELL, 32, 32) 412 413 /* VMAPP command fields */ 414 FIELD(VMAPP_0, ALLOC, 8, 1) /* GICv4.1 only */ 415 FIELD(VMAPP_0, PTZ, 9, 1) /* GICv4.1 only */ 416 FIELD(VMAPP_0, VCONFADDR, 16, 36) /* GICv4.1 only */ 417 FIELD(VMAPP_1, DEFAULT_DOORBELL, 0, 32) /* GICv4.1 only */ 418 FIELD(VMAPP_1, VPEID, 32, 16) 419 FIELD(VMAPP_2, RDBASE, 16, 36) 420 FIELD(VMAPP_2, V, 63, 1) 421 FIELD(VMAPP_3, VPTSIZE, 0, 8) /* For GICv4.0, bits [7:6] are RES0 */ 422 FIELD(VMAPP_3, VPTADDR, 16, 36) 423 424 /* VMOVP command fields */ 425 FIELD(VMOVP_0, SEQNUM, 32, 16) /* not used for GITS_TYPER.VMOVP == 1 */ 426 FIELD(VMOVP_1, ITSLIST, 0, 16) /* not used for GITS_TYPER.VMOVP == 1 */ 427 FIELD(VMOVP_1, VPEID, 32, 16) 428 FIELD(VMOVP_2, RDBASE, 16, 36) 429 FIELD(VMOVP_2, DB, 63, 1) /* GICv4.1 only */ 430 FIELD(VMOVP_3, DEFAULT_DOORBELL, 0, 32) /* GICv4.1 only */ 431 432 /* VMOVI command fields */ 433 FIELD(VMOVI_0, DEVICEID, 32, 32) 434 FIELD(VMOVI_1, EVENTID, 0, 32) 435 FIELD(VMOVI_1, VPEID, 32, 16) 436 FIELD(VMOVI_2, D, 0, 1) 437 FIELD(VMOVI_2, DOORBELL, 32, 32) 438 439 /* VINVALL command fields */ 440 FIELD(VINVALL_1, VPEID, 32, 16) 441 442 /* 443 * 12 bytes Interrupt translation Table Entry size 444 * as per Table 5.3 in GICv3 spec 445 * ITE Lower 8 Bytes 446 * Bits: | 63 ... 48 | 47 ... 32 | 31 ... 26 | 25 ... 2 | 1 | 0 | 447 * Values: | vPEID | ICID | unused | IntNum | IntType | Valid | 448 * ITE Higher 4 Bytes 449 * Bits: | 31 ... 25 | 24 ... 0 | 450 * Values: | unused | Doorbell | 451 * (When Doorbell is unused, as it always is for INTYPE_PHYSICAL, 452 * the value of that field in memory cannot be relied upon -- older 453 * versions of QEMU did not correctly write to that memory.) 454 */ 455 #define ITS_ITT_ENTRY_SIZE 0xC 456 457 FIELD(ITE_L, VALID, 0, 1) 458 FIELD(ITE_L, INTTYPE, 1, 1) 459 FIELD(ITE_L, INTID, 2, 24) 460 FIELD(ITE_L, ICID, 32, 16) 461 FIELD(ITE_L, VPEID, 48, 16) 462 FIELD(ITE_H, DOORBELL, 0, 24) 463 464 /* Possible values for ITE_L INTTYPE */ 465 #define ITE_INTTYPE_VIRTUAL 0 466 #define ITE_INTTYPE_PHYSICAL 1 467 468 /* 16 bits EventId */ 469 #define ITS_IDBITS GICD_TYPER_IDBITS 470 471 /* 16 bits DeviceId */ 472 #define ITS_DEVBITS 0xF 473 474 /* 16 bits CollectionId */ 475 #define ITS_CIDBITS 0xF 476 477 /* 478 * 8 bytes Device Table Entry size 479 * Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits 480 */ 481 #define GITS_DTE_SIZE (0x8ULL) 482 483 FIELD(DTE, VALID, 0, 1) 484 FIELD(DTE, SIZE, 1, 5) 485 FIELD(DTE, ITTADDR, 6, 44) 486 487 /* 488 * 8 bytes Collection Table Entry size 489 * Valid = 1 bit, RDBase = 16 bits 490 */ 491 #define GITS_CTE_SIZE (0x8ULL) 492 FIELD(CTE, VALID, 0, 1) 493 FIELD(CTE, RDBASE, 1, RDBASE_PROCNUM_LENGTH) 494 495 /* 496 * 8 bytes VPE table entry size: 497 * Valid = 1 bit, VPTsize = 5 bits, VPTaddr = 36 bits, RDbase = 16 bits 498 * 499 * Field sizes for Valid and size are mandated; field sizes for RDbase 500 * and VPT_addr are IMPDEF. 501 */ 502 #define GITS_VPE_SIZE 0x8ULL 503 504 FIELD(VTE, VALID, 0, 1) 505 FIELD(VTE, VPTSIZE, 1, 5) 506 FIELD(VTE, VPTADDR, 6, 36) 507 FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH) 508 509 /* Special interrupt IDs */ 510 #define INTID_SECURE 1020 511 #define INTID_NONSECURE 1021 512 #define INTID_SPURIOUS 1023 513 514 /* Functions internal to the emulated GICv3 */ 515 516 /** 517 * gicv3_redist_size: 518 * @s: GICv3State 519 * 520 * Return the size of the redistributor register frame in bytes 521 * (which depends on what GIC version this is) 522 */ 523 static inline int gicv3_redist_size(GICv3State *s) 524 { 525 /* 526 * Redistributor size is controlled by the redistributor GICR_TYPER.VLPIS. 527 * It's the same for every redistributor in the GIC, so arbitrarily 528 * use the register field in the first one. 529 */ 530 if (s->cpu[0].gicr_typer & GICR_TYPER_VLPIS) { 531 return GICV4_REDIST_SIZE; 532 } else { 533 return GICV3_REDIST_SIZE; 534 } 535 } 536 537 /** 538 * gicv3_intid_is_special: 539 * @intid: interrupt ID 540 * 541 * Return true if @intid is a special interrupt ID (1020 to 542 * 1023 inclusive). This corresponds to the GIC spec pseudocode 543 * IsSpecial() function. 544 */ 545 static inline bool gicv3_intid_is_special(int intid) 546 { 547 return intid >= INTID_SECURE && intid <= INTID_SPURIOUS; 548 } 549 550 /** 551 * gicv3_redist_update: 552 * @cs: GICv3CPUState for this redistributor 553 * 554 * Recalculate the highest priority pending interrupt after a 555 * change to redistributor state, and inform the CPU accordingly. 556 */ 557 void gicv3_redist_update(GICv3CPUState *cs); 558 559 /** 560 * gicv3_update: 561 * @s: GICv3State 562 * @start: first interrupt whose state changed 563 * @len: length of the range of interrupts whose state changed 564 * 565 * Recalculate the highest priority pending interrupts after a 566 * change to the distributor state affecting @len interrupts 567 * starting at @start, and inform the CPUs accordingly. 568 */ 569 void gicv3_update(GICv3State *s, int start, int len); 570 571 /** 572 * gicv3_full_update_noirqset: 573 * @s: GICv3State 574 * 575 * Recalculate the cached information about highest priority 576 * pending interrupts, but don't inform the CPUs. This should be 577 * called after an incoming migration has loaded new state. 578 */ 579 void gicv3_full_update_noirqset(GICv3State *s); 580 581 /** 582 * gicv3_full_update: 583 * @s: GICv3State 584 * 585 * Recalculate the highest priority pending interrupts after 586 * a change that could affect the status of all interrupts, 587 * and inform the CPUs accordingly. 588 */ 589 void gicv3_full_update(GICv3State *s); 590 MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, 591 unsigned size, MemTxAttrs attrs); 592 MemTxResult gicv3_dist_write(void *opaque, hwaddr addr, uint64_t data, 593 unsigned size, MemTxAttrs attrs); 594 MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, 595 unsigned size, MemTxAttrs attrs); 596 MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, 597 unsigned size, MemTxAttrs attrs); 598 void gicv3_dist_set_irq(GICv3State *s, int irq, int level); 599 void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level); 600 void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level); 601 /** 602 * gicv3_redist_process_vlpi: 603 * @cs: GICv3CPUState 604 * @irq: (virtual) interrupt number 605 * @vptaddr: (guest) address of VLPI table 606 * @doorbell: doorbell (physical) interrupt number (1023 for "no doorbell") 607 * @level: level to set @irq to 608 * 609 * Process a virtual LPI being directly injected by the ITS. This function 610 * will update the VLPI table specified by @vptaddr and @vptsize. If the 611 * vCPU corresponding to that VLPI table is currently running on 612 * the CPU associated with this redistributor, directly inject the VLPI 613 * @irq. If the vCPU is not running on this CPU, raise the doorbell 614 * interrupt instead. 615 */ 616 void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr, 617 int doorbell, int level); 618 /** 619 * gicv3_redist_vlpi_pending: 620 * @cs: GICv3CPUState 621 * @irq: (virtual) interrupt number 622 * @level: level to set @irq to 623 * 624 * Set/clear the pending status of a virtual LPI in the vLPI table 625 * that this redistributor is currently using. (The difference between 626 * this and gicv3_redist_process_vlpi() is that this is called from 627 * the cpuif and does not need to do the not-running-on-this-vcpu checks.) 628 */ 629 void gicv3_redist_vlpi_pending(GICv3CPUState *cs, int irq, int level); 630 631 void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level); 632 /** 633 * gicv3_redist_update_lpi: 634 * @cs: GICv3CPUState 635 * 636 * Scan the LPI pending table and recalculate the highest priority 637 * pending LPI and also the overall highest priority pending interrupt. 638 */ 639 void gicv3_redist_update_lpi(GICv3CPUState *cs); 640 /** 641 * gicv3_redist_update_lpi_only: 642 * @cs: GICv3CPUState 643 * 644 * Scan the LPI pending table and recalculate cs->hpplpi only, 645 * without calling gicv3_redist_update() to recalculate the overall 646 * highest priority pending interrupt. This should be called after 647 * an incoming migration has loaded new state. 648 */ 649 void gicv3_redist_update_lpi_only(GICv3CPUState *cs); 650 /** 651 * gicv3_redist_inv_lpi: 652 * @cs: GICv3CPUState 653 * @irq: LPI to invalidate cached information for 654 * 655 * Forget or update any cached information associated with this LPI. 656 */ 657 void gicv3_redist_inv_lpi(GICv3CPUState *cs, int irq); 658 /** 659 * gicv3_redist_inv_vlpi: 660 * @cs: GICv3CPUState 661 * @irq: vLPI to invalidate cached information for 662 * @vptaddr: (guest) address of vLPI table 663 * 664 * Forget or update any cached information associated with this vLPI. 665 */ 666 void gicv3_redist_inv_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr); 667 /** 668 * gicv3_redist_mov_lpi: 669 * @src: source redistributor 670 * @dest: destination redistributor 671 * @irq: LPI to update 672 * 673 * Move the pending state of the specified LPI from @src to @dest, 674 * as required by the ITS MOVI command. 675 */ 676 void gicv3_redist_mov_lpi(GICv3CPUState *src, GICv3CPUState *dest, int irq); 677 /** 678 * gicv3_redist_movall_lpis: 679 * @src: source redistributor 680 * @dest: destination redistributor 681 * 682 * Scan the LPI pending table for @src, and for each pending LPI there 683 * mark it as not-pending for @src and pending for @dest, as required 684 * by the ITS MOVALL command. 685 */ 686 void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest); 687 /** 688 * gicv3_redist_mov_vlpi: 689 * @src: source redistributor 690 * @src_vptaddr: (guest) address of source VLPI table 691 * @dest: destination redistributor 692 * @dest_vptaddr: (guest) address of destination VLPI table 693 * @irq: VLPI to update 694 * @doorbell: doorbell for destination (1023 for "no doorbell") 695 * 696 * Move the pending state of the specified VLPI from @src to @dest, 697 * as required by the ITS VMOVI command. 698 */ 699 void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr, 700 GICv3CPUState *dest, uint64_t dest_vptaddr, 701 int irq, int doorbell); 702 /** 703 * gicv3_redist_vinvall: 704 * @cs: GICv3CPUState 705 * @vptaddr: address of VLPI pending table 706 * 707 * On redistributor @cs, invalidate all cached information associated 708 * with the vCPU defined by @vptaddr. 709 */ 710 void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr); 711 712 void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); 713 void gicv3_init_cpuif(GICv3State *s); 714 715 /** 716 * gicv3_cpuif_update: 717 * @cs: GICv3CPUState for the CPU to update 718 * 719 * Recalculate whether to assert the IRQ or FIQ lines after a change 720 * to the current highest priority pending interrupt, the CPU's 721 * current running priority or the CPU's current exception level or 722 * security state. 723 */ 724 void gicv3_cpuif_update(GICv3CPUState *cs); 725 726 /* 727 * gicv3_cpuif_virt_irq_fiq_update: 728 * @cs: GICv3CPUState for the CPU to update 729 * 730 * Recalculate whether to assert the virtual IRQ or FIQ lines after 731 * a change to the current highest priority pending virtual interrupt. 732 * Note that this does not recalculate and change the maintenance 733 * interrupt status (for that, see gicv3_cpuif_virt_update()). 734 */ 735 void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs); 736 737 static inline uint32_t gicv3_iidr(void) 738 { 739 /* Return the Implementer Identification Register value 740 * for the emulated GICv3, as reported in GICD_IIDR and GICR_IIDR. 741 * 742 * We claim to be an ARM r0p0 with a zero ProductID. 743 * This is the same as an r0p0 GIC-500. 744 */ 745 return 0x43b; 746 } 747 748 /* CoreSight PIDR0 values for ARM GICv3 implementations */ 749 #define GICV3_PIDR0_DIST 0x92 750 #define GICV3_PIDR0_REDIST 0x93 751 #define GICV3_PIDR0_ITS 0x94 752 753 static inline uint32_t gicv3_idreg(GICv3State *s, int regoffset, uint8_t pidr0) 754 { 755 /* Return the value of the CoreSight ID register at the specified 756 * offset from the first ID register (as found in the distributor 757 * and redistributor register banks). 758 * These values indicate an ARM implementation of a GICv3 or v4. 759 */ 760 static const uint8_t gicd_ids[] = { 761 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 762 }; 763 uint32_t id; 764 765 regoffset /= 4; 766 767 if (regoffset == 4) { 768 return pidr0; 769 } 770 id = gicd_ids[regoffset]; 771 if (regoffset == 6) { 772 /* PIDR2 bits [7:4] are the GIC architecture revision */ 773 id |= s->revision << 4; 774 } 775 return id; 776 } 777 778 /** 779 * gicv3_irq_group: 780 * 781 * Return the group which this interrupt is configured as (GICV3_G0, 782 * GICV3_G1 or GICV3_G1NS). 783 */ 784 static inline int gicv3_irq_group(GICv3State *s, GICv3CPUState *cs, int irq) 785 { 786 bool grpbit, grpmodbit; 787 788 if (irq < GIC_INTERNAL) { 789 grpbit = extract32(cs->gicr_igroupr0, irq, 1); 790 grpmodbit = extract32(cs->gicr_igrpmodr0, irq, 1); 791 } else { 792 grpbit = gicv3_gicd_group_test(s, irq); 793 grpmodbit = gicv3_gicd_grpmod_test(s, irq); 794 } 795 if (grpbit) { 796 return GICV3_G1NS; 797 } 798 if (s->gicd_ctlr & GICD_CTLR_DS) { 799 return GICV3_G0; 800 } 801 return grpmodbit ? GICV3_G1 : GICV3_G0; 802 } 803 804 /** 805 * gicv3_redist_affid: 806 * 807 * Return the 32-bit affinity ID of the CPU connected to this redistributor 808 */ 809 static inline uint32_t gicv3_redist_affid(GICv3CPUState *cs) 810 { 811 return cs->gicr_typer >> 32; 812 } 813 814 /** 815 * gicv3_cache_target_cpustate: 816 * 817 * Update the cached CPU state corresponding to the target for this interrupt 818 * (which is kept in s->gicd_irouter_target[]). 819 */ 820 static inline void gicv3_cache_target_cpustate(GICv3State *s, int irq) 821 { 822 GICv3CPUState *cs = NULL; 823 int i; 824 uint32_t tgtaff = extract64(s->gicd_irouter[irq], 0, 24) | 825 extract64(s->gicd_irouter[irq], 32, 8) << 24; 826 827 for (i = 0; i < s->num_cpu; i++) { 828 if (s->cpu[i].gicr_typer >> 32 == tgtaff) { 829 cs = &s->cpu[i]; 830 break; 831 } 832 } 833 834 s->gicd_irouter_target[irq] = cs; 835 } 836 837 /** 838 * gicv3_cache_all_target_cpustates: 839 * 840 * Populate the entire cache of CPU state pointers for interrupt targets 841 * (eg after inbound migration or CPU reset) 842 */ 843 static inline void gicv3_cache_all_target_cpustates(GICv3State *s) 844 { 845 int irq; 846 847 for (irq = GIC_INTERNAL; irq < GICV3_MAXIRQ; irq++) { 848 gicv3_cache_target_cpustate(s, irq); 849 } 850 } 851 852 void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s); 853 854 #endif /* QEMU_ARM_GICV3_INTERNAL_H */ 855