xref: /openbmc/qemu/hw/intc/gicv3_internal.h (revision 641f32f6)
1 /*
2  * ARM GICv3 support - internal interfaces
3  *
4  * Copyright (c) 2012 Linaro Limited
5  * Copyright (c) 2015 Huawei.
6  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
7  * Written by Peter Maydell
8  * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation, either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License along
21  * with this program; if not, see <http://www.gnu.org/licenses/>.
22  */
23 
24 #ifndef QEMU_ARM_GICV3_INTERNAL_H
25 #define QEMU_ARM_GICV3_INTERNAL_H
26 
27 #include "hw/registerfields.h"
28 #include "hw/intc/arm_gicv3_common.h"
29 
30 /* Distributor registers, as offsets from the distributor base address */
31 #define GICD_CTLR            0x0000
32 #define GICD_TYPER           0x0004
33 #define GICD_IIDR            0x0008
34 #define GICD_STATUSR         0x0010
35 #define GICD_SETSPI_NSR      0x0040
36 #define GICD_CLRSPI_NSR      0x0048
37 #define GICD_SETSPI_SR       0x0050
38 #define GICD_CLRSPI_SR       0x0058
39 #define GICD_SEIR            0x0068
40 #define GICD_IGROUPR         0x0080
41 #define GICD_ISENABLER       0x0100
42 #define GICD_ICENABLER       0x0180
43 #define GICD_ISPENDR         0x0200
44 #define GICD_ICPENDR         0x0280
45 #define GICD_ISACTIVER       0x0300
46 #define GICD_ICACTIVER       0x0380
47 #define GICD_IPRIORITYR      0x0400
48 #define GICD_ITARGETSR       0x0800
49 #define GICD_ICFGR           0x0C00
50 #define GICD_IGRPMODR        0x0D00
51 #define GICD_NSACR           0x0E00
52 #define GICD_SGIR            0x0F00
53 #define GICD_CPENDSGIR       0x0F10
54 #define GICD_SPENDSGIR       0x0F20
55 #define GICD_IROUTER         0x6000
56 #define GICD_IDREGS          0xFFD0
57 
58 /* GICD_CTLR fields  */
59 #define GICD_CTLR_EN_GRP0           (1U << 0)
60 #define GICD_CTLR_EN_GRP1NS         (1U << 1) /* GICv3 5.3.20 */
61 #define GICD_CTLR_EN_GRP1S          (1U << 2)
62 #define GICD_CTLR_EN_GRP1_ALL       (GICD_CTLR_EN_GRP1NS | GICD_CTLR_EN_GRP1S)
63 /* Bit 4 is ARE if the system doesn't support TrustZone, ARE_S otherwise */
64 #define GICD_CTLR_ARE               (1U << 4)
65 #define GICD_CTLR_ARE_S             (1U << 4)
66 #define GICD_CTLR_ARE_NS            (1U << 5)
67 #define GICD_CTLR_DS                (1U << 6)
68 #define GICD_CTLR_E1NWF             (1U << 7)
69 #define GICD_CTLR_RWP               (1U << 31)
70 
71 #define GICD_TYPER_LPIS_SHIFT          17
72 
73 /* 16 bits EventId */
74 #define GICD_TYPER_IDBITS            0xf
75 
76 /*
77  * Redistributor frame offsets from RD_base
78  */
79 #define GICR_SGI_OFFSET 0x10000
80 
81 /*
82  * Redistributor registers, offsets from RD_base
83  */
84 #define GICR_CTLR             0x0000
85 #define GICR_IIDR             0x0004
86 #define GICR_TYPER            0x0008
87 #define GICR_STATUSR          0x0010
88 #define GICR_WAKER            0x0014
89 #define GICR_SETLPIR          0x0040
90 #define GICR_CLRLPIR          0x0048
91 #define GICR_PROPBASER        0x0070
92 #define GICR_PENDBASER        0x0078
93 #define GICR_INVLPIR          0x00A0
94 #define GICR_INVALLR          0x00B0
95 #define GICR_SYNCR            0x00C0
96 #define GICR_IDREGS           0xFFD0
97 
98 /* SGI and PPI Redistributor registers, offsets from RD_base */
99 #define GICR_IGROUPR0         (GICR_SGI_OFFSET + 0x0080)
100 #define GICR_ISENABLER0       (GICR_SGI_OFFSET + 0x0100)
101 #define GICR_ICENABLER0       (GICR_SGI_OFFSET + 0x0180)
102 #define GICR_ISPENDR0         (GICR_SGI_OFFSET + 0x0200)
103 #define GICR_ICPENDR0         (GICR_SGI_OFFSET + 0x0280)
104 #define GICR_ISACTIVER0       (GICR_SGI_OFFSET + 0x0300)
105 #define GICR_ICACTIVER0       (GICR_SGI_OFFSET + 0x0380)
106 #define GICR_IPRIORITYR       (GICR_SGI_OFFSET + 0x0400)
107 #define GICR_ICFGR0           (GICR_SGI_OFFSET + 0x0C00)
108 #define GICR_ICFGR1           (GICR_SGI_OFFSET + 0x0C04)
109 #define GICR_IGRPMODR0        (GICR_SGI_OFFSET + 0x0D00)
110 #define GICR_NSACR            (GICR_SGI_OFFSET + 0x0E00)
111 
112 #define GICR_CTLR_ENABLE_LPIS        (1U << 0)
113 #define GICR_CTLR_RWP                (1U << 3)
114 #define GICR_CTLR_DPG0               (1U << 24)
115 #define GICR_CTLR_DPG1NS             (1U << 25)
116 #define GICR_CTLR_DPG1S              (1U << 26)
117 #define GICR_CTLR_UWP                (1U << 31)
118 
119 #define GICR_TYPER_PLPIS             (1U << 0)
120 #define GICR_TYPER_VLPIS             (1U << 1)
121 #define GICR_TYPER_DIRECTLPI         (1U << 3)
122 #define GICR_TYPER_LAST              (1U << 4)
123 #define GICR_TYPER_DPGS              (1U << 5)
124 #define GICR_TYPER_PROCNUM           (0xFFFFU << 8)
125 #define GICR_TYPER_COMMONLPIAFF      (0x3 << 24)
126 #define GICR_TYPER_AFFINITYVALUE     (0xFFFFFFFFULL << 32)
127 
128 #define GICR_WAKER_ProcessorSleep    (1U << 1)
129 #define GICR_WAKER_ChildrenAsleep    (1U << 2)
130 
131 FIELD(GICR_PROPBASER, IDBITS, 0, 5)
132 FIELD(GICR_PROPBASER, INNERCACHE, 7, 3)
133 FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2)
134 FIELD(GICR_PROPBASER, PHYADDR, 12, 40)
135 FIELD(GICR_PROPBASER, OUTERCACHE, 56, 3)
136 
137 FIELD(GICR_PENDBASER, INNERCACHE, 7, 3)
138 FIELD(GICR_PENDBASER, SHAREABILITY, 10, 2)
139 FIELD(GICR_PENDBASER, PHYADDR, 16, 36)
140 FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3)
141 FIELD(GICR_PENDBASER, PTZ, 62, 1)
142 
143 #define GICR_PROPBASER_IDBITS_THRESHOLD          0xd
144 
145 #define ICC_CTLR_EL1_CBPR           (1U << 0)
146 #define ICC_CTLR_EL1_EOIMODE        (1U << 1)
147 #define ICC_CTLR_EL1_PMHE           (1U << 6)
148 #define ICC_CTLR_EL1_PRIBITS_SHIFT 8
149 #define ICC_CTLR_EL1_PRIBITS_MASK   (7U << ICC_CTLR_EL1_PRIBITS_SHIFT)
150 #define ICC_CTLR_EL1_IDBITS_SHIFT 11
151 #define ICC_CTLR_EL1_SEIS           (1U << 14)
152 #define ICC_CTLR_EL1_A3V            (1U << 15)
153 
154 #define ICC_PMR_PRIORITY_MASK    0xff
155 #define ICC_BPR_BINARYPOINT_MASK 0x07
156 #define ICC_IGRPEN_ENABLE        0x01
157 
158 #define ICC_CTLR_EL3_CBPR_EL1S (1U << 0)
159 #define ICC_CTLR_EL3_CBPR_EL1NS (1U << 1)
160 #define ICC_CTLR_EL3_EOIMODE_EL3 (1U << 2)
161 #define ICC_CTLR_EL3_EOIMODE_EL1S (1U << 3)
162 #define ICC_CTLR_EL3_EOIMODE_EL1NS (1U << 4)
163 #define ICC_CTLR_EL3_RM (1U << 5)
164 #define ICC_CTLR_EL3_PMHE (1U << 6)
165 #define ICC_CTLR_EL3_PRIBITS_SHIFT 8
166 #define ICC_CTLR_EL3_IDBITS_SHIFT 11
167 #define ICC_CTLR_EL3_SEIS (1U << 14)
168 #define ICC_CTLR_EL3_A3V (1U << 15)
169 #define ICC_CTLR_EL3_NDS (1U << 17)
170 
171 #define ICH_VMCR_EL2_VENG0_SHIFT 0
172 #define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT)
173 #define ICH_VMCR_EL2_VENG1_SHIFT 1
174 #define ICH_VMCR_EL2_VENG1 (1U << ICH_VMCR_EL2_VENG1_SHIFT)
175 #define ICH_VMCR_EL2_VACKCTL (1U << 2)
176 #define ICH_VMCR_EL2_VFIQEN (1U << 3)
177 #define ICH_VMCR_EL2_VCBPR_SHIFT 4
178 #define ICH_VMCR_EL2_VCBPR (1U << ICH_VMCR_EL2_VCBPR_SHIFT)
179 #define ICH_VMCR_EL2_VEOIM_SHIFT 9
180 #define ICH_VMCR_EL2_VEOIM (1U << ICH_VMCR_EL2_VEOIM_SHIFT)
181 #define ICH_VMCR_EL2_VBPR1_SHIFT 18
182 #define ICH_VMCR_EL2_VBPR1_LENGTH 3
183 #define ICH_VMCR_EL2_VBPR1_MASK (0x7U << ICH_VMCR_EL2_VBPR1_SHIFT)
184 #define ICH_VMCR_EL2_VBPR0_SHIFT 21
185 #define ICH_VMCR_EL2_VBPR0_LENGTH 3
186 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT)
187 #define ICH_VMCR_EL2_VPMR_SHIFT 24
188 #define ICH_VMCR_EL2_VPMR_LENGTH 8
189 #define ICH_VMCR_EL2_VPMR_MASK (0xffU << ICH_VMCR_EL2_VPMR_SHIFT)
190 
191 #define ICH_HCR_EL2_EN (1U << 0)
192 #define ICH_HCR_EL2_UIE (1U << 1)
193 #define ICH_HCR_EL2_LRENPIE (1U << 2)
194 #define ICH_HCR_EL2_NPIE (1U << 3)
195 #define ICH_HCR_EL2_VGRP0EIE (1U << 4)
196 #define ICH_HCR_EL2_VGRP0DIE (1U << 5)
197 #define ICH_HCR_EL2_VGRP1EIE (1U << 6)
198 #define ICH_HCR_EL2_VGRP1DIE (1U << 7)
199 #define ICH_HCR_EL2_TC (1U << 10)
200 #define ICH_HCR_EL2_TALL0 (1U << 11)
201 #define ICH_HCR_EL2_TALL1 (1U << 12)
202 #define ICH_HCR_EL2_TSEI (1U << 13)
203 #define ICH_HCR_EL2_TDIR (1U << 14)
204 #define ICH_HCR_EL2_EOICOUNT_SHIFT 27
205 #define ICH_HCR_EL2_EOICOUNT_LENGTH 5
206 #define ICH_HCR_EL2_EOICOUNT_MASK (0x1fU << ICH_HCR_EL2_EOICOUNT_SHIFT)
207 
208 #define ICH_LR_EL2_VINTID_SHIFT 0
209 #define ICH_LR_EL2_VINTID_LENGTH 32
210 #define ICH_LR_EL2_VINTID_MASK (0xffffffffULL << ICH_LR_EL2_VINTID_SHIFT)
211 #define ICH_LR_EL2_PINTID_SHIFT 32
212 #define ICH_LR_EL2_PINTID_LENGTH 10
213 #define ICH_LR_EL2_PINTID_MASK (0x3ffULL << ICH_LR_EL2_PINTID_SHIFT)
214 /* Note that EOI shares with the top bit of the pINTID field */
215 #define ICH_LR_EL2_EOI (1ULL << 41)
216 #define ICH_LR_EL2_PRIORITY_SHIFT 48
217 #define ICH_LR_EL2_PRIORITY_LENGTH 8
218 #define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT)
219 #define ICH_LR_EL2_GROUP (1ULL << 60)
220 #define ICH_LR_EL2_HW (1ULL << 61)
221 #define ICH_LR_EL2_STATE_SHIFT 62
222 #define ICH_LR_EL2_STATE_LENGTH 2
223 #define ICH_LR_EL2_STATE_MASK (3ULL << ICH_LR_EL2_STATE_SHIFT)
224 /* values for the state field: */
225 #define ICH_LR_EL2_STATE_INVALID 0
226 #define ICH_LR_EL2_STATE_PENDING 1
227 #define ICH_LR_EL2_STATE_ACTIVE 2
228 #define ICH_LR_EL2_STATE_ACTIVE_PENDING 3
229 #define ICH_LR_EL2_STATE_PENDING_BIT (1ULL << ICH_LR_EL2_STATE_SHIFT)
230 #define ICH_LR_EL2_STATE_ACTIVE_BIT (2ULL << ICH_LR_EL2_STATE_SHIFT)
231 
232 #define ICH_MISR_EL2_EOI (1U << 0)
233 #define ICH_MISR_EL2_U (1U << 1)
234 #define ICH_MISR_EL2_LRENP (1U << 2)
235 #define ICH_MISR_EL2_NP (1U << 3)
236 #define ICH_MISR_EL2_VGRP0E (1U << 4)
237 #define ICH_MISR_EL2_VGRP0D (1U << 5)
238 #define ICH_MISR_EL2_VGRP1E (1U << 6)
239 #define ICH_MISR_EL2_VGRP1D (1U << 7)
240 
241 #define ICH_VTR_EL2_LISTREGS_SHIFT 0
242 #define ICH_VTR_EL2_TDS (1U << 19)
243 #define ICH_VTR_EL2_NV4 (1U << 20)
244 #define ICH_VTR_EL2_A3V (1U << 21)
245 #define ICH_VTR_EL2_SEIS (1U << 22)
246 #define ICH_VTR_EL2_IDBITS_SHIFT 23
247 #define ICH_VTR_EL2_PREBITS_SHIFT 26
248 #define ICH_VTR_EL2_PRIBITS_SHIFT 29
249 
250 /* ITS Registers */
251 
252 FIELD(GITS_BASER, SIZE, 0, 8)
253 FIELD(GITS_BASER, PAGESIZE, 8, 2)
254 FIELD(GITS_BASER, SHAREABILITY, 10, 2)
255 FIELD(GITS_BASER, PHYADDR, 12, 36)
256 FIELD(GITS_BASER, PHYADDRL_64K, 16, 32)
257 FIELD(GITS_BASER, PHYADDRH_64K, 12, 4)
258 FIELD(GITS_BASER, ENTRYSIZE, 48, 5)
259 FIELD(GITS_BASER, OUTERCACHE, 53, 3)
260 FIELD(GITS_BASER, TYPE, 56, 3)
261 FIELD(GITS_BASER, INNERCACHE, 59, 3)
262 FIELD(GITS_BASER, INDIRECT, 62, 1)
263 FIELD(GITS_BASER, VALID, 63, 1)
264 
265 FIELD(GITS_CBASER, SIZE, 0, 8)
266 FIELD(GITS_CBASER, SHAREABILITY, 10, 2)
267 FIELD(GITS_CBASER, PHYADDR, 12, 40)
268 FIELD(GITS_CBASER, OUTERCACHE, 53, 3)
269 FIELD(GITS_CBASER, INNERCACHE, 59, 3)
270 FIELD(GITS_CBASER, VALID, 63, 1)
271 
272 FIELD(GITS_CREADR, STALLED, 0, 1)
273 FIELD(GITS_CREADR, OFFSET, 5, 15)
274 
275 FIELD(GITS_CWRITER, RETRY, 0, 1)
276 FIELD(GITS_CWRITER, OFFSET, 5, 15)
277 
278 FIELD(GITS_CTLR, ENABLED, 0, 1)
279 FIELD(GITS_CTLR, QUIESCENT, 31, 1)
280 
281 FIELD(GITS_TYPER, PHYSICAL, 0, 1)
282 FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4)
283 FIELD(GITS_TYPER, IDBITS, 8, 5)
284 FIELD(GITS_TYPER, DEVBITS, 13, 5)
285 FIELD(GITS_TYPER, SEIS, 18, 1)
286 FIELD(GITS_TYPER, PTA, 19, 1)
287 FIELD(GITS_TYPER, CIDBITS, 32, 4)
288 FIELD(GITS_TYPER, CIL, 36, 1)
289 
290 #define GITS_IDREGS           0xFFD0
291 
292 #define ITS_CTLR_ENABLED               (1U)  /* ITS Enabled */
293 
294 #define GITS_BASER_RO_MASK                  (R_GITS_BASER_ENTRYSIZE_MASK | \
295                                               R_GITS_BASER_TYPE_MASK)
296 
297 #define GITS_BASER_PAGESIZE_4K                0
298 #define GITS_BASER_PAGESIZE_16K               1
299 #define GITS_BASER_PAGESIZE_64K               2
300 
301 #define GITS_BASER_TYPE_DEVICE               1ULL
302 #define GITS_BASER_TYPE_COLLECTION           4ULL
303 
304 #define GITS_PAGE_SIZE_4K       0x1000
305 #define GITS_PAGE_SIZE_16K      0x4000
306 #define GITS_PAGE_SIZE_64K      0x10000
307 
308 #define L1TABLE_ENTRY_SIZE         8
309 
310 #define LPI_CTE_ENABLED          TABLE_ENTRY_VALID_MASK
311 #define LPI_PRIORITY_MASK         0xfc
312 
313 #define GITS_CMDQ_ENTRY_SIZE               32
314 #define NUM_BYTES_IN_DW                     8
315 
316 #define CMD_MASK                  0xff
317 
318 /* ITS Commands */
319 #define GITS_CMD_CLEAR            0x04
320 #define GITS_CMD_DISCARD          0x0F
321 #define GITS_CMD_INT              0x03
322 #define GITS_CMD_MAPC             0x09
323 #define GITS_CMD_MAPD             0x08
324 #define GITS_CMD_MAPI             0x0B
325 #define GITS_CMD_MAPTI            0x0A
326 #define GITS_CMD_INV              0x0C
327 #define GITS_CMD_INVALL           0x0D
328 #define GITS_CMD_SYNC             0x05
329 
330 /* MAPC command fields */
331 #define ICID_LENGTH                  16
332 #define ICID_MASK                 ((1U << ICID_LENGTH) - 1)
333 FIELD(MAPC, RDBASE, 16, 32)
334 
335 #define RDBASE_PROCNUM_LENGTH        16
336 #define RDBASE_PROCNUM_MASK       ((1ULL << RDBASE_PROCNUM_LENGTH) - 1)
337 
338 /* MAPD command fields */
339 #define ITTADDR_LENGTH               44
340 #define ITTADDR_SHIFT                 8
341 #define ITTADDR_MASK             MAKE_64BIT_MASK(ITTADDR_SHIFT, ITTADDR_LENGTH)
342 #define SIZE_MASK                 0x1f
343 
344 /* MAPI command fields */
345 #define EVENTID_MASK              ((1ULL << 32) - 1)
346 
347 /* MAPTI command fields */
348 #define pINTID_SHIFT                 32
349 #define pINTID_MASK               MAKE_64BIT_MASK(32, 32)
350 
351 #define DEVID_SHIFT                  32
352 #define DEVID_MASK                MAKE_64BIT_MASK(32, 32)
353 
354 #define VALID_SHIFT               63
355 #define CMD_FIELD_VALID_MASK      (1ULL << VALID_SHIFT)
356 #define L2_TABLE_VALID_MASK       CMD_FIELD_VALID_MASK
357 #define TABLE_ENTRY_VALID_MASK    (1ULL << 0)
358 
359 /**
360  * Default features advertised by this version of ITS
361  */
362 /* Physical LPIs supported */
363 #define GITS_TYPE_PHYSICAL           (1U << 0)
364 
365 /*
366  * 12 bytes Interrupt translation Table Entry size
367  * as per Table 5.3 in GICv3 spec
368  * ITE Lower 8 Bytes
369  *   Bits:    | 49 ... 26 | 25 ... 2 |   1     |   0    |
370  *   Values:  |    1023   |  IntNum  | IntType |  Valid |
371  * ITE Higher 4 Bytes
372  *   Bits:    | 31 ... 16 | 15 ...0 |
373  *   Values:  |  vPEID    |  ICID   |
374  */
375 #define ITS_ITT_ENTRY_SIZE            0xC
376 #define ITE_ENTRY_INTTYPE_SHIFT        1
377 #define ITE_ENTRY_INTID_SHIFT          2
378 #define ITE_ENTRY_INTID_MASK         MAKE_64BIT_MASK(2, 24)
379 #define ITE_ENTRY_INTSP_SHIFT          26
380 #define ITE_ENTRY_ICID_MASK          MAKE_64BIT_MASK(0, 16)
381 
382 /* 16 bits EventId */
383 #define ITS_IDBITS                   GICD_TYPER_IDBITS
384 
385 /* 16 bits DeviceId */
386 #define ITS_DEVBITS                   0xF
387 
388 /* 16 bits CollectionId */
389 #define ITS_CIDBITS                  0xF
390 
391 /*
392  * 8 bytes Device Table Entry size
393  * Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits
394  */
395 #define GITS_DTE_SIZE                 (0x8ULL)
396 #define GITS_DTE_ITTADDR_SHIFT           6
397 #define GITS_DTE_ITTADDR_MASK         MAKE_64BIT_MASK(GITS_DTE_ITTADDR_SHIFT, \
398                                                       ITTADDR_LENGTH)
399 
400 /*
401  * 8 bytes Collection Table Entry size
402  * Valid = 1 bit,RDBase = 36 bits(considering max RDBASE)
403  */
404 #define GITS_CTE_SIZE                 (0x8ULL)
405 #define GITS_CTE_RDBASE_PROCNUM_MASK  MAKE_64BIT_MASK(1, RDBASE_PROCNUM_LENGTH)
406 
407 /* Special interrupt IDs */
408 #define INTID_SECURE 1020
409 #define INTID_NONSECURE 1021
410 #define INTID_SPURIOUS 1023
411 
412 /* Functions internal to the emulated GICv3 */
413 
414 /**
415  * gicv3_intid_is_special:
416  * @intid: interrupt ID
417  *
418  * Return true if @intid is a special interrupt ID (1020 to
419  * 1023 inclusive). This corresponds to the GIC spec pseudocode
420  * IsSpecial() function.
421  */
422 static inline bool gicv3_intid_is_special(int intid)
423 {
424     return intid >= INTID_SECURE && intid <= INTID_SPURIOUS;
425 }
426 
427 /**
428  * gicv3_redist_update:
429  * @cs: GICv3CPUState for this redistributor
430  *
431  * Recalculate the highest priority pending interrupt after a
432  * change to redistributor state, and inform the CPU accordingly.
433  */
434 void gicv3_redist_update(GICv3CPUState *cs);
435 
436 /**
437  * gicv3_update:
438  * @s: GICv3State
439  * @start: first interrupt whose state changed
440  * @len: length of the range of interrupts whose state changed
441  *
442  * Recalculate the highest priority pending interrupts after a
443  * change to the distributor state affecting @len interrupts
444  * starting at @start, and inform the CPUs accordingly.
445  */
446 void gicv3_update(GICv3State *s, int start, int len);
447 
448 /**
449  * gicv3_full_update_noirqset:
450  * @s: GICv3State
451  *
452  * Recalculate the cached information about highest priority
453  * pending interrupts, but don't inform the CPUs. This should be
454  * called after an incoming migration has loaded new state.
455  */
456 void gicv3_full_update_noirqset(GICv3State *s);
457 
458 /**
459  * gicv3_full_update:
460  * @s: GICv3State
461  *
462  * Recalculate the highest priority pending interrupts after
463  * a change that could affect the status of all interrupts,
464  * and inform the CPUs accordingly.
465  */
466 void gicv3_full_update(GICv3State *s);
467 MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data,
468                             unsigned size, MemTxAttrs attrs);
469 MemTxResult gicv3_dist_write(void *opaque, hwaddr addr, uint64_t data,
470                              unsigned size, MemTxAttrs attrs);
471 MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
472                               unsigned size, MemTxAttrs attrs);
473 MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
474                                unsigned size, MemTxAttrs attrs);
475 void gicv3_dist_set_irq(GICv3State *s, int irq, int level);
476 void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level);
477 void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level);
478 void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level);
479 /**
480  * gicv3_redist_update_lpi:
481  * @cs: GICv3CPUState
482  *
483  * Scan the LPI pending table and recalculate the highest priority
484  * pending LPI and also the overall highest priority pending interrupt.
485  */
486 void gicv3_redist_update_lpi(GICv3CPUState *cs);
487 /**
488  * gicv3_redist_update_lpi_only:
489  * @cs: GICv3CPUState
490  *
491  * Scan the LPI pending table and recalculate cs->hpplpi only,
492  * without calling gicv3_redist_update() to recalculate the overall
493  * highest priority pending interrupt. This should be called after
494  * an incoming migration has loaded new state.
495  */
496 void gicv3_redist_update_lpi_only(GICv3CPUState *cs);
497 void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns);
498 void gicv3_init_cpuif(GICv3State *s);
499 
500 /**
501  * gicv3_cpuif_update:
502  * @cs: GICv3CPUState for the CPU to update
503  *
504  * Recalculate whether to assert the IRQ or FIQ lines after a change
505  * to the current highest priority pending interrupt, the CPU's
506  * current running priority or the CPU's current exception level or
507  * security state.
508  */
509 void gicv3_cpuif_update(GICv3CPUState *cs);
510 
511 static inline uint32_t gicv3_iidr(void)
512 {
513     /* Return the Implementer Identification Register value
514      * for the emulated GICv3, as reported in GICD_IIDR and GICR_IIDR.
515      *
516      * We claim to be an ARM r0p0 with a zero ProductID.
517      * This is the same as an r0p0 GIC-500.
518      */
519     return 0x43b;
520 }
521 
522 static inline uint32_t gicv3_idreg(int regoffset)
523 {
524     /* Return the value of the CoreSight ID register at the specified
525      * offset from the first ID register (as found in the distributor
526      * and redistributor register banks).
527      * These values indicate an ARM implementation of a GICv3.
528      */
529     static const uint8_t gicd_ids[] = {
530         0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1
531     };
532     return gicd_ids[regoffset / 4];
533 }
534 
535 /**
536  * gicv3_irq_group:
537  *
538  * Return the group which this interrupt is configured as (GICV3_G0,
539  * GICV3_G1 or GICV3_G1NS).
540  */
541 static inline int gicv3_irq_group(GICv3State *s, GICv3CPUState *cs, int irq)
542 {
543     bool grpbit, grpmodbit;
544 
545     if (irq < GIC_INTERNAL) {
546         grpbit = extract32(cs->gicr_igroupr0, irq, 1);
547         grpmodbit = extract32(cs->gicr_igrpmodr0, irq, 1);
548     } else {
549         grpbit = gicv3_gicd_group_test(s, irq);
550         grpmodbit = gicv3_gicd_grpmod_test(s, irq);
551     }
552     if (grpbit) {
553         return GICV3_G1NS;
554     }
555     if (s->gicd_ctlr & GICD_CTLR_DS) {
556         return GICV3_G0;
557     }
558     return grpmodbit ? GICV3_G1 : GICV3_G0;
559 }
560 
561 /**
562  * gicv3_redist_affid:
563  *
564  * Return the 32-bit affinity ID of the CPU connected to this redistributor
565  */
566 static inline uint32_t gicv3_redist_affid(GICv3CPUState *cs)
567 {
568     return cs->gicr_typer >> 32;
569 }
570 
571 /**
572  * gicv3_cache_target_cpustate:
573  *
574  * Update the cached CPU state corresponding to the target for this interrupt
575  * (which is kept in s->gicd_irouter_target[]).
576  */
577 static inline void gicv3_cache_target_cpustate(GICv3State *s, int irq)
578 {
579     GICv3CPUState *cs = NULL;
580     int i;
581     uint32_t tgtaff = extract64(s->gicd_irouter[irq], 0, 24) |
582         extract64(s->gicd_irouter[irq], 32, 8) << 24;
583 
584     for (i = 0; i < s->num_cpu; i++) {
585         if (s->cpu[i].gicr_typer >> 32 == tgtaff) {
586             cs = &s->cpu[i];
587             break;
588         }
589     }
590 
591     s->gicd_irouter_target[irq] = cs;
592 }
593 
594 /**
595  * gicv3_cache_all_target_cpustates:
596  *
597  * Populate the entire cache of CPU state pointers for interrupt targets
598  * (eg after inbound migration or CPU reset)
599  */
600 static inline void gicv3_cache_all_target_cpustates(GICv3State *s)
601 {
602     int irq;
603 
604     for (irq = GIC_INTERNAL; irq < GICV3_MAXIRQ; irq++) {
605         gicv3_cache_target_cpustate(s, irq);
606     }
607 }
608 
609 void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s);
610 
611 #endif /* QEMU_ARM_GICV3_INTERNAL_H */
612