1 /* 2 * ARM GICv3 support - internal interfaces 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Copyright (c) 2015 Huawei. 6 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 7 * Written by Peter Maydell 8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef QEMU_ARM_GICV3_INTERNAL_H 25 #define QEMU_ARM_GICV3_INTERNAL_H 26 27 #include "hw/registerfields.h" 28 #include "hw/intc/arm_gicv3_common.h" 29 30 /* Distributor registers, as offsets from the distributor base address */ 31 #define GICD_CTLR 0x0000 32 #define GICD_TYPER 0x0004 33 #define GICD_IIDR 0x0008 34 #define GICD_STATUSR 0x0010 35 #define GICD_SETSPI_NSR 0x0040 36 #define GICD_CLRSPI_NSR 0x0048 37 #define GICD_SETSPI_SR 0x0050 38 #define GICD_CLRSPI_SR 0x0058 39 #define GICD_SEIR 0x0068 40 #define GICD_IGROUPR 0x0080 41 #define GICD_ISENABLER 0x0100 42 #define GICD_ICENABLER 0x0180 43 #define GICD_ISPENDR 0x0200 44 #define GICD_ICPENDR 0x0280 45 #define GICD_ISACTIVER 0x0300 46 #define GICD_ICACTIVER 0x0380 47 #define GICD_IPRIORITYR 0x0400 48 #define GICD_ITARGETSR 0x0800 49 #define GICD_ICFGR 0x0C00 50 #define GICD_IGRPMODR 0x0D00 51 #define GICD_NSACR 0x0E00 52 #define GICD_SGIR 0x0F00 53 #define GICD_CPENDSGIR 0x0F10 54 #define GICD_SPENDSGIR 0x0F20 55 #define GICD_INMIR 0x0F80 56 #define GICD_INMIRnE 0x3B00 57 #define GICD_IROUTER 0x6000 58 #define GICD_IDREGS 0xFFD0 59 60 /* GICD_CTLR fields */ 61 #define GICD_CTLR_EN_GRP0 (1U << 0) 62 #define GICD_CTLR_EN_GRP1NS (1U << 1) /* GICv3 5.3.20 */ 63 #define GICD_CTLR_EN_GRP1S (1U << 2) 64 #define GICD_CTLR_EN_GRP1_ALL (GICD_CTLR_EN_GRP1NS | GICD_CTLR_EN_GRP1S) 65 /* Bit 4 is ARE if the system doesn't support TrustZone, ARE_S otherwise */ 66 #define GICD_CTLR_ARE (1U << 4) 67 #define GICD_CTLR_ARE_S (1U << 4) 68 #define GICD_CTLR_ARE_NS (1U << 5) 69 #define GICD_CTLR_DS (1U << 6) 70 #define GICD_CTLR_E1NWF (1U << 7) 71 #define GICD_CTLR_RWP (1U << 31) 72 73 #define GICD_TYPER_NMI_SHIFT 9 74 #define GICD_TYPER_LPIS_SHIFT 17 75 76 /* 16 bits EventId */ 77 #define GICD_TYPER_IDBITS 0xf 78 79 /* 80 * Redistributor frame offsets from RD_base 81 */ 82 #define GICR_SGI_OFFSET 0x10000 83 #define GICR_VLPI_OFFSET 0x20000 84 85 /* 86 * Redistributor registers, offsets from RD_base 87 */ 88 #define GICR_CTLR 0x0000 89 #define GICR_IIDR 0x0004 90 #define GICR_TYPER 0x0008 91 #define GICR_STATUSR 0x0010 92 #define GICR_WAKER 0x0014 93 #define GICR_SETLPIR 0x0040 94 #define GICR_CLRLPIR 0x0048 95 #define GICR_PROPBASER 0x0070 96 #define GICR_PENDBASER 0x0078 97 #define GICR_INVLPIR 0x00A0 98 #define GICR_INVALLR 0x00B0 99 #define GICR_SYNCR 0x00C0 100 #define GICR_IDREGS 0xFFD0 101 102 /* SGI and PPI Redistributor registers, offsets from RD_base */ 103 #define GICR_IGROUPR0 (GICR_SGI_OFFSET + 0x0080) 104 #define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100) 105 #define GICR_ICENABLER0 (GICR_SGI_OFFSET + 0x0180) 106 #define GICR_ISPENDR0 (GICR_SGI_OFFSET + 0x0200) 107 #define GICR_ICPENDR0 (GICR_SGI_OFFSET + 0x0280) 108 #define GICR_ISACTIVER0 (GICR_SGI_OFFSET + 0x0300) 109 #define GICR_ICACTIVER0 (GICR_SGI_OFFSET + 0x0380) 110 #define GICR_IPRIORITYR (GICR_SGI_OFFSET + 0x0400) 111 #define GICR_ICFGR0 (GICR_SGI_OFFSET + 0x0C00) 112 #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04) 113 #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) 114 #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) 115 #define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80) 116 117 /* VLPI redistributor registers, offsets from VLPI_base */ 118 #define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70) 119 #define GICR_VPENDBASER (GICR_VLPI_OFFSET + 0x78) 120 121 #define GICR_CTLR_ENABLE_LPIS (1U << 0) 122 #define GICR_CTLR_CES (1U << 1) 123 #define GICR_CTLR_RWP (1U << 3) 124 #define GICR_CTLR_DPG0 (1U << 24) 125 #define GICR_CTLR_DPG1NS (1U << 25) 126 #define GICR_CTLR_DPG1S (1U << 26) 127 #define GICR_CTLR_UWP (1U << 31) 128 129 #define GICR_TYPER_PLPIS (1U << 0) 130 #define GICR_TYPER_VLPIS (1U << 1) 131 #define GICR_TYPER_DIRECTLPI (1U << 3) 132 #define GICR_TYPER_LAST (1U << 4) 133 #define GICR_TYPER_DPGS (1U << 5) 134 #define GICR_TYPER_PROCNUM (0xFFFFU << 8) 135 #define GICR_TYPER_COMMONLPIAFF (0x3 << 24) 136 #define GICR_TYPER_AFFINITYVALUE (0xFFFFFFFFULL << 32) 137 138 #define GICR_WAKER_ProcessorSleep (1U << 1) 139 #define GICR_WAKER_ChildrenAsleep (1U << 2) 140 141 FIELD(GICR_PROPBASER, IDBITS, 0, 5) 142 FIELD(GICR_PROPBASER, INNERCACHE, 7, 3) 143 FIELD(GICR_PROPBASER, SHAREABILITY, 10, 2) 144 FIELD(GICR_PROPBASER, PHYADDR, 12, 40) 145 FIELD(GICR_PROPBASER, OUTERCACHE, 56, 3) 146 147 FIELD(GICR_PENDBASER, INNERCACHE, 7, 3) 148 FIELD(GICR_PENDBASER, SHAREABILITY, 10, 2) 149 FIELD(GICR_PENDBASER, PHYADDR, 16, 36) 150 FIELD(GICR_PENDBASER, OUTERCACHE, 56, 3) 151 FIELD(GICR_PENDBASER, PTZ, 62, 1) 152 153 #define GICR_PROPBASER_IDBITS_THRESHOLD 0xd 154 155 /* These are the GICv4 VPROPBASER and VPENDBASER layouts; v4.1 is different */ 156 FIELD(GICR_VPROPBASER, IDBITS, 0, 5) 157 FIELD(GICR_VPROPBASER, INNERCACHE, 7, 3) 158 FIELD(GICR_VPROPBASER, SHAREABILITY, 10, 2) 159 FIELD(GICR_VPROPBASER, PHYADDR, 12, 40) 160 FIELD(GICR_VPROPBASER, OUTERCACHE, 56, 3) 161 162 FIELD(GICR_VPENDBASER, INNERCACHE, 7, 3) 163 FIELD(GICR_VPENDBASER, SHAREABILITY, 10, 2) 164 FIELD(GICR_VPENDBASER, PHYADDR, 16, 36) 165 FIELD(GICR_VPENDBASER, OUTERCACHE, 56, 3) 166 FIELD(GICR_VPENDBASER, DIRTY, 60, 1) 167 FIELD(GICR_VPENDBASER, PENDINGLAST, 61, 1) 168 FIELD(GICR_VPENDBASER, IDAI, 62, 1) 169 FIELD(GICR_VPENDBASER, VALID, 63, 1) 170 171 #define ICC_CTLR_EL1_CBPR (1U << 0) 172 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 173 #define ICC_CTLR_EL1_PMHE (1U << 6) 174 #define ICC_CTLR_EL1_PRIBITS_SHIFT 8 175 #define ICC_CTLR_EL1_PRIBITS_MASK (7U << ICC_CTLR_EL1_PRIBITS_SHIFT) 176 #define ICC_CTLR_EL1_IDBITS_SHIFT 11 177 #define ICC_CTLR_EL1_SEIS (1U << 14) 178 #define ICC_CTLR_EL1_A3V (1U << 15) 179 180 #define ICC_PMR_PRIORITY_MASK 0xff 181 #define ICC_BPR_BINARYPOINT_MASK 0x07 182 #define ICC_IGRPEN_ENABLE 0x01 183 184 #define ICC_CTLR_EL3_CBPR_EL1S (1U << 0) 185 #define ICC_CTLR_EL3_CBPR_EL1NS (1U << 1) 186 #define ICC_CTLR_EL3_EOIMODE_EL3 (1U << 2) 187 #define ICC_CTLR_EL3_EOIMODE_EL1S (1U << 3) 188 #define ICC_CTLR_EL3_EOIMODE_EL1NS (1U << 4) 189 #define ICC_CTLR_EL3_RM (1U << 5) 190 #define ICC_CTLR_EL3_PMHE (1U << 6) 191 #define ICC_CTLR_EL3_PRIBITS_SHIFT 8 192 #define ICC_CTLR_EL3_IDBITS_SHIFT 11 193 #define ICC_CTLR_EL3_SEIS (1U << 14) 194 #define ICC_CTLR_EL3_A3V (1U << 15) 195 #define ICC_CTLR_EL3_NDS (1U << 17) 196 197 #define ICH_VMCR_EL2_VENG0_SHIFT 0 198 #define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT) 199 #define ICH_VMCR_EL2_VENG1_SHIFT 1 200 #define ICH_VMCR_EL2_VENG1 (1U << ICH_VMCR_EL2_VENG1_SHIFT) 201 #define ICH_VMCR_EL2_VACKCTL (1U << 2) 202 #define ICH_VMCR_EL2_VFIQEN (1U << 3) 203 #define ICH_VMCR_EL2_VCBPR_SHIFT 4 204 #define ICH_VMCR_EL2_VCBPR (1U << ICH_VMCR_EL2_VCBPR_SHIFT) 205 #define ICH_VMCR_EL2_VEOIM_SHIFT 9 206 #define ICH_VMCR_EL2_VEOIM (1U << ICH_VMCR_EL2_VEOIM_SHIFT) 207 #define ICH_VMCR_EL2_VBPR1_SHIFT 18 208 #define ICH_VMCR_EL2_VBPR1_LENGTH 3 209 #define ICH_VMCR_EL2_VBPR1_MASK (0x7U << ICH_VMCR_EL2_VBPR1_SHIFT) 210 #define ICH_VMCR_EL2_VBPR0_SHIFT 21 211 #define ICH_VMCR_EL2_VBPR0_LENGTH 3 212 #define ICH_VMCR_EL2_VBPR0_MASK (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT) 213 #define ICH_VMCR_EL2_VPMR_SHIFT 24 214 #define ICH_VMCR_EL2_VPMR_LENGTH 8 215 #define ICH_VMCR_EL2_VPMR_MASK (0xffU << ICH_VMCR_EL2_VPMR_SHIFT) 216 217 #define ICH_HCR_EL2_EN (1U << 0) 218 #define ICH_HCR_EL2_UIE (1U << 1) 219 #define ICH_HCR_EL2_LRENPIE (1U << 2) 220 #define ICH_HCR_EL2_NPIE (1U << 3) 221 #define ICH_HCR_EL2_VGRP0EIE (1U << 4) 222 #define ICH_HCR_EL2_VGRP0DIE (1U << 5) 223 #define ICH_HCR_EL2_VGRP1EIE (1U << 6) 224 #define ICH_HCR_EL2_VGRP1DIE (1U << 7) 225 #define ICH_HCR_EL2_TC (1U << 10) 226 #define ICH_HCR_EL2_TALL0 (1U << 11) 227 #define ICH_HCR_EL2_TALL1 (1U << 12) 228 #define ICH_HCR_EL2_TSEI (1U << 13) 229 #define ICH_HCR_EL2_TDIR (1U << 14) 230 #define ICH_HCR_EL2_EOICOUNT_SHIFT 27 231 #define ICH_HCR_EL2_EOICOUNT_LENGTH 5 232 #define ICH_HCR_EL2_EOICOUNT_MASK (0x1fU << ICH_HCR_EL2_EOICOUNT_SHIFT) 233 234 #define ICH_LR_EL2_VINTID_SHIFT 0 235 #define ICH_LR_EL2_VINTID_LENGTH 32 236 #define ICH_LR_EL2_VINTID_MASK (0xffffffffULL << ICH_LR_EL2_VINTID_SHIFT) 237 #define ICH_LR_EL2_PINTID_SHIFT 32 238 #define ICH_LR_EL2_PINTID_LENGTH 10 239 #define ICH_LR_EL2_PINTID_MASK (0x3ffULL << ICH_LR_EL2_PINTID_SHIFT) 240 /* Note that EOI shares with the top bit of the pINTID field */ 241 #define ICH_LR_EL2_EOI (1ULL << 41) 242 #define ICH_LR_EL2_PRIORITY_SHIFT 48 243 #define ICH_LR_EL2_PRIORITY_LENGTH 8 244 #define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT) 245 #define ICH_LR_EL2_GROUP (1ULL << 60) 246 #define ICH_LR_EL2_HW (1ULL << 61) 247 #define ICH_LR_EL2_STATE_SHIFT 62 248 #define ICH_LR_EL2_STATE_LENGTH 2 249 #define ICH_LR_EL2_STATE_MASK (3ULL << ICH_LR_EL2_STATE_SHIFT) 250 /* values for the state field: */ 251 #define ICH_LR_EL2_STATE_INVALID 0 252 #define ICH_LR_EL2_STATE_PENDING 1 253 #define ICH_LR_EL2_STATE_ACTIVE 2 254 #define ICH_LR_EL2_STATE_ACTIVE_PENDING 3 255 #define ICH_LR_EL2_STATE_PENDING_BIT (1ULL << ICH_LR_EL2_STATE_SHIFT) 256 #define ICH_LR_EL2_STATE_ACTIVE_BIT (2ULL << ICH_LR_EL2_STATE_SHIFT) 257 258 #define ICH_MISR_EL2_EOI (1U << 0) 259 #define ICH_MISR_EL2_U (1U << 1) 260 #define ICH_MISR_EL2_LRENP (1U << 2) 261 #define ICH_MISR_EL2_NP (1U << 3) 262 #define ICH_MISR_EL2_VGRP0E (1U << 4) 263 #define ICH_MISR_EL2_VGRP0D (1U << 5) 264 #define ICH_MISR_EL2_VGRP1E (1U << 6) 265 #define ICH_MISR_EL2_VGRP1D (1U << 7) 266 267 #define ICH_VTR_EL2_LISTREGS_SHIFT 0 268 #define ICH_VTR_EL2_TDS (1U << 19) 269 #define ICH_VTR_EL2_NV4 (1U << 20) 270 #define ICH_VTR_EL2_A3V (1U << 21) 271 #define ICH_VTR_EL2_SEIS (1U << 22) 272 #define ICH_VTR_EL2_IDBITS_SHIFT 23 273 #define ICH_VTR_EL2_PREBITS_SHIFT 26 274 #define ICH_VTR_EL2_PRIBITS_SHIFT 29 275 276 /* ITS Registers */ 277 278 FIELD(GITS_BASER, SIZE, 0, 8) 279 FIELD(GITS_BASER, PAGESIZE, 8, 2) 280 FIELD(GITS_BASER, SHAREABILITY, 10, 2) 281 FIELD(GITS_BASER, PHYADDR, 12, 36) 282 FIELD(GITS_BASER, PHYADDRL_64K, 16, 32) 283 FIELD(GITS_BASER, PHYADDRH_64K, 12, 4) 284 FIELD(GITS_BASER, ENTRYSIZE, 48, 5) 285 FIELD(GITS_BASER, OUTERCACHE, 53, 3) 286 FIELD(GITS_BASER, TYPE, 56, 3) 287 FIELD(GITS_BASER, INNERCACHE, 59, 3) 288 FIELD(GITS_BASER, INDIRECT, 62, 1) 289 FIELD(GITS_BASER, VALID, 63, 1) 290 291 FIELD(GITS_CBASER, SIZE, 0, 8) 292 FIELD(GITS_CBASER, SHAREABILITY, 10, 2) 293 FIELD(GITS_CBASER, PHYADDR, 12, 40) 294 FIELD(GITS_CBASER, OUTERCACHE, 53, 3) 295 FIELD(GITS_CBASER, INNERCACHE, 59, 3) 296 FIELD(GITS_CBASER, VALID, 63, 1) 297 298 FIELD(GITS_CREADR, STALLED, 0, 1) 299 FIELD(GITS_CREADR, OFFSET, 5, 15) 300 301 FIELD(GITS_CWRITER, RETRY, 0, 1) 302 FIELD(GITS_CWRITER, OFFSET, 5, 15) 303 304 FIELD(GITS_CTLR, ENABLED, 0, 1) 305 FIELD(GITS_CTLR, QUIESCENT, 31, 1) 306 307 FIELD(GITS_TYPER, PHYSICAL, 0, 1) 308 FIELD(GITS_TYPER, VIRTUAL, 1, 1) 309 FIELD(GITS_TYPER, ITT_ENTRY_SIZE, 4, 4) 310 FIELD(GITS_TYPER, IDBITS, 8, 5) 311 FIELD(GITS_TYPER, DEVBITS, 13, 5) 312 FIELD(GITS_TYPER, SEIS, 18, 1) 313 FIELD(GITS_TYPER, PTA, 19, 1) 314 FIELD(GITS_TYPER, CIDBITS, 32, 4) 315 FIELD(GITS_TYPER, CIL, 36, 1) 316 FIELD(GITS_TYPER, VMOVP, 37, 1) 317 318 #define GITS_IDREGS 0xFFD0 319 320 #define GITS_BASER_RO_MASK (R_GITS_BASER_ENTRYSIZE_MASK | \ 321 R_GITS_BASER_TYPE_MASK) 322 323 #define GITS_BASER_PAGESIZE_4K 0 324 #define GITS_BASER_PAGESIZE_16K 1 325 #define GITS_BASER_PAGESIZE_64K 2 326 327 #define GITS_BASER_TYPE_DEVICE 1ULL 328 #define GITS_BASER_TYPE_VPE 2ULL 329 #define GITS_BASER_TYPE_COLLECTION 4ULL 330 331 #define GITS_PAGE_SIZE_4K 0x1000 332 #define GITS_PAGE_SIZE_16K 0x4000 333 #define GITS_PAGE_SIZE_64K 0x10000 334 335 #define L1TABLE_ENTRY_SIZE 8 336 337 #define LPI_CTE_ENABLED TABLE_ENTRY_VALID_MASK 338 #define LPI_PRIORITY_MASK 0xfc 339 340 #define GITS_CMDQ_ENTRY_WORDS 4 341 #define GITS_CMDQ_ENTRY_SIZE (GITS_CMDQ_ENTRY_WORDS * sizeof(uint64_t)) 342 343 #define CMD_MASK 0xff 344 345 /* ITS Commands */ 346 #define GITS_CMD_MOVI 0x01 347 #define GITS_CMD_INT 0x03 348 #define GITS_CMD_CLEAR 0x04 349 #define GITS_CMD_SYNC 0x05 350 #define GITS_CMD_MAPD 0x08 351 #define GITS_CMD_MAPC 0x09 352 #define GITS_CMD_MAPTI 0x0A 353 #define GITS_CMD_MAPI 0x0B 354 #define GITS_CMD_INV 0x0C 355 #define GITS_CMD_INVALL 0x0D 356 #define GITS_CMD_MOVALL 0x0E 357 #define GITS_CMD_DISCARD 0x0F 358 #define GITS_CMD_VMOVI 0x21 359 #define GITS_CMD_VMOVP 0x22 360 #define GITS_CMD_VSYNC 0x25 361 #define GITS_CMD_VMAPP 0x29 362 #define GITS_CMD_VMAPTI 0x2A 363 #define GITS_CMD_VMAPI 0x2B 364 #define GITS_CMD_VINVALL 0x2D 365 366 /* MAPC command fields */ 367 #define ICID_LENGTH 16 368 #define ICID_MASK ((1U << ICID_LENGTH) - 1) 369 FIELD(MAPC, RDBASE, 16, 32) 370 371 #define RDBASE_PROCNUM_LENGTH 16 372 #define RDBASE_PROCNUM_MASK ((1ULL << RDBASE_PROCNUM_LENGTH) - 1) 373 374 /* MAPD command fields */ 375 #define ITTADDR_LENGTH 44 376 #define ITTADDR_SHIFT 8 377 #define ITTADDR_MASK MAKE_64BIT_MASK(ITTADDR_SHIFT, ITTADDR_LENGTH) 378 #define SIZE_MASK 0x1f 379 380 /* MAPI command fields */ 381 #define EVENTID_MASK ((1ULL << 32) - 1) 382 383 /* MAPTI command fields */ 384 #define pINTID_SHIFT 32 385 #define pINTID_MASK MAKE_64BIT_MASK(32, 32) 386 387 #define DEVID_SHIFT 32 388 #define DEVID_MASK MAKE_64BIT_MASK(32, 32) 389 390 #define VALID_SHIFT 63 391 #define CMD_FIELD_VALID_MASK (1ULL << VALID_SHIFT) 392 #define L2_TABLE_VALID_MASK CMD_FIELD_VALID_MASK 393 #define TABLE_ENTRY_VALID_MASK (1ULL << 0) 394 395 /* MOVALL command fields */ 396 FIELD(MOVALL_2, RDBASE1, 16, 36) 397 FIELD(MOVALL_3, RDBASE2, 16, 36) 398 399 /* MOVI command fields */ 400 FIELD(MOVI_0, DEVICEID, 32, 32) 401 FIELD(MOVI_1, EVENTID, 0, 32) 402 FIELD(MOVI_2, ICID, 0, 16) 403 404 /* INV command fields */ 405 FIELD(INV_0, DEVICEID, 32, 32) 406 FIELD(INV_1, EVENTID, 0, 32) 407 408 /* VMAPI, VMAPTI command fields */ 409 FIELD(VMAPTI_0, DEVICEID, 32, 32) 410 FIELD(VMAPTI_1, EVENTID, 0, 32) 411 FIELD(VMAPTI_1, VPEID, 32, 16) 412 FIELD(VMAPTI_2, VINTID, 0, 32) /* VMAPTI only */ 413 FIELD(VMAPTI_2, DOORBELL, 32, 32) 414 415 /* VMAPP command fields */ 416 FIELD(VMAPP_0, ALLOC, 8, 1) /* GICv4.1 only */ 417 FIELD(VMAPP_0, PTZ, 9, 1) /* GICv4.1 only */ 418 FIELD(VMAPP_0, VCONFADDR, 16, 36) /* GICv4.1 only */ 419 FIELD(VMAPP_1, DEFAULT_DOORBELL, 0, 32) /* GICv4.1 only */ 420 FIELD(VMAPP_1, VPEID, 32, 16) 421 FIELD(VMAPP_2, RDBASE, 16, 36) 422 FIELD(VMAPP_2, V, 63, 1) 423 FIELD(VMAPP_3, VPTSIZE, 0, 8) /* For GICv4.0, bits [7:6] are RES0 */ 424 FIELD(VMAPP_3, VPTADDR, 16, 36) 425 426 /* VMOVP command fields */ 427 FIELD(VMOVP_0, SEQNUM, 32, 16) /* not used for GITS_TYPER.VMOVP == 1 */ 428 FIELD(VMOVP_1, ITSLIST, 0, 16) /* not used for GITS_TYPER.VMOVP == 1 */ 429 FIELD(VMOVP_1, VPEID, 32, 16) 430 FIELD(VMOVP_2, RDBASE, 16, 36) 431 FIELD(VMOVP_2, DB, 63, 1) /* GICv4.1 only */ 432 FIELD(VMOVP_3, DEFAULT_DOORBELL, 0, 32) /* GICv4.1 only */ 433 434 /* VMOVI command fields */ 435 FIELD(VMOVI_0, DEVICEID, 32, 32) 436 FIELD(VMOVI_1, EVENTID, 0, 32) 437 FIELD(VMOVI_1, VPEID, 32, 16) 438 FIELD(VMOVI_2, D, 0, 1) 439 FIELD(VMOVI_2, DOORBELL, 32, 32) 440 441 /* VINVALL command fields */ 442 FIELD(VINVALL_1, VPEID, 32, 16) 443 444 /* 445 * 12 bytes Interrupt translation Table Entry size 446 * as per Table 5.3 in GICv3 spec 447 * ITE Lower 8 Bytes 448 * Bits: | 63 ... 48 | 47 ... 32 | 31 ... 26 | 25 ... 2 | 1 | 0 | 449 * Values: | vPEID | ICID | unused | IntNum | IntType | Valid | 450 * ITE Higher 4 Bytes 451 * Bits: | 31 ... 25 | 24 ... 0 | 452 * Values: | unused | Doorbell | 453 * (When Doorbell is unused, as it always is for INTYPE_PHYSICAL, 454 * the value of that field in memory cannot be relied upon -- older 455 * versions of QEMU did not correctly write to that memory.) 456 */ 457 #define ITS_ITT_ENTRY_SIZE 0xC 458 459 FIELD(ITE_L, VALID, 0, 1) 460 FIELD(ITE_L, INTTYPE, 1, 1) 461 FIELD(ITE_L, INTID, 2, 24) 462 FIELD(ITE_L, ICID, 32, 16) 463 FIELD(ITE_L, VPEID, 48, 16) 464 FIELD(ITE_H, DOORBELL, 0, 24) 465 466 /* Possible values for ITE_L INTTYPE */ 467 #define ITE_INTTYPE_VIRTUAL 0 468 #define ITE_INTTYPE_PHYSICAL 1 469 470 /* 16 bits EventId */ 471 #define ITS_IDBITS GICD_TYPER_IDBITS 472 473 /* 16 bits DeviceId */ 474 #define ITS_DEVBITS 0xF 475 476 /* 16 bits CollectionId */ 477 #define ITS_CIDBITS 0xF 478 479 /* 480 * 8 bytes Device Table Entry size 481 * Valid = 1 bit,ITTAddr = 44 bits,Size = 5 bits 482 */ 483 #define GITS_DTE_SIZE (0x8ULL) 484 485 FIELD(DTE, VALID, 0, 1) 486 FIELD(DTE, SIZE, 1, 5) 487 FIELD(DTE, ITTADDR, 6, 44) 488 489 /* 490 * 8 bytes Collection Table Entry size 491 * Valid = 1 bit, RDBase = 16 bits 492 */ 493 #define GITS_CTE_SIZE (0x8ULL) 494 FIELD(CTE, VALID, 0, 1) 495 FIELD(CTE, RDBASE, 1, RDBASE_PROCNUM_LENGTH) 496 497 /* 498 * 8 bytes VPE table entry size: 499 * Valid = 1 bit, VPTsize = 5 bits, VPTaddr = 36 bits, RDbase = 16 bits 500 * 501 * Field sizes for Valid and size are mandated; field sizes for RDbase 502 * and VPT_addr are IMPDEF. 503 */ 504 #define GITS_VPE_SIZE 0x8ULL 505 506 FIELD(VTE, VALID, 0, 1) 507 FIELD(VTE, VPTSIZE, 1, 5) 508 FIELD(VTE, VPTADDR, 6, 36) 509 FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH) 510 511 /* Special interrupt IDs */ 512 #define INTID_SECURE 1020 513 #define INTID_NONSECURE 1021 514 #define INTID_SPURIOUS 1023 515 516 /* Functions internal to the emulated GICv3 */ 517 518 /** 519 * gicv3_redist_size: 520 * @s: GICv3State 521 * 522 * Return the size of the redistributor register frame in bytes 523 * (which depends on what GIC version this is) 524 */ 525 static inline int gicv3_redist_size(GICv3State *s) 526 { 527 /* 528 * Redistributor size is controlled by the redistributor GICR_TYPER.VLPIS. 529 * It's the same for every redistributor in the GIC, so arbitrarily 530 * use the register field in the first one. 531 */ 532 if (s->cpu[0].gicr_typer & GICR_TYPER_VLPIS) { 533 return GICV4_REDIST_SIZE; 534 } else { 535 return GICV3_REDIST_SIZE; 536 } 537 } 538 539 /** 540 * gicv3_intid_is_special: 541 * @intid: interrupt ID 542 * 543 * Return true if @intid is a special interrupt ID (1020 to 544 * 1023 inclusive). This corresponds to the GIC spec pseudocode 545 * IsSpecial() function. 546 */ 547 static inline bool gicv3_intid_is_special(int intid) 548 { 549 return intid >= INTID_SECURE && intid <= INTID_SPURIOUS; 550 } 551 552 /** 553 * gicv3_redist_update: 554 * @cs: GICv3CPUState for this redistributor 555 * 556 * Recalculate the highest priority pending interrupt after a 557 * change to redistributor state, and inform the CPU accordingly. 558 */ 559 void gicv3_redist_update(GICv3CPUState *cs); 560 561 /** 562 * gicv3_update: 563 * @s: GICv3State 564 * @start: first interrupt whose state changed 565 * @len: length of the range of interrupts whose state changed 566 * 567 * Recalculate the highest priority pending interrupts after a 568 * change to the distributor state affecting @len interrupts 569 * starting at @start, and inform the CPUs accordingly. 570 */ 571 void gicv3_update(GICv3State *s, int start, int len); 572 573 /** 574 * gicv3_full_update_noirqset: 575 * @s: GICv3State 576 * 577 * Recalculate the cached information about highest priority 578 * pending interrupts, but don't inform the CPUs. This should be 579 * called after an incoming migration has loaded new state. 580 */ 581 void gicv3_full_update_noirqset(GICv3State *s); 582 583 /** 584 * gicv3_full_update: 585 * @s: GICv3State 586 * 587 * Recalculate the highest priority pending interrupts after 588 * a change that could affect the status of all interrupts, 589 * and inform the CPUs accordingly. 590 */ 591 void gicv3_full_update(GICv3State *s); 592 MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, 593 unsigned size, MemTxAttrs attrs); 594 MemTxResult gicv3_dist_write(void *opaque, hwaddr addr, uint64_t data, 595 unsigned size, MemTxAttrs attrs); 596 MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, 597 unsigned size, MemTxAttrs attrs); 598 MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, 599 unsigned size, MemTxAttrs attrs); 600 void gicv3_dist_set_irq(GICv3State *s, int irq, int level); 601 void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level); 602 void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level); 603 /** 604 * gicv3_redist_process_vlpi: 605 * @cs: GICv3CPUState 606 * @irq: (virtual) interrupt number 607 * @vptaddr: (guest) address of VLPI table 608 * @doorbell: doorbell (physical) interrupt number (1023 for "no doorbell") 609 * @level: level to set @irq to 610 * 611 * Process a virtual LPI being directly injected by the ITS. This function 612 * will update the VLPI table specified by @vptaddr and @vptsize. If the 613 * vCPU corresponding to that VLPI table is currently running on 614 * the CPU associated with this redistributor, directly inject the VLPI 615 * @irq. If the vCPU is not running on this CPU, raise the doorbell 616 * interrupt instead. 617 */ 618 void gicv3_redist_process_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr, 619 int doorbell, int level); 620 /** 621 * gicv3_redist_vlpi_pending: 622 * @cs: GICv3CPUState 623 * @irq: (virtual) interrupt number 624 * @level: level to set @irq to 625 * 626 * Set/clear the pending status of a virtual LPI in the vLPI table 627 * that this redistributor is currently using. (The difference between 628 * this and gicv3_redist_process_vlpi() is that this is called from 629 * the cpuif and does not need to do the not-running-on-this-vcpu checks.) 630 */ 631 void gicv3_redist_vlpi_pending(GICv3CPUState *cs, int irq, int level); 632 633 void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level); 634 /** 635 * gicv3_redist_update_lpi: 636 * @cs: GICv3CPUState 637 * 638 * Scan the LPI pending table and recalculate the highest priority 639 * pending LPI and also the overall highest priority pending interrupt. 640 */ 641 void gicv3_redist_update_lpi(GICv3CPUState *cs); 642 /** 643 * gicv3_redist_update_lpi_only: 644 * @cs: GICv3CPUState 645 * 646 * Scan the LPI pending table and recalculate cs->hpplpi only, 647 * without calling gicv3_redist_update() to recalculate the overall 648 * highest priority pending interrupt. This should be called after 649 * an incoming migration has loaded new state. 650 */ 651 void gicv3_redist_update_lpi_only(GICv3CPUState *cs); 652 /** 653 * gicv3_redist_inv_lpi: 654 * @cs: GICv3CPUState 655 * @irq: LPI to invalidate cached information for 656 * 657 * Forget or update any cached information associated with this LPI. 658 */ 659 void gicv3_redist_inv_lpi(GICv3CPUState *cs, int irq); 660 /** 661 * gicv3_redist_inv_vlpi: 662 * @cs: GICv3CPUState 663 * @irq: vLPI to invalidate cached information for 664 * @vptaddr: (guest) address of vLPI table 665 * 666 * Forget or update any cached information associated with this vLPI. 667 */ 668 void gicv3_redist_inv_vlpi(GICv3CPUState *cs, int irq, uint64_t vptaddr); 669 /** 670 * gicv3_redist_mov_lpi: 671 * @src: source redistributor 672 * @dest: destination redistributor 673 * @irq: LPI to update 674 * 675 * Move the pending state of the specified LPI from @src to @dest, 676 * as required by the ITS MOVI command. 677 */ 678 void gicv3_redist_mov_lpi(GICv3CPUState *src, GICv3CPUState *dest, int irq); 679 /** 680 * gicv3_redist_movall_lpis: 681 * @src: source redistributor 682 * @dest: destination redistributor 683 * 684 * Scan the LPI pending table for @src, and for each pending LPI there 685 * mark it as not-pending for @src and pending for @dest, as required 686 * by the ITS MOVALL command. 687 */ 688 void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest); 689 /** 690 * gicv3_redist_mov_vlpi: 691 * @src: source redistributor 692 * @src_vptaddr: (guest) address of source VLPI table 693 * @dest: destination redistributor 694 * @dest_vptaddr: (guest) address of destination VLPI table 695 * @irq: VLPI to update 696 * @doorbell: doorbell for destination (1023 for "no doorbell") 697 * 698 * Move the pending state of the specified VLPI from @src to @dest, 699 * as required by the ITS VMOVI command. 700 */ 701 void gicv3_redist_mov_vlpi(GICv3CPUState *src, uint64_t src_vptaddr, 702 GICv3CPUState *dest, uint64_t dest_vptaddr, 703 int irq, int doorbell); 704 /** 705 * gicv3_redist_vinvall: 706 * @cs: GICv3CPUState 707 * @vptaddr: address of VLPI pending table 708 * 709 * On redistributor @cs, invalidate all cached information associated 710 * with the vCPU defined by @vptaddr. 711 */ 712 void gicv3_redist_vinvall(GICv3CPUState *cs, uint64_t vptaddr); 713 714 void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); 715 void gicv3_init_cpuif(GICv3State *s); 716 717 /** 718 * gicv3_cpuif_update: 719 * @cs: GICv3CPUState for the CPU to update 720 * 721 * Recalculate whether to assert the IRQ or FIQ lines after a change 722 * to the current highest priority pending interrupt, the CPU's 723 * current running priority or the CPU's current exception level or 724 * security state. 725 */ 726 void gicv3_cpuif_update(GICv3CPUState *cs); 727 728 /* 729 * gicv3_cpuif_virt_irq_fiq_update: 730 * @cs: GICv3CPUState for the CPU to update 731 * 732 * Recalculate whether to assert the virtual IRQ or FIQ lines after 733 * a change to the current highest priority pending virtual interrupt. 734 * Note that this does not recalculate and change the maintenance 735 * interrupt status (for that, see gicv3_cpuif_virt_update()). 736 */ 737 void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs); 738 739 static inline uint32_t gicv3_iidr(void) 740 { 741 /* Return the Implementer Identification Register value 742 * for the emulated GICv3, as reported in GICD_IIDR and GICR_IIDR. 743 * 744 * We claim to be an ARM r0p0 with a zero ProductID. 745 * This is the same as an r0p0 GIC-500. 746 */ 747 return 0x43b; 748 } 749 750 /* CoreSight PIDR0 values for ARM GICv3 implementations */ 751 #define GICV3_PIDR0_DIST 0x92 752 #define GICV3_PIDR0_REDIST 0x93 753 #define GICV3_PIDR0_ITS 0x94 754 755 static inline uint32_t gicv3_idreg(GICv3State *s, int regoffset, uint8_t pidr0) 756 { 757 /* Return the value of the CoreSight ID register at the specified 758 * offset from the first ID register (as found in the distributor 759 * and redistributor register banks). 760 * These values indicate an ARM implementation of a GICv3 or v4. 761 */ 762 static const uint8_t gicd_ids[] = { 763 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x0B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 764 }; 765 uint32_t id; 766 767 regoffset /= 4; 768 769 if (regoffset == 4) { 770 return pidr0; 771 } 772 id = gicd_ids[regoffset]; 773 if (regoffset == 6) { 774 /* PIDR2 bits [7:4] are the GIC architecture revision */ 775 id |= s->revision << 4; 776 } 777 return id; 778 } 779 780 /** 781 * gicv3_irq_group: 782 * 783 * Return the group which this interrupt is configured as (GICV3_G0, 784 * GICV3_G1 or GICV3_G1NS). 785 */ 786 static inline int gicv3_irq_group(GICv3State *s, GICv3CPUState *cs, int irq) 787 { 788 bool grpbit, grpmodbit; 789 790 if (irq < GIC_INTERNAL) { 791 grpbit = extract32(cs->gicr_igroupr0, irq, 1); 792 grpmodbit = extract32(cs->gicr_igrpmodr0, irq, 1); 793 } else { 794 grpbit = gicv3_gicd_group_test(s, irq); 795 grpmodbit = gicv3_gicd_grpmod_test(s, irq); 796 } 797 if (grpbit) { 798 return GICV3_G1NS; 799 } 800 if (s->gicd_ctlr & GICD_CTLR_DS) { 801 return GICV3_G0; 802 } 803 return grpmodbit ? GICV3_G1 : GICV3_G0; 804 } 805 806 /** 807 * gicv3_redist_affid: 808 * 809 * Return the 32-bit affinity ID of the CPU connected to this redistributor 810 */ 811 static inline uint32_t gicv3_redist_affid(GICv3CPUState *cs) 812 { 813 return cs->gicr_typer >> 32; 814 } 815 816 /** 817 * gicv3_cache_target_cpustate: 818 * 819 * Update the cached CPU state corresponding to the target for this interrupt 820 * (which is kept in s->gicd_irouter_target[]). 821 */ 822 static inline void gicv3_cache_target_cpustate(GICv3State *s, int irq) 823 { 824 GICv3CPUState *cs = NULL; 825 int i; 826 uint32_t tgtaff = extract64(s->gicd_irouter[irq], 0, 24) | 827 extract64(s->gicd_irouter[irq], 32, 8) << 24; 828 829 for (i = 0; i < s->num_cpu; i++) { 830 if (s->cpu[i].gicr_typer >> 32 == tgtaff) { 831 cs = &s->cpu[i]; 832 break; 833 } 834 } 835 836 s->gicd_irouter_target[irq] = cs; 837 } 838 839 /** 840 * gicv3_cache_all_target_cpustates: 841 * 842 * Populate the entire cache of CPU state pointers for interrupt targets 843 * (eg after inbound migration or CPU reset) 844 */ 845 static inline void gicv3_cache_all_target_cpustates(GICv3State *s) 846 { 847 int irq; 848 849 for (irq = GIC_INTERNAL; irq < GICV3_MAXIRQ; irq++) { 850 gicv3_cache_target_cpustate(s, irq); 851 } 852 } 853 854 void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s); 855 856 #endif /* QEMU_ARM_GICV3_INTERNAL_H */ 857